Layout guide for EMC1
PCB design techniques for EMC compliance
PCB design techniques
for EMC compliance
1. Placement rule.
2. Trace routing rule.
3. Stack up rule.
4. The other Layout guide.
PCB design techniques
for EMC compliance
1. Placement rule.
2. Trace routing rule.
3. Stack up rule.
4. The other Layout guide.
Placement rule
1 IC , Clock generator , CPU , VGA Chip North bridge Chip Layout , trace 離 2Clock generator CPU GND Layer
(例 : CLK generator CPU Top Layer , Layer-2
GND Layer).
Placement rule
3Placement , Power Plane , IC 連 , 度切 離
4 Output control IC Output port Connector, Filter Output port Connector
Placement rule
5Clock generator 切 留螺 ,若 留 , 螺 GND Layer 切 , 螺 floating ,不 6PCB 螺 , 5 ~ 7cm 螺 ( 數 λ/20rule ).
λ/20 率 1.04m 0.61m 0.45m 0.23m 0.15m 0.11m 7.5cm 6.5cm 3.0cm 1.5cm
14.318
24.576
33
65
100
133
200
230
500
1000λ/20 Wavelength Distance Frequency of Interest (MHz)
PCB design techniques
for EMC compliance
1. Placement rule.
2. Trace routing rule.
3. Stack up rule.
4. The other Layout guide.
Trace routing rule(for CLK&High Speed Bus)
1 High Speed CLK trace(≥8MHz) , GND Layer
若 , trace Layout GND Layer.
2Clock trace 不 Via,不 3 ,
CPU , 量CPU CLK SDRAM CLK impedance match , Layout 2 Via .
Trace routing rule (for CLK&High Speed Bus)
3High Speed Clock GND trace, GND trace 1~1.5cm GND Via GND Plane.a.若GND Via ,不 離 , 更 .
b. GND Via 切 control IC Pin Bypass .( )
4All Clock trace 3W rule
若 3 行 3W 度 Clock crosstalk.
Application of the 3-W rule
a. For the via :
Clock via 兩 Clock trace ≥1W 離
Application of the 3-W rule
b. Between both trace :
兩 Clock trace ≥2W 離
Trace routing rule (for CLK&High Speed Bus)5High Speed Clock trace , 不 moat ; 若 Vcc , 不 , 不
6High Speed Clock trace ,不 IC ( Top Layer Bottom Layer)
Trace routing rule (for CLK&High Speed Bus)7 流 power trace , 離High speed Clock trace
8Clock trace trace
PCB design techniques
for EMC compliance
1. Placement rule.
2. Trace routing rule.
3. Stack up rule.
4. The other Layout guide.
Stack up rule
(1) Power and Ground Layer , PCB
(2) /
(3) crosstalk
(4) 說 :
Stack up rule
110 Layers for 6 signal Layers : (3-GND/1-Vcc)
Stack up rule
28 Layers for 5 signal Layers : (2-GND/1-Vcc)