DDR4_SDRAM_Controller_Core

DDR4_SDRAM_Controller_Core

Block Diagram

Product Highlights

? Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support

? Minimal latency achieved via pa-rameterized pipelining ? Achieves high clock rates with minimal routing constraints ? Supports half-rate and quarter-rate clock operation ? Full run-time configurable timing parameters and memory settings ? Supports all DDR4 operating modes ? DFI 3.0 Compatible

? Full set of Add-On Cores available ? Delivered fully integrated and verified with target DDR PHY ? Minimal ASIC gate count ? Broad range of ASIC and FPGA platforms supported ? Source code available ? Customization and Integration services available

Product Overview

Bank

Management

Bank Management Refresh Control

dfi_cke[7:0]

dfi_ras_n

dfi_cas_n dfi_we_n

Initialization Control

Address Generation

dfi_addr[15:0]dfi_ba[3:0]dfi_cs_n[7:0]reset_n

Config Ports

l_addr[36:0]

l_b_size l_r_req l_w_req l_busy

l_d_req l_r_valid

l_auto_pch

DDR4 SDRAM Controller Core

DDR Data Control

l_datain[2n-1:0]l_dataout[2n-1:0]

l_dm_in[2n/8-1:0]dfi_wrdata_data_h/l[n-1:0]dfi_wrdata_en Control and Timing

Queue Control

dfi_rddata_h/l[n-1:0]

dfi_odt dfi_act_n

dfi_rddata_en sd_cke[7:0]sd_ras_n

sd_cas_n sd_we_n sd_odt[7:0]sd_a[15:0]sd_ba[3:0]sd_cs_n[7:0]

sd_dq[n-1:0]sd_dm[n/8-1:0]

sd_dqs[n/8-1:0]sd_dqs_n[n/8-1:0]

sd_clk_out_p[m-1:0]

sd_clk_out_n[m-1:0]

dfi_reset_n sd_reset_n Clock Synthesis Module

1x

phy clocks

A S I C / S t r u c t u r e d A S I C P H Y

Multi-Burst (optional)

dfi_rddata_valid

sd_act_n

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