M88141Y-15T6T中文资料

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DATA BRIEFING

June 2000

Complete data available on Data-on-Disc CD-ROM or at https://www.360docs.net/doc/182731936.html,

M88FAMILY

In-System Programmable (ISP)Multiple-Memory and Logic FLASH+PSD Systems (with CPLD)for MCUs

Single Supply Voltage:–5V ±10%for M88xxFxY

–3V (+20/–10%)for M88xxFxW

1or 2Mbit of Primary Flash Memory (8uniform sectors,16K x 8,or 32K x 8)

A second non-volatile memory:

–256Kbit (32K x 8)EEPROM (for M8813F1x)or Flash memory (for M88x3F2x)–4uniform sectors (8K x 8)

s SRAM (16Kbit,2K x 8;or 64Kbit,8K x 8)s Over 3,000Gates of PLD:DPLD and CPLD s 27Reconfigurable I/O ports s Enhanced JTAG Serial Port

s Programmable power management s

Stand-by current:

–50μA for M88xxFxY –25μA for M88xxFxW s

High Endurance:

–100,000Erase/Write Cycles of Flash Memory –10,000Erase/Write Cycles of EEPROM –1,000Erase/Write Cycles of PLD

DESCRIPTION

The FLASH+PSD family of memory systems for microcontrollers (MCUs)brings In-System-Figure 1.Logic Diagram

AI02856

AD0-AD15

PC0-PC7

V CC

FLASH+PSD

V SS

PD0-PD23

PB0-PB7

PA0-PA7

CNTL0- CNTL2

RESET

Table 1.Signal Names

PA0-PA7Port-A PB0-PB7Port-B PC0-PC7

Port-C

PC2=Voltage Stand-by

PD0-PD2Port-D AD0-AD15Address/Data CNTL0-CNTL2Control RESET Reset

V CC Supply Voltage V SS Ground

PLCC52(K)

PQFP52(T)

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Figure 2A.PLCC Connections

P B 0

P B 1

P B 2

P B 3

P B 4

P B 5

G N D

P B 6

P B 7

C N T L 1

C N T L 2

R E S E T

C N T L 0

P A 7

P A 6

P A 5

P A 4

P A 3

G N D

P A 2

P A 1

P A 0

A D 0

A D 1

A D 2

A D 3

AD15AD14AD13AD12AD11AD10AD9AD8VCC AD7AD6AD5AD4

PD2PD1PD0PC7PC6PC5PC4VCC GND PC3PC2PC1PC0

89101112131415161718192046454443424140393837363534

AI02857

Figure 2B.PQFP Connections

39AD15 38AD14 37AD13 36AD12 35AD11 34AD10 33AD9 32AD8 31V CC 30AD7 29AD6 28AD5 27AD4

PD2 PD1 PD0 PC7 PC6 PC5 PC4 V CC GND PC3 PC2 PC1 PC0

1 2 3 4 5 6 7 8 9 10 11 12 13

52 51 50 49 48 47 46 45 44 43 42 41 40P B 0

P B 1

P B 2

P B 3

P B 4

P B 5

G N D

P B 6

P B 7

C N T L 1

C N T L 2

R E S E T

C N T L O

22 23

P A 7 P A 6 P A 5 P A 4 P A 3 G N D P A 2 P A 1 P A 0 A D 0 A D 1 A D 2 A D 3AI02858

Table 2.Product Range 1

Note:1.All products support:JTAG serial ISP,MCU parallel ISP,ISP Flash memory,ISP CPLD,Security features,Power Management

Unit (PMU),Automatic Power-down (APD)

2.SRAM may be backed up using an external battery.

Part Number Primary Flash Memory

Secondary NVM SRAM 2I/O Ports Voltage Range

Access Time

M8813F1Y 1Mbit 256Kbit EEPROM 16Kbit 27 4.5-5.5V

90ns or 150ns M8813F2Y 1Mbit 256Kbit Flash memory 16Kbit 27M8834F2Y 2Mbit 256Kbit Flash memory 64Kbit 27M8813F1W 1Mbit 256Kbit EEPROM 16Kbit 27 2.7-3.6V

150ns

M8813F2W 1Mbit 256Kbit Flash memory 16Kbit 27M8834F2W

2Mbit

256Kbit Flash memory

64Kbit

Programmability (ISP)to Flash memory and

programmable logic.The result is a simple and flexible solution for embedded designs.FLASH+PSD devices combine many of the peripheral functions found in MCU based applications.FLASH+PSD provides a glueless interface to most commonly-used ROMless MCUs.

Table 2summarizes all the devices in the M88Family.

The CPLD in the FLASH+PSD devices features an optimized Macrocell logic architecture.The Macrocell was created to address the unique requirements of embedded system designs.It allows direct connection between the system address/data bus,and the internal FLASH+PSD

registers,to simplify communication between the MCU and other supporting devices.

The FLASH+PSD device includes a JTAG Serial Programming interface,to allow In-System Programming (ISP)of the entire device.This feature reduces development time,simplifies the manufacturing flow,and dramatically lowers the cost of field https://www.360docs.net/doc/182731936.html,ing ST’s special Fast-JTAG programming,a design can be rapidly programmed into the FLASH+PSD.

The innovative FLASH+PSD family solves key problems faced by designers when managing discrete Flash memory devices,such as:–Complex address decoding

–In-System (first-time)Programming (ISP)

–Concurrent EEPROM or Flash memory programming (IAP).

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M88FAMILY

Figure 3.FLASH+PSD Block Diagram

P R O G .M C U B U S I N T R F .

A D I O P O R T

C N T L 0,C N T L 1, C N T L 2

A D 0–A D 15

C L K I N (P

D 1)C L K I N C L K I N

P L D I N P U T B U S

P R O G .P O R T

P O R T A

P R O G .P O R T

P O R T B

P O W E R M A N G M T U N I T

1O R 2M B I T P R I M A R Y F L A S H M E M O R Y

8S E C T O R S

V S T D B Y P A 0–P A 7

P B 0–P B 7

P R O G .P O R T

P O R T C

P R O G .P O R T

P O R T D

P C 0–P C 7

P D 0–P D 2

A D D R E S S /D A T A /C O N T R O L

B U S

P O R T A ,B &C

3E X T C S T O P O R T D

24I N P U T M A C R O C E L L S

P O R T A ,B &C

7373256K B I T S E C O N D A R Y E E P R O M o r F L A S H M E M O R Y (B O O T O R D A T A )4S E C T O R S

16O R 64K B I T B A T T E R Y B A C K U P S R A M

R U N T I M E C O N T R O L A N D I /O R E G I S T E R S

S R A M S E L E C T

P E R I P I /O M O D E S E L E C T S

M A C R O C E L L F E E D B A C K O R P O R T I N P U T

C S I O P F L A S H I S P C P L

D (C P L D )

16O U T P U T M A C R O C E L L S

F L A S H D E C O D E P L D (D P L D )

P L D ,C O N F I G U R A T I O N &F L A S H M E M O R Y L O A D E R J T A G S E R I A L C H A N N E L (P C 2)

P A G E R E G I S T E R

E M B E D D E D A L G O R I T H M S E C T O R S E L E C T S S E C T O R S E L E C T S

G L O B A L C O N F I G .&S E C U R I T Y

AI02861D

Sometimes computers try to be too clever for their own good.Take this illustration for instance.Just because so many of the labels are rotated through ninety degrees,FrameMaker seems to want to insist on telling the postscript file that I would find it more convenient to see this page displayed in landscape,rotated by ninety degrees.Well I wouldn’t.So I am putting in all this text just to weight the average in this direction.

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The JTAG Serial Interface block allows In-System Programming (ISP).Embedded dual-bank memories eliminates the need for an external Boot EPROM or Flash memory,or an external programmer.To simplify Flash memory updates,program execution is performed from a secondary Flash memory (for the M88xxF2x)or EEPROM (for the M8813F1x)while the primary Flash memory is being updated.This solution avoids the complicated hardware and software overhead necessary to implement IAP.

ST makes available a software development tool,PSDsoft,that generates ANSI-C compliant code for use with your target MCU.This code allows you to manipulate the non-volatile memory (NVM)within the FLASH+PSD.Code examples are also provided for:

–Flash memory IAP via the UART of the host MCU

–Memory paging to execute code across several FLASH+PSD memory pages

–Loading,reading,and manipulation of FLASH+PSD Macrocells by the MCU.FLASH+PSD ARCHITECTURAL OVERVIEW FLASH+PSD devices contain several major functional blocks.Figure 3shows the architecture of the M88FLASH+PSD device family.The functions of each block are described briefly in the following sections.Many of the blocks perform multiple functions and are user configurable.Memory

The 1or 2Mbit (128K x 8,or 256K x 8)Flash memory is the primary memory of the FLASH+PSD.It is divided into eight equally-sized sectors that are individually selectable.

The 256Kbit (32K x 8)secondary EEPROM or Flash memory is divided into four equally-sized sectors.Each sector is individually selectable.The SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM.If an external battery is connected to Voltage Stand-by (VSTBY,PC2),data is retained in the event of power failure.

Each sector of memory can be located in a different address space as defined by the user.The access times for all memory types includes the address latching and DPLD decoding time.The M8813F1x has 64bytes of OTP memory for product identifiers,serial numbers,calibration constants,etc..Page Register

The 8-bit Page Register expands the address range of the MCU by up to 256times.The paged address can be used as part of the address space to access external memory and peripherals,or

internal memory and I/O.The Page Register can also be used to change the address mapping of sectors of the Flash memories into different memory spaces for IAP.PLDs

The device contains two PLDs,the Decode PLD (DPLD)and the Complex PLD (CPLD),each optimized for a different function,as shown in Table 3.The functional partitioning of the PLDs reduces power consumption,optimizes cost/performance,and eases design entry.

The DPLD is used to decode addresses and to generate Sector Select signals for the FLASH+PSD internal memory and registers.The DPLD has 17combinatorial outputs,which are used to select memory sectors and JTAG.The CPLD has 16Output Macrocells (OMC)and 3combinatorial outputs.The CPLD also has 24Input Macrocells (IMC)that can be configured as inputs to the PLDs.The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations,number of product terms,and Macrocells.

The PLDs consume minimal power.The speed and power consumption of the PLD is controlled by the Turbo bit in the PMMR0register and other bits in the PMMR2registers.These registers are set by the MCU at run-time.There is a slight penalty to PLD propagation time when invoking the power management features.I/O Ports

The FLASH+PSD has 27individually configurable I/O pins distributed over the four ports (Port A,B,C,and D).Each I/O pin can be individually configured for different functions.Ports can be configured as standard MCU I/O ports,PLD I/O,or latched address outputs for MCUs using multiplexed address/data buses.Ports A and B can be configured to be open drain.

The JTAG pins can be enabled on Port C for In-System Programming (ISP).

Ports A and B can also be configured as a data port for a non-multiplexed bus or multiplexed address/data bus for certain types of 8-bit MCUs.MCU Bus Interface

FLASH+PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed address/data buses.The device is configured to respond to the MCU’s control signals,which are also used as inputs to the PLDs.Where there is a requirement to use a 16-bit data bus to interface to a 16-bit MCU,two PSDs must be used.For examples,please see the full data sheet.

M88FAMILY JTAG Port

In-System Programming(ISP)can be performed

through the JTAG signals on Port C.This serial

interface allows complete programming of the

entire FLASH+PSD device.A blank device can be

completely programmed for the first time after it is

soldered to the board.The JTAG signals(TMS, TCK,TSTAT,TERR,TDI,TDO)can be

multiplexed with other functions on Port C.Table4 indicates the JTAG pin assignments.Four-pin JTAG is also fully supported.

In-System Programming(ISP)

Using the JTAG signals on Port C,the entire

FLASH+PSD device can be programmed or

erased without the use of the MCU.The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory,or SRAM.The secondary memory can be programmed the same way by executing out of the primary Flash memory.The PLD or other FLASH+PSD Configuration blocks can be programmed through the JTAG port or a device insertion programmer.Table5indicates which programming methods can program different functional blocks of the FLASH+PSD.

Power Management Unit(PMU)

The Power Management Unit(PMU)gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD)Unit that turns off device functions during MCU inactivity.The APD Unit has a Power-down mode that helps reduce power consumption.

The FLASH+PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD.The Turbo bit in the PMMR0register can be reset to0and the CPLD latches its outputs and goes to sleep until the next transition on its inputs.

Additionally,bits in the PMMR2register can be set by the MCU to block signals from entering the CPLD to reduce power consumption.Please see the full data sheet for more details.

SECURITY AND NVM SECTOR PROTECTION A security bit in the Protection Register enables the software project,coded in the FLASH+PSD,to be locked up.This bit is only accessible by the system designer from the JTAG serial port,or from a parallel insertion programmer.It cannot be accessed from the MCU.The only way a security bit can be cleared is to erase the entire chip.

The contents of the sectors of the primary and secondary NVM blocks can be protected using bits in the Protection Registers.These bits are accessible from the MCU in the application code, or from a programmer during the set-up procedure.

Table3.PLD I/O

Name Inputs Outputs Product Terms

Decode PLD(DPLD)731742 Complex PLD(CPLD)7319140Table4.JTAG SIgnals on Port C Port C Pins JTAG Signal PC0TMS

PC1TCK

PC3TSTA T

PC4TERR

PC5TDI

PC6TDO

Table5.Methods of Programming Different Functional Blocks of the FLASH+PSD

Functional Block JTAG Programming Device Programmer IAP

Primary Flash Memory Yes Yes Yes

Secondary EEPROM or Flash memory Yes Yes Yes

PLD Array(DPLD and CPLD)Yes Yes No

FLASH+PSD Configuration Yes Yes No

OTP Row No Yes Yes

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ORDERING INFORMATION SCHEME

When delivered from ST,the FLASH+PSD device has all bits in the memory and PLDs set to 1.The FLASH+PSD Configuration Register bits are set to 0.The code,configuration,and PLD logic are loaded using the programming https://www.360docs.net/doc/182731936.html,rmation for programming the device is available directly from ST.Please contact your local sales representative.

The notation used for the device number is as shown in Table 6.For a list of available options (speed,package,etc.)or for further information on any aspect of this device,please see the full data sheet (please consult our pages on the world wide web:https://www.360docs.net/doc/182731936.html,/flashpsd ).Alternatively,please contact your nearest ST Sales Office.

Table 6.Ordering Information Scheme

Note:1.Available on the 4.5to 5.5V range,only.

Example:

M8813F 1W –

SRAM Capacity

Option 116Kbit T

Tape &Reel Packing

64Kbit

Temperature Range

Flash Memory Capacity 10to 70°C (commercial)31Mbit (128K x 8)6

–40to 85°C (industrial)

2Mbit (256K x 8)2nd Non Volatile Memory Package 1256Kbit EEPROM K PLCC522

256Kbit Flash memory T

PQFP52

Operating Voltage Speed Y 4.5V to 5.5V -9090ns 1W

2.7V to

3.6V

-15150ns

M88FAMILY Information furnished is believed to be accurate and reliable.However,STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use.No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics.Specifications mentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

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Australia-Brazil-China-Finland-France-Germany-Hong Kong-India-Italy-Japan-Malaysia-Malta-Morocco-Singapore-Spain-

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