实验四 基于Quartus II的计时电路设计

实验四基于Quartus II的计时电路设计

1、实验要求

顶层电路设计采用原理图输入方法，各电路模块可以采用原理图或硬件描述语言输入方法实现一个简易计时电路。

基本要求：由四个数码管显示的计时电路，低两位按照20进制设计，高两位按照11进制设计。

附加要求1：该计时电路具有校准功能，可以按照1Hz频率校准高两位的显示，可以按10Hz频率校准低两位的显示；附加要求2：高两位的进制可以任意设置；

附加要求3：在计数到达某整点值时例如0300的时刻（该值可以根据老师的要求设置），4盏LED灯一起按照10Hz闪烁5秒钟。

2、实验内容

（1）输出频率1HZ

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY exa4_1 IS PORT(clk:IN STD_LOGIC;

clk_out:OUT STD_LOGIC);

END exa4_1;

ARCHITECTURE fwm OF exa4_1 IS CONSTANT m : INTEGER:= 25000000;

SIGNAL tmp :STD_LOGIC; BEGIN

PROCESS(clk, tmp)

VARIABLE cout : INTEGER:=0;

BEGIN

IF clk'EVENT AND clk='1' THEN cout:=cout+1;

IF cout<=m THEN tmp<='0';

ELSIF cout

ELSE cout:=0;

END IF; END IF;

END PROCESS;

clk_out<=tmp;

END fwm;

（2）输出频率10Hz

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY exa4_2 IS PORT(clk:IN STD_LOGIC;

clk_out:OUT STD_LOGIC);

END exa4_2;

ARCHITECTURE fwm OF exa4_2 IS CONSTANT m : INTEGER:= 2500000; SIGNAL tmp :STD_LOGIC;

BEGIN

PROCESS(clk, tmp)

VARIABLE cout : INTEGER:=0;

BEGIN

IF clk'EVENT AND clk='1' THEN cout:=cout+1;

IF cout<=m THEN tmp<='0';

ELSIF cout

ELSE cout:=0;

END IF;

END IF;

END PROCESS; clk_out<=tmp;

END fwm;

（3）11进制加法计数器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY exa4_3 IS

PORT ( CLK,RST : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));

END exa4_3;

ARCHITECTURE fwm OF exa4_3 IS

SIGNAL Q1 : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN PROCESS(CLK,RST) BEGIN

IF RST = '0' THEN Q1<=(OTHERS => '0');

ELSIF RISING_EDGE(clk) THEN IF Q1<"1010" THEN Q1<=Q1+1; ELSE Q1<=(OTHERS => '0');

END IF;

END IF;

END PROCESS;

DOUT<=Q1 ;

END fwm;

（4）20进制加法计数器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY

exa4_4 IS

PORT ( CLK,RST : IN STD_LOGIC;

DOUT : OUT STD_LOGIC_VECTOR (4 DOWNTO 0));

END exa4_4;

ARCHITECTURE fwm OF exa4_4 IS

SIGNAL Q1 : STD_LOGIC_VECTOR (4 DOWNTO 0); BEGIN PROCESS(CLK,RST) BEGIN

IF RST = '0' THEN Q1<=(OTHERS => '0');

ELSIF RISING_EDGE(clk) THEN IF Q1<"10011" THEN Q1<=Q1+1;

ELSE Q1<=(OTHERS => '0');

END IF;

END IF;

END PROCESS;

DOUT<=Q1 ;

END fwm;

（5）11进制的个位显示

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY exa4_5 IS

PORT (data_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0); dis_out:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END exa4_5;

ARCHITECTURE fwm OF exa4_5 IS BEGIN PROCESS(data_in) BEGIN

CASE data_in IS

WHEN"0000"=>dis_out<="1000000";

WHEN"0001"=>dis_out<="1111001"; WHEN"0010"=>dis_out<="0100100";

WHEN"0011"=>dis_out<="0110000";

WHEN"0100"=>dis_out<="0011001";

WHEN"0101"=>dis_out<="0010010"; WHEN"0110"=>dis_out<="0000010";

WHEN"0111"=>dis_out<="1111000";

WHEN"1000"=>dis_out<="0000000";

WHEN"1001"=>dis_out<="0010000";

WHEN"1010"=>dis_out<="1000000";

WHEN OTHERS=>dis_out<="1111111";

END CASE;

END PROCESS; END fwm;

（6）11进制的十位显示

LIBRARY IEEE;

ENTITY exa4_6 IS PORT (data_in:IN STD_LOGIC_VECTOR(3 DOWNTO 0); dis_out:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END exa4_6;

ARCHITECTURE fwm OF exa4_6 IS BEGIN

PROCESS(data_in) BEGIN

CASE data_in IS

WHEN"0000"=>dis_out<="1000000";

WHEN"0001"=>dis_out<="1000000";

WHEN"0010"=>dis_out<="1000000";

WHEN"0011"=>dis_out<="1000000";

WHEN"0100"=>dis_out<="1000000";

WHEN"0101"=>dis_out<="1000000";

WHEN"0110"=>dis_out<="1000000";

WHEN"0111"=>dis_out<="1000000";

WHEN"1000"=>dis_out<="1000000";

WHEN"1001"=>dis_out<="1000000";

WHEN"1010"=>dis_out<="1111001";

WHEN OTHERS=>dis_out<="1111111";

END CASE;

END PROCESS;

END fwm;

（7）20进制的个位显示

LIBRARY IEEE;

ENTITY exa4_7 IS PORT (data_in:IN STD_LOGIC_VECTOR(4 DOWNTO 0); dis_out:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END exa4_7;

ARCHITECTURE fwm OF exa4_7 IS BEGIN

PROCESS(data_in) BEGIN

CASE data_in IS

WHEN"00000"=>dis_out<="1000000";

WHEN"00001"=>dis_out<="1111001";

WHEN"00010"=>dis_out<="0100100";

WHEN"00011"=>dis_out<="0110000";

WHEN"00100"=>dis_out<="0011001";

WHEN"00101"=>dis_out<="0010010";

WHEN"00110"=>dis_out<="0000010";

WHEN"00111"=>dis_out<="1111000";

WHEN"01000"=>dis_out<="0000000";

WHEN"01001"=>dis_out<="0010000";

WHEN"01010"=>dis_out<="1000000";

WHEN"01011"=>dis_out<="1111001";

WHEN"01100"=>dis_out<="0100100";

WHEN"01101"=>dis_out<="0110000";

WHEN"01110"=>dis_out<="0011001";

WHEN"01111"=>dis_out<="0010010";

WHEN"10000"=>dis_out<="0000010";

WHEN"10001"=>dis_out<="1111000";

WHEN"10010"=>dis_out<="0000000";

WHEN"10011"=>dis_out<="0010000";

WHEN OTHERS=>dis_out<="1111111";

END CASE;

END PROCESS;

END fwm;

（8）20进制的十位显示

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY exa4_8 IS

PORT (data_in:IN STD_LOGIC_VECTOR(4 DOWNTO 0); dis_out:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END exa4_8;

ARCHITECTURE fwm OF exa4_8 IS BEGIN

PROCESS(data_in) BEGIN

CASE data_in IS

WHEN"00000"=>dis_out<="1000000";

WHEN"00001"=>dis_out<="1000000";

WHEN"00010"=>dis_out<="1000000";

WHEN"00011"=>dis_out<="1000000";

WHEN"00100"=>dis_out<="1000000";

WHEN"00101"=>dis_out<="1000000";

WHEN"00110"=>dis_out<="1000000";

WHEN"00111"=>dis_out<="1000000";

WHEN"01000"=>dis_out<="1000000";

WHEN"01001"=>dis_out<="1000000";

WHEN"01010"=>dis_out<="1111001";

WHEN"01011"=>dis_out<="1111001"; WHEN"01100"=>dis_out<="1111001";

WHEN"01101"=>dis_out<="1111001"; WHEN"01110"=>dis_out<="1111001";

WHEN"01111"=>dis_out<="1111001";

WHEN"10000"=>dis_out<="1111001";

WHEN"10001"=>dis_out<="1111001"; WHEN"10010"=>dis_out<="1111001";

WHEN"10011"=>dis_out<="1111001";

WHEN OTHERS=>dis_out<="1111111";

END CASE;

END PROCESS;

END fwm;

3、实验结果

原理图

4实验总结

通过此次试验，学习掌握了通过各模块原理图实现一个功能电路（简易计时电路）。在实验过程中遇见了许多与前几节课类似的问题，进一步加强了自己对QuartuaII软件的使用。