A 5-GHz BiCMOS variable-gain low noise amplifier with inductorless low-gain branch

A 5-GHz BiCMOS Variable-gain Low Noise Amplifier with Inductorless Low-gain Branch

Mingxu Liu(1,2) and Jan Craninckx(1)

(1) IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium.

(2) Also PhD student at Department ELEC-ETRO, Vrije Universiteit Brussel, Belgium.

Mingxu.Liu@imec.be, Jan.Craninckx@imec.be

Abstract:

A 5-GHz variable-gain low noise amplifier without using an excess inductor in its low-gain mode has been demonstrated. When the LNA’s gain is reduced from 16.3 d

B to 5.8 dB, its IIP3 is improved from –7.8 dBm to +1.1 dBm and current consumption is reduced from 3 mA to 2 mA. The noise figures in the high- and low-gain modes are 3.5 dB and 8.3 dB, respectively. Input and output impedance matching are well maintained in both modes. The amplifier is also unconditionally stable from 100 MHz to 10 GHz.

1. Introduction

The Low-Noise Amplifier (LNA) is a crucial part in a receiver because it is the first active circuit in the signal path. For the weakest signal, an LNA must exhibit sufficiently low noise figure (NF) in order to maintain signal-to-noise ratio (SNR). M oreover, when a strong interference exists or the wanted signal itself goes up to a very high power level, the complete receiver must be able to handle them without generating severe distortions. Part of a common solution to this problem is to design a variable-gain LNA that can switch into a low- gain mode when strong interferences exist. The reduced gain improves the cascaded third-order input intercept point (IIP3) of the whole receiver. However, the intrinsic linearity of the LNA is not improved for some variable-gain techniques, which puts a final limitation on the linearity performance of the receiver.

There are a few approaches for variable-gain LNA design. Variable load impedance technique [1] and current steering technique [2] do not change input transistors and their biasing in low-gain modes, so they do not improve power consumption and intrinsic linearity of the LNAs in their low-gain modes. Although there has been attempt to reduce current consumption in low-gain modes for current steering technique, the LNA’s NF and input impedance matching are deteriorated dramatically [3]. The only way to achieve better IIP3 and lower power dissipation in low-gain modes is to design a separate low-gain branch. The low- gain branch can be an emitter follower or source follower [4] but it shows a negative gain which may not be desirable. An inductively degenerated common-emitter low-gain branch [5] can provide a positive gain but the excess inductor occupies a lot of silicon area.

This paper describes a 5-GHz variable-gain LNA using an inductorless low-gain branch. While still providing a positive gain in its low-gain mode, the LNA exhibits significant IIP3 improvement and reduced DC current. Good input and output impedance matching are maintained in both gain modes, which is also a challenge at 5 GHz. The LNA features ESD protection diodes at its RF input/output and is unconditionally stable even though evaluated on a PCB.

2. Circuit Analysis

Figure 1 shows the well-known current-steering technique for variable-gain amplifier design. In the high- gain mode, Q2b is off, so all the current from the input transistor Q1 goes through the cascode transistor Q2a to the output. When Q2b is turned on, a fraction of the current from Q1 will run through Q2b to the power supply such that the gain of the amplifier is reduced.

The drawback of current steering technique is that the LNA’s intrinsic linearity is unchanged because the intrinsic linearity is determined by the input transistor Q1, degeneration inductor L e and biasing current, all of which stay the same in both gain modes. The LNA’s power consumption does not get any reduction in its low-gain mode either. It consumes in its low-gain mode as

much DC current as in its high-gain mode. Although the Figure 1: Current steering technique for variable-gain

LNAs.

Proceedings of ESSCIRC,Grenoble,France,2005

DC current can be lowered in the low-gain mode, the input impedance and noise performance of the LNA, which are highly dependent on biasing, will change such that the NF and S 11 will be deteriorated significantly [3]. Even though the biasing current is kept unchanged, the LNA will still get NF degradation when switching into its low-gain mode because both Q 2a and Q 2b see a very low impedance at their emitters such that their noise contribution is not negligible.

To improve linearity and power consumption in low-gain modes, the topology in Figure 2 can be employed. In the low-gain mode, there is an excess inductor L eLG besides L e to degenerate the input transistor Q 1b such that a lower gain and a higher IIP3 can be achieved at a lower biasing current [5], but the penalty is that the excess inductor L eLG occupies much silicon area.

To eliminate the excess inductor L eLG in Figure 2, a new approach has been developed as shown in Figure 3. Q 1a ,Q 2a and L e form the high-gain branch while the low-gain branch consists of Q 1b ,Q 2b ,R 1,R 2,C d and C m . The two modes share the same base inductor L b . Biasing voltage V Ctrl1a and V Ctrl1b are the controlling voltages to turn on/off Q 1a and Q 1b alternatively in the two gain modes. The major challenge is to maintain input impedance matching in both modes at 5 GHz.

In the high-gain mode, the impedance looking into the base of Q 1a is

)1

(111e a

a e a m HG L j C j C L g Z ωωππ++= Eq.

1 in which the second element is capacitive at operating

frequencies.

In the low-gain mode, the impedance looking into the left node of C d is

)

(1

111M b d LG C C j C j R Z ++

+

=πωω Eq. 2 in which

m

b m M C R g C )1(21+=is Miller capacitance.

Therefore, if Z LG is designed to equal Z HG at the center frequency of the LNA’s passband, input impedance matching in both modes can be maintained using the same base inductor L b . From Eq. 1 and Eq. 2, the following design equations are obtained.

1

11R C L g a

e

a m =π)

(1

1111M b d e a C C C L C ++

=?ππωωωωNote that even if Q 1a or Q 1b is turned off, its base-emitter junction still exhibits a zero-biased junction

capacitance that is not negligible at 5 GHz. To reduce the

Figure 3: Variable-gain LNA using an inductorless low-

gain branch.

Figure 4: Simplified schematic of the variable-gain LNA

on PCB. Figure 2: Variable-gain LNA using an excess inductor in

its low-gain branch.

Proceedings of ESSCIRC,Grenoble,France,2005

loading effect of the turned-off branch to the functioning branch, small-sized transistors are used for both Q 1a and Q 1b . Due to the loading effect, R 1 should be larger than 50? in order to achieve 50-? impedance matching at the LNA’s input.

In the low-gain mode, R 1 reduces the voltage drop on Q 1b and C m introduces negative feedback, so linearity in the low-gain mode is improved dramatically even though a lower DC current is consumed. However, due to R 1 and C m , NF in the low-gain mode also increases.

3. Implementation and Measurements

The 5-GHz variable-gain LNA was designed and fabricated using 0.35-μm SiGe BiCM OS technology which features NPN transistors with a peak f T of 50 GHz. Figure 4 shows the simplified schematic of the LNA after it is bonded on a PCB. The core LNA is the one shown in Figure 3. The buffer following the core LNA is necessary to ensure stability after wire bonding. It is an inductively-degenerated common-emitter stage with a resistive load. Each stage has 6 ground bondpads to reduce parasitic inductances due to bonding wires. Power and ground pads of the two stages are separated for stability concerns. RF, power and ground pads are

arranged with a pitch of 150 μm for wafer-probing. The die size is 1.05 mm by 1.13 mm (Figure 5).

The base inductor L b (Figure 3) is implemented by the bonding wire L bwIN (Figure 4) which is shared by both modes. For the high-gain branch, the emitter degeneration inductor L e consists of two identical 0.8-nH on-chip spiral inductors in parallel to reduce parasitic effects due to on-chip interconnects. Inductor L o is a 3-nH on-chip spiral inductor. For the low-gain branch, C d and C m are M IM capacitors of 2 pF and 40 fF,

respectively. Resistor R 2 is 300

?. A 70-? resistor is used for R 1, which is to counteract the loading effect of the turned-off high-gain branch.

ESD-protection diodes and ground shields under RF bondpads introduce in total about 300 fF parasitic capacitance between RF input/output pad and the on-chip ground. The capacitance has also been taken into account during input/output impedance matching.

There is a surface-mounted 10-pF ceramic capacitor C B at both the input and output of the LNA on the PCB for DC-decoupling. In addition, a shunt capacitor C 1 is

soldered at the input for impedance matching.

Figure 6: Measured NF in both gain modes.

Figure 7: Measured S-Parameters in the high-gain mode.

Figure 8: Measured S-Parameters in the low-gain mode.

Figure 5: Die photo.

Proceedings of ESSCIRC,Grenoble,France,2005

S-Parameters and NF have been measured in both gain modes without board de-embedding. The results are shown in Figure 6 to Figure 8. At 5 GHz, the LNA shows a 16.3-dB gain in the high-gain mode and a 5.8-dB gain in the low-gain mode. S11 is lower than –10 dB in both modes. S22 is below –14 dB in both modes thanks to the buffer. S12is below –40 dB from 100 M Hz to 10 GHz. At 5 GHz, NFs are 3.5 dB and 8.3 dB in the high- and low-gain modes, respectively. Because of using separated power and ground pads for the two stages, the LNA is unconditionally stable in both modes from 100 MHz up to 10 GHz.

Linearity measurements have also been conducted in both gain modes at 5 GHz. After the LNA is switched from high-gain to low-gain mode, its IIP3 is improved from –7.8 dBm up to +1.1 dBm. The input 1-dB compression point P–1dB also gets better, from –19.3 dBm up to –9.8 dBm. Figure 9 illustrates the two-tone measurement in the low-gain mode at 5 GHz.

Power consumption is also reduced as the gain drops. The core LNA consumes 3 mA in the high-gain mode and 2 mA in the low-gain mode, both from a 3-V supply. Table 1 summarizes the performance of the variable-gain LNA at 5 GHz.

4. Conclusions

This paper describes a 5-GHz variable-gain LNA in 0.35-μm SiGe BiCM OS technology. The LNA exhibits better IIP3 and lower power dissipation in the low-gain mode than in the high-gain mode. The low-gain operation is achieved by an inductorless low-gain branch which occupies much less silicon area. Performance trade-offs are demonstrated between the two gain modes.

5. Acknowledgements

The authors thank P. Wambacq, G. Vandersteen, G. Van der Plas,D. Linten, W. Diel and D. Hauspie for technical discussion.

References:

[1] M. K. Raja, T. T. C. Boon, K. N. Kumar and

W. S. Jau. A fully integrated variable gain 5.75-GHz LNA with on chip active balun for WLAN. In T. Quach, editor, 2003 IEEE RFIC Symposium, pages 439–442, IEEE, June 2003.

[2] H. A. Ainspan, C. S. Webster, J.-O. Plouchart and

M. Soyuer. A 5.5-GHz low noise amplifier in SiGe BiC

OS. In J.

H.

Huijsing et al, editor,

ESSCIRC’1998, pages 80–83, Editions Frontieres,

September 1998.

[3] P. Garcia and D. Belot. Improved high dynamic

range switched gain low-noise amplifier for wide-

band CDM A applications. In F. Dielacher and

H. Grünbacher, editor, ESSCIRC’2001, pages 72–75,

Frontier Group, September 2001.

[4] H. Waite et al. A CDM A2000 zero IF receiver with

low-leakage integrated front-end. In J. Franca and

R. Koch, editor, ESSCIRC’2003, pages 433–436,

IEEE, September 2003.

[5] M. Kamat et al. High performance low current

CDM A receiver front end using 0.18μm SiGe

BiCM OS. In T. Quach, editor, 2003 IEEE RFIC

Symposium, pages 23–26, IEEE, June 2003. Proceedings of ESSCIRC,Grenoble,France,2005