固体电子器件 ee231 part6

Gate Oxides –Physics and Technology

Reading: Chapter 7

EE231 –Vivek Subramanian Slide 6-1 The ITRS Roadmap –A Preview

Note that we are operating at 50% of dielectric breakdown (~10MV/cm), and are working with thicknesses that we definitely expect to allow tunneling

EE231 –Vivek Subramanian Slide 6-2

EE231 –Vivek Subramanian Slide 6-3

Conduction in insulators (specifically, SiO 2)?Three mechanisms:

–Direct tunneling –requires a fairly thin oxide for significant current (<3nm)–Fowler-Nordheim tunneling –electrical “thinning”of oxide allows tunneling –Dielectric breakdown –physical damage forms conductive path through oxide

Cathode Anode b

Ox n

b

Ox E B E

B Ox hm m q K hq

m B He e KE J Ox

Ox

?π?π?8328SiO for 270MV/cm ~B by determined Nordheim

Fowler 32

/32b

//2==≈=???poly Si SiO 2Si

3.2 eV EE231 –Vivek Subramanian Slide 6-4

?Low fields:–No FN tunneling, i.e., no “thinning”of oxide

–Mainly direct tunneling

?Traps can increase current

?Wave function shape will result in some very small current even in thicker oxides

?Thin oxides (<2nm) have substantial direct tunneling due to non-zero wavefunction across barrier

?Intermediate fields:–FN tunneling

?High fields:–Breakdown Tunneling Currents

direct tunneling FN

tunneling T Ox

4V

V Direct FN

J

EE231 –Vivek Subramanian Slide 6-5

Dielectric Reliability

?Why do we care?

–Breakdown –creates conductive path between gate and channel. FET functionality fails –Damage –trapping, etc., causes V T shifts, degrading circuit

performance ?Applications of reliability phenomena:

–SONOS Memories

–Antifuses (FPGAs, Memories, etc.)

?We need to develop models for dielectric reliability to aid quantitative analysis and design.EE231 –Vivek Subramanian Slide 6-6

Breakdown Quantification

?Methods of characterizing breakdown

–Dielectric Strength

?Ramp voltage till dielectric breaks down. Measure multiple

devices to identify intrinsic breakdown vs. defects

?Indicates peak field that can be applied

?10MV/cm for SiO

2, 1MV/cm for Si, ~1-5MV/cm for most

high-K dielectrics ?Typically operate at 30% -50% of breakdown strength –limit on oxide thickness scaling for a given technology node.

log J

V

Oxide defect

Intrinsic breakdown

EE231 –Vivek Subramanian Slide 6-7

Breakdown Quantification

?Methods of characterizing breakdown

–Time-dependent dielectric breakdown (tddb)

?Apply constant voltage (typically >50% of V BD ) or constant current.?Breakdown occurs when voltage across dielectric drops (constant current) or current suddenly increases (constant voltage).

?Indicative of lifetime of oxide under normal operation; better indicator than V BD .

?Can integrate to find charge to breakdown (Q BD ).?Use statistics of several devices to find “intrinsic”tddb

time

voltage slow rise is due to trapping

breakdown EE231 –Vivek Subramanian Slide 6-8

Statistical Analyses

?Breakdown tends to be heavily affected by defects.

–Multiple devices must be measured to confirm accuracy of data –Statistics provide information about dielectric quality and defects

Type of plots:

1)Cumulative distribution (Qbd vs. %)

2)Weibull plot (expands tail to make defects and early

breakdown more visible) f is % failure

EE231 –Vivek Subramanian Slide 6-9

Qualitative models of oxide breakdown

?Hole generation and trapping model –Impact ionization at anode produces holes, that are back-injected towards cathode and trapped in oxide.

?Anode physical damage model

–Recombation of energetic electrons at anode causes physical damage to oxide.

1) Electron is injected to anode

2) Impact ionization forms hot hole 3) Holes are trapped, increasing tunneling current until breakdown Energy release causes

damage, which propagates

back to the anode

EE231 –Vivek Subramanian Slide 6-10

Effects at the anode

We can inject from the gate to the substrate or

vice versa Gate

Substrate

High mechanical stress at gate interface makes

bonds weaker, causing asymmetry in Q BD

?Both models dictate that bond-breaking / impact ionization at the anode is a critical process. We can see this empirically.

EE231 –Vivek Subramanian Slide 6-11

Effect of Field / Energy

?Both models dictate that the energy at the anode is critically important. We can see this empirically.

I n c r e a s i n g e l e c t r o n e n e r g y EE231 –Vivek Subramanian Slide 6-12

The hole generation / trapping model ?Concept:

?Electrons are injected from cathode

?Recombination at anode causes impact ionization

?Hot hole is injected towards cathode

?Hole is trapped in oxide, increasing leakage and causing oxide wearout over time

Ox

Ox

E g

hole E

g hole e I I efficiency e I I /80/80 ??∝=∝

EE231 –Vivek Subramanian Slide 6-13

Effect of hole trapping

?As seen in the previous section, V T shift can be either positive or

negative

?The trap generation has numerous consequences on reliability:

–N it generation

–Oxide damage

–SILC (Stress induced leakage current)

–Breakdown

15V

n +

p no

charge-

trapping EE231 –Vivek Subramanian Slide 6-14

High field electron tunneling Hole generation damage, electron traps breakdown: critical amount of hole fluence, also critical amount of trap density (#/cm 3)defect

Ox

E e J /270?∝Ox

E e /80?∝ηE

E E BD e e e J T /350/80/270 1

∝?∝?∝η

Dependence on electric field

log T BD

1

E Ox

350 MV/cm

Advantage: We can now do accelerated testing by using a higher field and extrapolating

lifetime

EE231 –Vivek Subramanian Slide 6-15

Model Comparison ?Hole generation model predicts an exponential dependence on 1/E

?Physical damage model would be better fit by an exponential dependence on E ?Both models work reasonably well

–1/E works better at high fields

– E works better at low fields kT

E BD

Ox e T /γ?∝E

Log τBD

1/E model

E model

EE231 –Vivek Subramanian Slide 6-16

Questions

?How do you expect reliability to scale as we scale oxide thickness? Think in terms of the effect of:

–Direct vs. FN tunneling

–Interfacial stress

–ITRS Voltage projections

EE231 –Vivek Subramanian Slide 6-17

Modeling defect-induced breakdown

?We would really like a model that explained the “early”breakdown events (the previous models only explain the intrinsic breakdown behavior.?We model this by assuming that all early breakdown is caused by

defects, which result in an effective “thinning”of the oxide.

X Ox

X eff Oxide area = A cm 2,

Defect density = D cm -2

probability that an oxide contains no defect: e -AD

probability of containing 1+ defects is 1-e -AD ~AD

Ox

eff Ox V GT E

G BD e

e T /0/0ττ==EE231 –Vivek Subramanian Slide 6-18

Oxide Leakage: An upcoming brick wall

EE231 –Vivek Subramanian Slide 6-19

Gate Stack Scaling Limits EE231 –Vivek Subramanian Slide 6-20

The Defending Champion

SiO 2Material properties

?non-crystalline insulator

?very high energy gap

?easy to grow on Si

?easy to integrate in a process

?Interface states can be

electrically neutralized (H 2-anneal)

?stable and insensitive

to following process-steps

?excellent scaling capabilities

?no real candidates for replacement (?)

?etc...

The extraordinary properties of SiO

2

are the basis of the success of MOS-technology however there is a limit

EE231 –Vivek Subramanian Slide 6-21State-of-the-art (SiON) Dielectrics ?OI-SiN (Tsujikawa et al., VLSI 2002)

?EOT = 0.9nm, Tphys. = 1.4nm, Jg = 100A/cm 2

?Improved SiN (Matsushita et al., VLSI 2004)

?EOT = 0.73nm, Jg = 88 A/cm 2, gm = 92% SiO 2(96% extra nitridation)

Ideal film structure:

SiN with a few atomic

layers

of SiO 2at SiN/Si interface

EE231 –Vivek Subramanian Slide 6-22

High-K dielectrics

EE231 –Vivek Subramanian Slide 6-23

High-K dielectrics

–an overview

?High-K dielectrics have two

advantages:

–They enable use of thicker films

for the same EOT, resulting in

lower leakage

–They typically have better K/V

BD

ratios than SiO 2, allowing the use

of smaller EOTs for a given V DD .

?Disadvantages:

–Complex process integration –Usually have smaller bandgap,

which results in increased low-field

leakage

EE231 –Vivek Subramanian Slide 6-24

Issues with High-K gate dielectrics

?Process Integration

–An interfacial high-K/SiO

2intermediate compound is usually

formed due to oxygen diffusion to the Si interface. This

dramatically reduces EOT.

–Materials often become crystalline at elevated temperatures, resulting in increased leakage. This constrains thermal budget ?Performance Issues

–Mobility is usually degraded due to high D it

–Reliability / uniformity is still a major question mark.

EE231 –Vivek Subramanian Slide 6-25

The Challengers

Al 2O 38-11.5NdAlO 322.5Al x Si y O z PrAlO 325

(Ba,Sr)TiO 3200-300Si 3N 47

BeAl 2O 48.3-9.43SmAlO 319

CeO 216.6-26SrTiO 3150-250CeHfO 410-20Ta 2O 525-45CoTiO 3/Si 3N 4Ta 2O 5-TiO 2

EuAlO 322.5TiO 286-95HfO 226-30TiO 2/Si 3N 4

Hf silicate 11Y 2O 38-11.6La 2O 320.8Y x Si y O z

LaAlO 323.8-27ZrO 222.2-28LaScO 330Zr-Al-O

La 2SiO 5Zr silicate 11-12.6MgAl 2O 48.3-9.4(Zr,Sn)TiO 440-60

EE231 –Vivek Subramanian Slide 6-26

High-k: Material Requirements

?Barrier height and permittivity

?Thermodynamics and stability

–Maintain capacitance after thermal process

?Dielectric film morphology

–Amorphous versus crystalline ?Interface quality –Dit and EOT contribution, growth ?Gate material compatibility ?Deposition method ? (4)

32

10

C o n

d

u c t

i

o

n -b

a n d

o f f

s e

t

(

e

V

)40

3020100k-value

SiO 2Si 3N 4

Al 2O 3Y 2O 3HfO 2ZrO 2

BaZrO 3

Ta 2O 5

RTCVD poly

ZrO 2

EE231 –Vivek Subramanian Slide 6-27

Hf-based dielectrics

HfO 217-25crystallizes at low temperatures Hf silicate ~11phase separation at high temp.nitrided Hf silicate ~ 9-11increased temp. stability Hf-Al-O 9-25wide range of k-values possible

charge in the layer (due to Al?)

Considered for DRAM

stacked/capped layers combine optimum properties

compatibility with poly-Si

Hf-based materials have received most attention over the last years EE231 –Vivek Subramanian Slide 6-28

PVD Technique “Hf-metal_sputter + RPO ”

HfO 2O*O*O*O*O*O*Hf-metal Hf Hf Hf Hf Hf-metal_sputter

(Controlled Oxidation)Si sub.Starting Surface

Si sub.Si sub.Interface interface

HfO

2Si-sub.

CO time

①T1 ②T2 ③T31.61.01.41.21.8

T 1T 2T 3Treatment Temperature O x

i

d a t i o n R

a t

e (a .

u .

)

Hf Si Hf-metal_sputter:pure Hf-metal (from pure

target) can be deposited onto any starting

surface uniformly and in high density. CO (controlled oxidation):the Hf-metal

should be oxidized uniformly and preferentially

at low temperatures and selective to Si.

EE231 –Vivek Subramanian Slide 6-29

CVD Techniques Metal Organic CVD TDEAH*TDMAS**O 2*Tetrakis(diethylamido)Hafnium **Tetrakis(dimethylamido)Silicon Atomic Layer Deposition

HfCl 4

H

2O

+

n N 2purge

+

o ?based on well-separated saturating gas solid surface reactions ?volatile precursors introduced separately

EE231 –Vivek Subramanian Slide 6-30

High-k Stacks: Leakage Current Reduction

leakage current reduction

of several orders of

magnitude obtained with high-k materials

enhanced high k scalability for metal gates compared to poly gates

10-610-510-410-3

10-210-1110+10.5 1.0 1.5 2.0

EOT(nm)

J g

a t

V

f

b

-1

V (

A /c m

2)S i O 2

t r e n d S i

O N

t r

e n d poly-Si

gate

ALCVD-HfO 2poly-Si gate

metal gate metal gate PVD-HfO 2

EE231 –Vivek Subramanian Slide 6-31

-2.5-2.0-1.5-1.0-0.50.00.510-1210-1010-810-610-4 1.5nm SiON Lot#: HK02089 Wafer#: D03pMOSFET I D I G Vd = -0.02 V 10x1_D1T Lot#: HK02205 Wafer#: D23

C u r

r

e n

t

(A )Gate Voltage (V)-0.50.00.5 1.0 1.5 2.01.5nm SiON 10x1_D1T Vd = +0.02 V

Gate Voltage (V)

nMOSFET

I D I

G High-k Stacks: Issues (with polySi)

?Reduce

hysteresis/V T instability -charge trapping

?Improve g m

,

u eff performance

(esp. nMOS)

?Control V T

and Cinv (esp. pMOS)

Key Focus Areas EE231 –Vivek Subramanian Slide 6-32

Impact on mobility: ~20% lower

0.00.20.40.60.8 1.0 1.2 1.4

050100

150

200250300350400450500

universal

electron mobility implanted poly-Si(A) 1.7 nm SiON + 5 cy HfO 2

+ 10 cy HfO 2R S =70?

μe

f

f (

c

m 2

/

V s

)E eff (MV/cm)poly-Si

SiON N IT

N

FIX HfO

2

Remote charge scattering (and phonons) can be reduced by:

?high-k engineering (decrease Q ); e.g. HfSiON

?interface engineering (increase r ); e.g. engineered SiON ?screening of RCS; e.g. with metal gate (see later)

Gate Electrodes

EE231 –Vivek Subramanian Slide 6-33 Gate Electrode Materials

EE231 –Vivek Subramanian Slide 6-34

EE231 –Vivek Subramanian Slide 6-35

Metal Gates: Work function Requirements

4.1eV (n+poly)4.65eV (mid-gap)

5.2eV (p+poly)Single Metal/FUSI Dual

Metal/FUSI

Single

Metal/FUSI + tuning NMOS PMOS NMOS

PMOS

PMOS

NMOS mid-gap mid-gap + 0.2eV Band-edge

Planar SOI Multiple gate High

performance

Low standby power EE231 –Vivek Subramanian Slide 6-36

Metal gates: Other Requirements

?Compatibility

–Low resistivity

–Appropriate workfunction

?Or tunable workfunction

–Good interface with gate dielectric

?Manufacturability

–Easy to deposit –CVD process available

–Easy to etch and clean-up

?Integration

–Stable with thermal budget

–Amorphous –crystalline (nano crystals)

?No phase change in Tbudget

–Process scheme

EE231 –Vivek Subramanian Slide 6-37

Metal Gate Integration –Dual WF

?Deposit and etch of the N and P type metal separately.

–The first metal etch has to be very selective and non-damaging towards the dielectric.

–Or the dielectric has to be re-grown [SiON] or re-deposited [high-k] selectively.

?Sequential deposition of N and P type metal –modification of one of the two gate electrodes.

–The right materials and modification

process has to be found given both

an N and P type electrode.

–Alloying

?Deposition of single metal or FUSI and modification to meet N and PMOS by implantation, chemical reaction EE231 –Vivek Subramanian Slide 6-38

Workfunction Engineering

NiSi RTP silicidation Poly-Si

(or a-Si)

Implant e.g. As, P, B, etc.Activation Anneal

(May be skipped)Ni

Ni deposition

Dopant concentration Low solubility of dopants in NiSi Dopant segregation to surface Dopants snowplowed,segregation to oxide interface 10101010As 8E15C

o

u n

t s (A .

U .

)

C o

n

c e n t

r a t i o

n

(

a t /

c m

3)

23

2221 20

1019

Depth (nm)

0 25 50 75 100 125 150

As 2E15

Ni

Si J.Kittl, internal data

EE231 –Vivek Subramanian Slide 6-39Workfunction Engineering

4.1

4.2

4.34.44.54.6

4.7

4.84.95

5.15.2

W o r k f u n c t i o n (e V )NiSi (group III)NiSi

(undoped)

NiSi (group V)

NiPt PtSi PtSi (on High-k)A,Lauwers, internal data ?WF tuning possible on SiOx dielectrics

?No significant separation with dopants for FUSI/high-k ?Could be Fermi Level Pinning

EE231 –Vivek Subramanian Slide 6-40

Conventional materials considered ?Pure metals

–Selected pure metals are promising especially for pMOS. ?Pt, Ir, Ru (PMOS like –expensive –difficult to etch)?Ti (4.56eV) and Mo (4.72eV) on Si 3N 4(Q.Lu, VLSI 2000)?Ta/AlN (4.9eV) and Hf/AlN (4.4eV) (C.Park, VLSI 2003)?Pure metal –φM adjusting

–Modification by implantation or silicidation (see before)?(110) Mo / N implantation (4.53 –4.94eV) (Q.Lu, VLSI 2001)?Metal nitrides

–Makes the metals more stable (silicon incorporation gives additional stability)?TiN (4.8eV),TaSiN (4.19 –4.27eV) on HfO 2(S.Samavedam, VLSI 2002)?HfN (4.65eV) (H.Yu, VLSI 2003)

?Alloying / Interdiffusion

–Linked to the possible implementation scheme for CMOS ?Ni and Ti (I.Polischuk, IEEE EDL, April 2002)?RuTa (4.2 –5.2eV) (V.Misra, IEDM 2002)