encounter流程使用说明

The Basic Digital IC backend Flow Using Encounter

9.1

The backend flow with Encounter can be briefly expressed as follow:

(1) Design Importing

(2) Global Net Connect: just define the VSS and VDD, but not implement the connective.

(3) Floorplan: initialize floorplan + auto floorplan + Add Halo

(4) Power Planning: Add Ring + Add Strapes (core ring, block ring)

(5) Special Route: without std cell

(6) Placement: mode setup + place standard cell

(7) Pre-CTS Timing Analysis and Optimization: cmd timeDesign -preCTS, optDesign -preCTS

(8) CTS

(9) Post-CTS Timing Analysis and Optimization: timeDesign -postCTS, timeDesign -postCTS -hold, optDesign -postCTS, optDesign -postCTS -hold

(10) Special Route: just select standard cell

(11) Trial Route

(12) Nano Route

(13) Post-Route Timing Analysis and Optimization

(14) Add Filling (core filling, IO filling)

(15) Verify Connectivity, Verify Geometry

(16) Output SDF: extract RC + calculate delay

(17) Export NETLIST, GDSII.

In this tutorial, TSMC 35 technology is used.

Data Preparation:

1. Netlist: The verilog file comes from Design Compiler.

2. SDC: The sdc file comes from Design Compiler, but revises it as follows:

replace the follow coding

set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA

set_operating_conditions -max WCCOM -max_library

tpz773pntc -min BCCOM -min_library tpz773pntc

set_wire_load_mode enclosed

set_wire_load_model -name TSMC16K_Conservative -library tcb773ptc

set_driving_cell -min -lib_cell PDI -pin C [get_ports N_RST]

as

set_operating_conditions -analysis_type bc_wc -max WCCOM -min BCCOM

set_driving_cell -min -lib_cell PDI -pin C [get_ports N_RST] set_driving_cell -min -lib_cell PDI -pin C [get_ports CLK]

and add the

set_propagated_clock [get_clock clk]

behind create_clock

3. IO file: The .io file that defines the location and order of Pads or Pins.

4. LEF file: Include the core and IO LEF, and their antenna LEF respectively.

5. LIB file: Include the worst, best, typical case of both core

(standard cells) and IO.

6. StreamOut map: The map file that is used to map to the target technology when stream out GDSII file.

I. Design Importing

File--> Import Design...

(1) Load Netlist, LEF, LIB, SDC, IO files, and write the cell name "By user". As fig.1 shows.

When load the LEF files, we must select the files as the order: core.lef -- IO.lef -- core antenna.lef -- IO antenna.lef. Or there will be something wrong latter. As Fig. 2 shows.

(2) Define power and GROUND nets as Fig. 3 shows.

(3) Save configuration. Click the "save..." button and name it "Setup.conf".

(4) Click "OK".

II. Global Net Connect

Power--> Connect Global Nets...

Define the "Pin Name" and "To Global Net" "VDD" and "VSS" respectively, and Add to List. This operation define the connection between Stdcell, Macro, IO power and gound Pins and Global power and ground. That means, in the following flow, all the Stdcell Macro, IO power/ground Pins should should connect to Global power/ground Nets.

T hen, we should also define the logical "1" and "0" to connect to Global power and ground.

Select "Tie High" and fill the "To Global Net" "VDD". Then add to list.

The same to select "Tie Low" and define the logical "0".

This global definition should be completed before Floorplan. Note that, This step just defines the connection-ship but not connects any pins actually.

III. Floorplan

(1) Floorplan --> Specify Floorplan.

We can define the size and Core Utilization. And we must define the space between core and IO to place Power supply Rings. Here I

define it 30 um.

(2) Auto-Floorplan

Floorplan --> Automatic Floorplan --> Plan Design

Select "Keep Guide", and "OK".

(3) Add Halo

If there are some macros, the Halos are needed to prevent unexpected nets routes through macros.

Floorplan --> Edit Floorplan --> Edit Halo...

Set the enough space for Halo.

IV. Power Planning

(1) Add power rings.

Power --> Power Planning --> Add Ring

Set the appropriate "layer", "width", "spacing" and "offset" to create the power and ground rings.

If some blocks need seperated power rings, the "Block rings around" can be selected.

After adding power rings, the layout could be :

(2) Adding stripes

If the design is rather large, and some stripes are needed to make sure the power supply is stable.

Power --> Power Planning --> Add Stripes

Set the "Layer", "Direction", "Width", "Spacing", "Set-to-set

distance", "Relative from core or selected area".

Then, the layout becomes as，

V. Special Route

The object of this step is to connect the power pins of Macros, IOs, Rings and stripes to power nets acturally which has been defined in "Global Net connect" step.

Route --> Special Route

As there is no std cell placed, the "Standard Cell Pins" is

unselected.

Click "OK".

VI. Placement

(1) Mode Setup

Options --> Set Mode --> Mode Setup Select as follows:

(2) Place Standard Cells

Place --> Place Standard Cell

Select as follow:

Click "OK".

Select the last view (physical view) at the upper right corner, and the placed standard cells can be seen as follow:

VII. Pre-CTS Timing Analysis and Optimization

(1) Analysis

After Placement, we should analysis the timing constrains.

Run the follow command in the terminal:

timeDesign -preCTS

The steps: Trial route, native defalt RC extraction, and timing

analysis for generating timing reports, are doing step by step. There

are some nets appear.

And to see the terminal, there are 2 max_cap violations and 75 max_tran violations. Therefore, some optimization must be done to fix these violations.

(2) Optimization

running the follow command in treminal optDesign -preCTS

Those violations are fixed.