LED displays

LED displays

Generate light with your FPGA!

The project

This project has 6 parts:

?Part 0: LED glow

?Part 1: How LEDs work

?Part 2: Varying an LED intensity

?Part 3: 7-segments LED displays

?Part 4: LED multiplexing

?Part 5: LED dot-matrix displays

Links

? A nice LED display technology review from Maxim.

?Charlieplexing - Reduced Pin-Count LED Display Multiplexing. LED glow

Do you have an FPGA board with an LED?

Try this simple design.

module LEDglow(clk, LED);

input clk;

output LED;

reg [23:0] cnt;

always @(posedge clk) cnt<=cnt+1;

wire [3:0] PWM_input = cnt[23] ? cnt[22:19] : ~cnt[22:19];

reg [4:0] PWM;

always @(posedge clk) PWM <= PWM[3:0]+PWM_input;

assign LED = PWM[4];

endmodule

This makes the LED "glow".

Note: Use a "clk" clock signal at around 20MHz. Otherwise the effect might be too slow or too fast to be appreciated.

How LEDs work

Controlling an LED with an FPGA

The ideal LED control is a current source.

FPGA pins are voltage controlled, so a simple solution is to add a resistor in series with the LED. Values from 100? to 1K? are common.

LED electronic basics

An LED (Light Emitting Diode) is a semiconductor device that produces light when current is going through it.

The LED symbol looks like a diode, with an anode (+) and cathode (-).

?An LED acts like a diode - conducts electricity one way, blocks it the other way.

?Like all diodes, it has a threshold voltage. The threshold voltage of a common red LED is around 2.0V.

o Below 2.0V, no light is emitted (no current goes through the LED).

o Above 2.0V, the LED conducts electricity, and the light intensity depends of the current that goes through the LED.

?An LED has 2 physical limits not to exceed:

o A maximum forward current (and so a maximum light intensity). The maximum is typically a few 10's of mA.

o A maximum reverse voltage (even though no current goes through when the LED is reversed biased, do not reverse bias it too much). The reverse voltage

limit is typically 5V... much lower than common diodes!

Varying an LED intensity

Turning an LED on and off

Here's how to make an LED blink (on and off).

module LEDblink(clk, LED);

input clk; // clock typically from 10MHz to 50MHz

output LED;

// create a binary counter

reg [32:0] cnt;

always @(posedge clk) cnt<=cnt+1;

assign LED = cnt[22]; // blink the LED at a few Hz (change the bit index to change the blinking rate)

endmodule

Making an LED half-lit

One solution would be doubling the value of the resistor used in series with the LED.

Another solution is to drive the LED FPGA output half of the time. If that's done fast enough, your eye will see the LED half-lit. Anything faster than 100Hz is too fast for the human eye to detect - it averages the light intensity it receives.

module LEDhalflit(clk, LED);

input clk; // clk should be at least 200Hz.

// Anything above is fine (most FPGA boards have adequate clocks, running at a few 10's of MHz)

output LED;

reg toggle;

always@(posedge clk) toggle<=~toggle; // toggles at half the clk frequency (at least 100Hz)

assign LED = toggle;

endmodule

Fine-tuning the LED intensity

For more LED intensity control, a PWM is an ideal solution.

Here's an example that uses a 4-bits control to select between 16 intensity levels out of an LED.

module LED_PWM(clk, PWM_input, LED);

input clk;

input [3:0] PWM_input; // 16 intensity levels

output LED;

reg [4:0] PWM;

always @(posedge clk) PWM <= PWM[3:0]+PWM_input;

assign LED = PWM[4];

endmodule

By continuously changing the LED intensity, the LED appears to "glow".

module LEDglow(clk, LED);

input clk;

output LED;

reg [23:0] cnt;

always @(posedge clk) cnt<=cnt+1;

wire [3:0] PWM_input = cnt[23] ? cnt[22:19] : ~cnt[22:19]; // ramp the PWM input up and down

reg [4:0] PWM;

always @(posedge clk) PWM <= PWM[3:0]+PWM_input;

assign LED = PWM[4];

endmodule

This is the same example that was presented in part 0.

7-segments LED displays

Now that we know how to drive an individual LED, let's try a 7-segment display.

The 7-segments display

The 7-segments display consists of 8 LEDs (let's not forget the dot) aggregated as shown below.

Each segment is created using a separate LED, typically named "A" to "G", plus DP for the dot. So a 7-segments display consists of 8 LEDs.

Now, the LEDs are not wired separately. To save a few pins in the 7-segments display, either the anodes or the cathodes are tied together, so that only 9 pins are required out of the display. Here's a typical "common-cathode" display:

Such a display requires at least 9 pins. It is often made in 10 pins packages (and the common signal is available on 2 pins).

Now, to drive such a display from an FPGA, the straighforward solution is to use 8 IOs.

Using such arrangement, here's how to display the digit '2'.

module LED_7seg(segA, segB, segC, segD, segE, segF, segG, segDP);

output segA, segB, segC, segD, segE, segF, segG, segDP;

assign {segA, segB, segC, segD, segE, segF, segG, segDP} = 8'b11011010; // light the leds to display '2'

endmodule

Now that wasn't too hard.

Decimal counter

Let's try a decimal counter.

module LED_7seg(clk, segA, segB, segC, segD, segE, segF, segG, segDP); input clk;

output segA, segB, segC, segD, segE, segF, segG, segDP;

// cnt is used as a prescaler

reg [23:0] cnt;

always @(posedge clk) cnt<=cnt+24'h1;

wire cntovf = &cnt;

// BCD is a counter that counts from 0 to 9

reg [3:0] BCD;

always @(posedge clk) if(cntovf) BCD <= (BCD==4'h9 ? 4'h0 : BCD+4'h1);

reg [7:0] SevenSeg;

always @(*)

case(BCD)

4'h0: SevenSeg = 8'b11111100;

4'h1: SevenSeg = 8'b01100000;

4'h2: SevenSeg = 8'b11011010;

4'h3: SevenSeg = 8'b11110010;

4'h4: SevenSeg = 8'b01100110;

4'h5: SevenSeg = 8'b10110110;

4'h6: SevenSeg = 8'b10111110;

4'h7: SevenSeg = 8'b11100000;

4'h8: SevenSeg = 8'b11111110;

4'h9: SevenSeg = 8'b11110110;

default: SevenSeg = 8'b00000000;

endcase

assign {segA, segB, segC, segD, segE, segF, segG, segDP} = SevenSeg; endmodule

Smooth counter

Finally let's try a "smooth" counter (fades each digit into then next).

module LED_7seg(clk, segA, segB, segC, segD, segE, segF, segG, segDP); input clk;

output segA, segB, segC, segD, segE, segF, segG, segDP;

reg [23:0] cnt;

always @(posedge clk) cnt<=cnt+24'h1;

wire cntovf = &cnt;

reg [3:0] BCD_new, BCD_old;

always @(posedge clk) if(cntovf) BCD_new <= (BCD_new==4'h9 ? 4'h0 : BCD_new+4'h1);

always @(posedge clk) if(cntovf) BCD_old <= BCD_new;

reg [4:0] PWM;

wire [3:0] PWM_input = cnt[22:19];

always @(posedge clk) PWM <= PWM[3:0]+PWM_input;

wire [3:0] BCD = (cnt[23] | PWM[4]) ? BCD_new : BCD_old;

reg [7:0] SevenSeg;

always @(*)

case(BCD)

4'h0: SevenSeg = 8'b11111100;

4'h1: SevenSeg = 8'b01100000;

4'h2: SevenSeg = 8'b11011010;

4'h3: SevenSeg = 8'b11110010;

4'h4: SevenSeg = 8'b01100110;

4'h5: SevenSeg = 8'b10110110;

4'h6: SevenSeg = 8'b10111110;

4'h7: SevenSeg = 8'b11100000;

4'h8: SevenSeg = 8'b11111110;

4'h9: SevenSeg = 8'b11110110;

default: SevenSeg = 8'b00000000;

endcase

assign {segA, segB, segC, segD, segE, segF, segG, segDP} = SevenSeg; endmodule

Nice, isn't it?

Sorry you have to build it if you want to see it.

LED multiplexing

Now that we know how to drive 7-segments displays, let's aggregate them to make big counters.

The pin count issue

Let's try to build a big display that uses eight 7-segments displays, so that it can show numbers from 0 to 99999999.

If we build it the straightforward way, we are using 64 FPGA pins.

That's not practical.

There must be a better way!

LED multiplexing

Now we are using only 16 FPGA pins.

The trade-off is that only one display out of eight can be lit at any particular time. But if the FPGA switches "fast enough", it seems that all the displays are lit.

"Fast enough" means 100Hz or more.

At 100Hz, a display cycle would last 10ms (and each display would be lit 1.25ms per cycle).

Notes:

?One the drawing, the 8 lower lines control which 7-segment display is enabled, and the 8 upper lines control what is displayed on the enabled 7-segment.

?The current in the 8 lower lines is enabled only 1/8th of the time, but the peak current can be 8 times higher than in the upper lines, so the lower FPGA lines cannot be

connected directly like that, but should go through power transistors (not shown on the drawing).

An 8-digits BCD counter example

Here's a counter design that drives a multiplexed 8-digits 7-segments display.

The counter goes from 00000000 to 99999999, then rolls-over.

The design uses 3 modules:

1.BCD1: BCD counter (single digit)

2.BCD8: BCD counter (holds 8 digits)

3.LED_BCD8x7seg: top-level that drives the display by multiplexing 8 digits

Get the file here.