段成华数字集成电路第六次作业

数字集成系统第六次作业

1.For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA.

(1)Synthesize and verify (simulate) the VHDL design of the FIFOs;

(2)For CPLD implementation (fit) of the FIFOs, how many MCs

(macrocells) and PTs (product terms) are needed? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.

(3)For FPGA implementation (place and route) of the FIFOs, how

many LBs (logic blocks)? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.

(4)Try to synthesize again the design with timing constraints and

compare with its former counterparts. You will create the timing constraint file by yourself and add it to your project. Please refer to the following graphic interface of ISE:

2. For the VHDL model given below (Code List Two), there may be some design errors in it. Some warning(s) and/or error(s) information may be issued when synthesizing it. Try to find out such design errors and correct them.

1.根据段老师题目中提供的程序代码，并对此书写testbench,

（1）综合后的RTL schematic和功能仿真后的结果分别如下图1和图2所示。

图 1 RTL schematic

图2仿真结果(功能仿真)

（2）设置芯片为XC9500 CPLDS系XC95108-7-PQ160，速度为-7，综合后报告分析如下

图 3 CPLD综合报告

由图3可以知道，对于本程序，一共使用了87个Macrocells，占总数的百分之八十一，使用了228个Pterms，占总数的百分之四十三，资源相对充裕，满足程序的设计要求。

图 4 CPLD时间报告

由图4可知，时钟的最小周期为15ns，受clock to setup delay影响最大，故关键路径为tcyc。延时为15ns，时钟的工作频率为66.67MHz。

(3) 更换芯片型号为Spartan3- xc3s200-5pq208,速度为-5，其综合报告如下

图 5 FPGA综合报告

查Spartan3的datasheet如下

图 6 Spartan3 datasheet

由上图知，对于选择的器件，其logic cell为4320,CLB 有24X20=480个，每个CLB包含4个slice,而对于我们的程序，一共使用了66个slice，占总数的百分之三（总slice共计1920个），故使用的CLB数为66/4=16.5,即使用了17个CLB

图7 时间报告

关键路径为clock to setup delay，延时为4.821ns，它对时钟的工作频率影响最大。时钟的工作频率为207.42MHz。

（4）

图8 timing constrain

图9 没有设置时序约束时的报告

图10 设置clk周期约束为5ns时的报告

图11 设置clk周期约束为4.5ns时的报告

图12 设置clk周期约束为4ns时的报告

图13 设置clk周期约束为3.5ns时的报告

由图10至13可以看到，当对CLK进行约束时，会对系统性能有所影响，随着条件的苛刻，best case achievable也越来越小，但当限制小到一定程度时，EDA工具可能会无法布

通，如3.5ns时timing error为31，score为9677.

2.

图14 对fifoxy进行综合后如下

主要有以上两个warning和一个错误：

(1) 程序中，输入端口rd没有使用到，其作用被oe所取代，因此可以将rd信号去掉，用oe来表示其功能，且不影响整个系统的设计。

(2) 程序中输入信号端口en也未被使用，因为直接在fifo(wrptr)中取得了写地址的值，因此信号en也应去掉。

(3) 语句dmuxout<=fifo(wrptr); 应改为dmuxout<=fifo(rdptr); 因为这时是读寄存器里的值，应该由读地址指针rdptr来指定应该读取哪个寄存器的值。

图15 修改后的波形图

备注，当时为了尽快看到波形，故使用了altera公司的quartus来对波形进行快速设置。上图为quartus的仿真波形图。

附录：fifo89—testbench

-----------------------------------------------------------------

---------------

-- Company:

-- Engineer:

--

-- Create Date: 20:04:55 12/06/2014

-- Design Name:

-- Module Name: D:/xilinx_workspace/test4/fifo89/fifo89_tb.vhd -- Project Name: fifo89

-- Target Device:

-- Tool versions:

-- Description:

--

-- VHDL Test Bench Created by ISE for module: fifo89

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes:

-- This testbench has been automatically generated using type s std_logic and

-- std_logic_vector for the ports of the unit under test. Xilinx recommends

-- that these types always be used for the top-level I/O o f a design in order

-- to guarantee that the testbench will bind correctly to t he post-implementation

-- simulation model.

--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY fifo89_tb IS

END fifo89_tb;

ARCHITECTURE behavior OF fifo89_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fifo89

PORT(

clk : IN std_logic;

rst : IN std_logic;

rd : IN std_logic;

wr : IN std_logic;

rdinc : IN std_logic;

wrinc : IN std_logic;

rdptrclr : IN std_logic;

wrptrclr : IN std_logic;

data_in : IN std_logic_vector(8 downto 0);

data_out : OUT std_logic_vector(8 downto 0) );

END COMPONENT;

--Inputs

signal clk : std_logic := '0';

signal rst : std_logic := '0';

signal rd : std_logic := '0';

signal wr : std_logic := '0';

signal rdinc : std_logic := '0';

signal wrinc : std_logic := '0';

signal rdptrclr : std_logic := '0';

signal wrptrclr : std_logic := '0';

signal data_in : std_logic_vector(8 downto 0) := (others => '0');

--Outputs

signal data_out : std_logic_vector(8 downto 0);

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fifo89 PORT MAP (

clk => clk,

rst => rst,

rd => rd,

wr => wr,

rdinc => rdinc,

wrinc => wrinc,

rdptrclr => rdptrclr,

wrptrclr => wrptrclr,

data_in => data_in,

data_out => data_out

);

-- Clock process definitions

clk_process :process

begin

clock_loop:loop

clk <= transport'0';

wait for 10ns;

clk <= transport'1';

wait for 100ns;

clk <= transport'0';

wait for 90ns;

end loop clock_loop;

end process;

-- Stimulus process

stim_proc: process

begin

wait for 200 ns; --200ns rst<=transport'1';

wait for 200 ns; --400ns rst<=transport'0';

rdptrclr<=transport'1';

wrptrclr<=transport'1';

wait for 200 ns; --600ns

wrinc<=transport'1';

rdptrclr<=transport'0';

wrptrclr<=transport'0';

wait for 200 ns; --800ns

rd<=transport'1';

wr<=transport'1';

wait for 400 ns; --1000ns

rd<=transport'0';

wait for 1800 ns; --2800ns

rd<=transport'1';

wr<=transport'0';

rdinc<=transport'1';

wrinc<=transport'0';

wait for 800 ns; --3600ns rd<=transport'0';

wait for 200 ns; --3600ns

rd<=transport'1';

wait;

end process;

-- Clock process definitions

data_process :process

begin

wait for 50ns;

data_in<="000000001"; d_loop:loop

wait for 200ns; data_in<=data_in+'1'; end loop d_loop;

end process; END;