并行输出控制器设计 POC Design

The Report of POC Design

Name Zhou Bin

School Number 04005606

April, 1, 2008

Purpose

1. The purpose of this project is to design and simulate a parallel output

controller (POC) which acts an interface between system bus and printer.

2. The use of MaxPlus II for design and simulation.

Task

The physical model of POC

POC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral (such as a printer or other output devices).

Figure 1 Printer Connection

Figure 1 shows the connecting of a printer to the system bus through the POC. The communication between POC and the printer is controlled by a “handshake” protocol illustrated in Figure 2.

Figure 2 The handshake-timing diagram between POC and the printer

The logical model of POC

The handshaking process is described as follows: When the printer is ready to receive a character, it holds RDY=1.The POC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR(transfer request).

The printer will change RDY to 0, take the character at PD and hold the RDY at 0 until the character has been printed (e.g. 5 or 10ms), then set RDY=1 again when it is ready to receive the next character. (Suppose the printer has only a one character “buffer” register, so that each character must be printed before the next character is sent).

In order to ease your design work, the further explanations of the POC operations and some design hints are given as follows: The buffer register BR is used to hold a character that has been sent via the system bus while that the character is being transferred to the printer. The status register SR is used for two control functions:SR7serves as a ready flag for system bus transfers to BR (like the printer RDY signal for transfers from POC to the printer), and SR0 is used to enable or disable interrupt requests from POC.If SR0=1, then POC will interrupt when it is ready to receive a character (i.e., when SR7=1). If SR0=0, then POC will not interrupt. The other bits of SR are not used and empty.

The transfer of a character to POC via the system bus proceeds as follows.

POC indicates that it is ready by setting SR7.The processor reads SR (by executing

a polling or interrupt service routine) and, finding SR7=1, writes a character to

BR.The POC clears SR7when it loads this character into BR to indicate that another character should not be sent for the moment. POC then proceeds to transfer the character in BR to the printer by generating a pulse at TR. The processor, in the meantime, continues to fetch and execute instructions .If it should happen to read SR, it will find SR7=0 and hence will not attempt to send another character to the printer. When the printer is ready to receive another character, POC sets SR7.The transfer cycle can now repeat.

The overall connection of printer and POC

The overall connection graph as follows:

In this graph there are two main modules: print and final_poc; Print in this project is used as a time-delayer. Final_POC contains the main program of this project.

Simulation and Explain

We use two modes to show the simulation waves.

1.POC without printer

Simulation waves

Rw is an input signal that is the control of writing data from CPU to POC.

Rdy is an input signal that is a printer ready message to POC.

Cs is an enable signal.

Tr is a pulse signal to make the rdy be low-level. Clk is a clock signal.

Irq is a interrupt signal from POC to CUP. Data is a 8 bits input signal.

Pd is also a 8 bits signal from POC to Printer.

Explain:

We can see that when Cs is high and rdy is high, the printer is free.POC gives an interrupt signal to CPU and the data transfers to POC when rw is high. Then the data will be transferred to printer as long as the printer is free. Of course, in the duration of this process the POC will send a tr pulse to down the rdy signal

which shows the printer is busy. The process will be circled.

https://www.360docs.net/doc/3e15192881.html,bined POC

Simulation waves

Explain:

The mean of signals is the same as the above. we can only pay attention to four signals: RW ,RESET ,DATA ,PD.

When RESET is high and RW is also high, it shows we have some data to be printed. Then if the printer is free, the POC will generate an interrupt (IRQ=1).After CPU deal with the interrupt, the data will be transferred to printer.

The printer will cost some time to deal with the data. Then the process can be circled.

Conclusions and discussions

We can see in our project the POC can work rightly and it is accorded with the fact. But in this model one printer can only be used by one user. If many people want to use the printer, the efficiency of the POC and CPU will be dropped fleetly. Because many users will generate interrupt. The CPU will be interrupted frequently and the POC will also work gap by gap. So we should solve this matter. We have some techniques to solve it. But the most popular of them is a technique called SPOOLing (Simultaneous Peripheral Operation On-Line). The core mind of it is sharing. The printer is independent in physics, but sharing in logic. It uses a sharing main memory to buffer data, the data will not be sent to POC (or printer) unless the memory is full. The speed of accessing to main memory is much higher than to POC (or printer), so the total speed will grow much. Of course, the achievement of this technique in the fact is much more complex.

Appendix

The full program as follows:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity final is

port(

rw:in std_logic;

data:in std_logic_vector(7 downto 0);

cs:in std_logic;

irq:out std_logic;

clk:in std_logic;

rdy:in std_logic;

tr:out std_logic;

pd:out std_logic_vector(7 downto 0)

);

end final;

architecture arc_poc of final is

signal sr:std_logic_vector(7 downto 0):="00000000"; signal br:std_logic_vector(7 downto 0):="00000000"; begin

p1:process(clk)

begin

if cs='0' then irq<='1';

elsif (clk'event and clk='1') then

if sr(0)='1' and sr(7)='1'then irq<='0';

else irq<='1';

end if;

end if;

end process p1;

p2:process(clk)

variable count:integer range 0 to 2;

begin

if (clk'event and clk='1') then

if rw='1' then br<=data; sr<="00000001";

elsif rdy='1' then pd<=br;sr<="10000001";tr<='1';

end if;

if count=2 then tr<='0';count:=0;

else count:=count+1;

end if;

end if;

end process p2;

end arc_poc;