数字系统课程设计报告-
数字系统课程设计
（数字电子钟）
班级：电信 081
姓名：徐镇江
学号：0840*******
一、系统设计要求：
本设计要求掌握数码管的显示原理、数字钟的VHDL编程方法。具体要求：（1）采用EDA实验箱上的共阴极数码管显示时间，从00:00：00~23:59:59，依此循环。
（2）整点报时。
二、系统设计思路：
根据系统的设计要求可知，本系统设计本设计可分为三个主要部分电路。
（1）计时：
主要是通过标准秒脉冲的输入，采集秒脉冲的上升沿，从而触发秒计时信号，从而达到秒计时的目的。当到达“59”时，产生分进位脉冲信号，激发计分电路，同理，从而实现计分。整体就实现了计时的功能。
（2）显示：
通过对计秒、计分、计时电路的BCD码输出，进行译码操作，输出给8段数码显示，并进行动态扫描，即可实现多位数码管的显示。
（3）整点报时
整点报时电路在该设计当中只是给出了一个整点的信号，该信号是低电平有效，持续时间是1分钟。通过外部的设计电路，该信号对“蜂鸣器”电路起一个控制的作用。
1.计时电路的设计
主要VHDL程序段如下：
process(clk_time)
begin
if (clk_time'event and clk_time = '1') then
if(sec_1 = "1001") then
sec_1<="0000";
if(sec_2 = "0101") then
sec_2 <= "0000";
co1 <= '1';
else
sec_2 <= sec_2 +'1';
co1<='0';
end if;
else sec_1<= sec_1 + '1';
end if;
end if;
sec <= sec_2 & sec_1;
end process;
上面的代码是计秒部分，它为计分电路提供一个分脉冲进位信号，“co1”当co1 = '1'时，触发计分电路
process(co1)
begin
if co1'event and co1 = '1' then
if(min_1 = "1001") then
min_1<="0000";
if(min_2 = "0101") then
min_2 <= "0000";
co2 <= '1';
else
min_2 <= min_2 +'1';
co2<='0';
end if;
else
min_1 <= min_1 +1;
end if;
end if;
min <= min_2 & min_1;
alter<='1';
end process;
同理，底下的代码是计时部分。
process(co2)
begin
if co2'event and co2 = '1' then
if (hour_1 = "0011" and hour_2 = "0010") then
hour_1 <="0000";
hour_2 <="0000";
elsif hour_1 = "1001" then
hour_2 <= hour_2 + '1';
hour_1 <= "0000";
else
hour_1 <= hour_1 + '1';
end if;
end if;
hour <= hour_2 & hour_1;
alter<='0';
end process;
2.显示控制电路的设计
本设计显示需要使用的是6个7段数码管，在计时结果显示电路中，6个7段数码管显示部分采用的是动态显示，由时钟信号clk_scan作为扫描信号，每来一次上升沿转换一个数码管显示，并显示对应的信息.
显示控制模块的主要VHDL程序段如下：
process(clk_scan)
begin
if clk_scan'event and clk_scan = '1' then
if cnt = "101" then
cnt <= "000";
else
cnt <= cnt +'1';
end if;
end if;
end process;
process(cnt)
begin
case cnt is
when "000" => bcd <=sec(3 downto 0);com <="111110";
when "001" => bcd <=sec(7 downto 4);com <="111101";
when "010" => bcd <=min(3 downto 0);com <="111011";
when "011" => bcd <=min(7 downto 4);com <="110111";
when "100" => bcd <=hour(3 downto 0);com <="101111";
when "101" => bcd <=hour(7 downto 4);com <="011111";
when others => bcd <= "0000";com <= "111111";
end case;
case bcd is
when "0000" => seg7 <= "00111111";
when "0001" => seg7 <= "00000110";
when "0010" => seg7 <= "00011011";
when "0011" => seg7 <= "01001111";
when "0100" => seg7 <= "01100110";
when "0101" => seg7 <= "01101101";
when "0110" => seg7 <= "01111101";
when "0111" => seg7 <= "00000111";
when "1000" => seg7 <= "01111111";
when "1001" => seg7 <= "01101111";
when others => seg7 <= "00000000";
end case;
end process;
系统的VHDL源程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity digclk is
port(
clk_scan: in std_logic;
clk_time: in std_logic;
com: out std_logic_vector(5 downto 0);
seg: out std_logic_vector(7 downto 0)
);
end entity digclk;
architecture art of digclk is
signal co1,co2:std_logic;
signal hour_1,hour_2:std_logic_vector(3 downto 0);
signal min_1,min_2:std_logic_vector(3 downto 0);
signal sec_1,sec_2:std_logic_vector(3 downto 0);
signal sec,min,hour,seg7:std_logic_vector(7 downto 0);
signal cnt:std_logic_vector(2 downto 0);
signal bcd:std_logic_vector(3 downto 0);
begin
process(clk_time)
begin
if (clk_time'event and clk_time = '1') then
if(sec_1 = "1001") then
sec_1<="0000";
if(sec_2 = "0101") then
sec_2 <= "0000";
co1 <= '1';
else
sec_2 <= sec_2 +'1';
co1<='0';
end if;
else sec_1<= sec_1 + '1';
end if;
end if;
sec <= sec_2 & sec_1;
end process;
process(co1)
begin
if co1'event and co1 = '1' then
if(min_1 = "1001") then
min_1<="0000";
if(min_2 = "0101") then
min_2 <= "0000";
co2 <= '1';
else
min_2 <= min_2 +'1';
co2<='0';
end if;
else
min_1 <= min_1 +1;
end if;
end if;
min <= min_2 & min_1;
end process;
process(co2)
begin
if co2'event and co2 = '1' then
if (hour_1 = "0011" and hour_2 = "0010") then hour_1 <="0000";
hour_2 <="0000";
elsif hour_1 = "1001" then
hour_2 <= hour_2 + '1';
hour_1 <= "0000";
else
hour_1 <= hour_1 + '1';
end if;
end if;
hour <= hour_2 & hour_1;
end process;
process(clk_scan)
begin
if clk_scan'event and clk_scan = '1' then
if cnt = "101" then
cnt <= "000";
else
cnt <= cnt +'1';
end if;
end if;
end process;
process(cnt)
begin
case cnt is
when "000" => bcd <=sec(3 downto 0);com <="111110";
when "001" => bcd <=sec(7 downto 4);com <="111101";
when "010" => bcd <=min(3 downto 0);com <="111011";
when "011" => bcd <=min(7 downto 4);com <="110111";
when "100" => bcd <=hour(3 downto 0);com <="101111";
when "101" => bcd <=hour(7 downto 4);com <="011111";
when others => bcd <= "0000";com <= "111111";
end case;
case bcd is
when "0000" => seg7 <= "00111111";
when "0001" => seg7 <= "00000110";
when "0010" => seg7 <= "00011011";
when "0011" => seg7 <= "01001111";
when "0100" => seg7 <= "01100110";
when "0101" => seg7 <= "01101101";
when "0110" => seg7 <= "01111101";
when "0111" => seg7 <= "00000111";
when "1000" => seg7 <= "01111111";
when "1001" => seg7 <= "01101111";
when others => seg7 <= "00000000";
end case;
end process;
seg<=seg7;
end architecture art;
6.系统的有关仿真
(1)计秒显示部分。
计分仿真图
计时仿真图