GL830 Datasheet_117

Genesys Logic, Inc.
GL830
USB 2.0 / PATA / SATA Bridge Controller Datasheet
Rev. 1.17 Jul 23, 2009

GL830 Datasheet
Copyright
Copyright ? 2009 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.
Ownership and Title
Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder.
Disclaimer
All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 https://www.360docs.net/doc/3416369102.html,
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GL830 Datasheet
Revision History
Revision 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 Date 06/14/2007 07/17/2007 08/21/2007 09/11/2007 12/11/2007 03/06/2008 03/25/2008 06/16/2008 07/30/2008 08/21/2008 First Formal Release Add 48 and 128 pin description Modify LQFP48/64/128 Description Modify Table 6.5-Reference Resistor Requirement, p.25 Add Windows Submission ID, Ch2, p.9 Modify 128 pin Description, p.12, p.15, p.18 Modify 64 pin & 128 pin Description, p.17, p.20 Add Power Pin Description, p.18 Modify Mode Selection Description, p.20 Modify Schmitt Trigger Description, p.24 Add Operating System Supported, Ch2, p.9 Modify Table 6.1-Maximum Ratings, p.24 Modify General Description, p.8 Modify Features, p.9 Modify LQFP 48 pin description, p.14, p.17 Modify block diagram, p. 24 Add Special Feature Description, p.26~p.28 Add EEPROM data structure, p. 29 Add LQFN 46 pin description, p.11, p.14, p.18~p.19, p.32 Modify Miscellaneous Interface, Ch3.3 Pin Description, p.17 Updated LQFN 46 pin , p.9, p.11, P.33 Modify: Features, Ch2, p.9 Power Pin, p.17, 18, 20 Test Pin, p.17, 18, 20, 22 Add Power Consumptions, Ch8.5, p.31~32 Modify Table 6.1- GPIO Descriptions, p.28 Modify Features, Ch2, p.9 Modify GPIO Descriptions, Table 6.1, p.28 Modify Features, Ch2, p.9 Modify LQFP 64 pin description, Table 3.7, p.19 Modify LQFP 128 pin description, Table 3.8, p 21 Add LQFP 64 pin (B) Ch1 general description, Table1.1, p.8 Add LQFP 64 pin (B) pinout diagram, p.13 Add table3.4-64 pin (B) pin list, p.16.17 Modified table 3.6-48 pin descriptions- miscellaneous interface, p.20 Modified table 3.7-46 pin descriptions- miscellaneous interface, p.21 Add Table 3.9-64 pin descriptions (B), p.23~24 Add Table 6.1-GPIO descriptions, p.33 Add Table 8.1-maximum Ratings, p.34 Add Table 8.5.1-power consumption, p.35 Description
1.10
09/10/2008
1.11 1.12
10/31/2008 12/12/2008
1.13
12/22/2008
1.14 1.15 1.16
12/30/2008 3/25/2009 5/18/2009
1.17
7/23/2009
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GL830 Datasheet
CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................... 8 CHAPTER 2 FEATURES .............................................................................. 9 CHAPTER 3 PIN ASSIGNMENT .............................................................. 10 3.1 Pinouts ..................................................................................................... 10 3.2 Pin List .................................................................................................... 15 3.3 Pin Descriptions...................................................................................... 19 CHAPTER 4 BLOCK DIAGRAM.............................................................. 29 CHAPTER 5 FUNCTION BLOCK DESCRIPTION ............................... 30 5.1 UTM......................................................................................................... 30 5.2 SIE ........................................................................................................... 30 5.3 EP0/EP3 FIFO and Bulk Buffer ........................................................... 30 5.4 Operation Register ................................................................................. 30 5.5 SPI Interface ........................................................................................... 30 5.6 PHY Layer .............................................................................................. 30 5.7 Link Layer .............................................................................................. 30 5.8 Transport Layer ..................................................................................... 30 5.9 Application Layer................................................................................... 30 CHAPTER 6 SPECIAL FEATURE DESCRIPTION............................... 31 6.1 Hard Disk Power Management Feature (Optional, only for HDD application) ................................................................................................... 31 6.2 Hard-Disk Write Protect (Only for HDD application)....................... 31 6.3 Hard Disk Lock/Unlock by EEPROM key (Only for HDD application) ................................................................................................... 32 6.4 General Purpose IO Description .......................................................... 33
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GL830 Datasheet
CHAPTER 7 ELECTRICAL CHARACTERISTICS............................... 34 7.1 Absolute Maximum Ratings.................................................................. 34 7.2 Temperature Conditions ....................................................................... 34 7.3 DC Characteristics ................................................................................. 34 7.3.1 I/O Type digital pins ....................................................................... 34 7.3.2 USB Interface DC Characteristics ................................................ 35 7.3.3 SATA Interface DC Characteristics ............................................. 35 7.3.4 Reference Clock Input Requirement ............................................ 35 7.3.5 Reference Resistor Requirement ................................................... 35 7.4 AC Characteristics ................................................................................. 35 7.4.1 USB Interface AC Characteristics ................................................ 35 7.4.2 SATA Interface AC Characteristics ............................................. 35 7.5 Power Consumptions ............................................................................. 35 7.5.1 Overall power consumption (Vdc=5V, TA= 25℃/ Maximum ℃ current)...................................................................................................... 35 7.5.2 Operating current breakdown (Vdc=5V, TA= 25℃/ Maximum ℃ current)...................................................................................................... 36 CHAPTER 8 PACKAGE DIMENSION..................................................... 37 CHAPTER 9 ORDERING INFORMATION ............................................ 41
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GL830 Datasheet
LIST OF FIGURES
Figure 3.1 - 48 Pin LQFP Pinout Diagram ....................................................................... 10 Figure 3.2 - 46 Pin LQFN Pinout Diagram....................................................................... 11 Figure 3.3 - 64 Pin LQFP Pinout Diagram (A)................................................................. 12 Figure 3.4 - 64 Pin LQFP Pinout Diagram (B) ................................................................. 13 Figure 3.5 - 128 Pin LQFP Pinout Diagram ..................................................................... 14 Figure 4.1 - Block Diagram ................................................................................................ 29 Figure 6.1 - Power Down Sequence for Hard-Disk Enclosure Application................... 31 Figure 6.2 - Write Protect Mechanism .............................................................................. 31 Figure 6.3 - Security by EEPROM key ............................................................................. 32 Figure 6.4 - Security by EEPROM key ............................................................................. 32 Figure 8.1 - GL830 48 Pin LQFP Package........................................................................ 37 Figure 8.2 - GL830 46 Pin LQFN Package ....................................................................... 38 Figure 8.3 - GL830 64 Pin LQFP Package........................................................................ 39 Figure 8.4 - GL830 128 Pin LQFP Package...................................................................... 40
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GL830 Datasheet
LIST OF TABLES
Table 1.1 - 48/46/64/128 pin feature comparison................................................................ 8 Table 3.1 - 48 Pin List ......................................................................................................... 15 Table 3.2 - 46 Pin List ......................................................................................................... 15 Table 3.3 - 64 Pin List (A)................................................................................................... 16 Table 3.4 - 64 Pin List (B) ................................................................................................... 16 Table 3.5 - 128 Pin List ....................................................................................................... 17 Table 3.6 - 48 Pin Descriptions........................................................................................... 19 Table 3.7 - 46 Pin Descriptions........................................................................................... 20 Table 3.8 - 64 Pin Descriptions (A) .................................................................................... 21 Table 3.9 - 64 Pin Descriptions (B) .................................................................................... 23 Table 3.10 - 128 Pin Descriptions....................................................................................... 25 Table 6.1 - GPIO Descriptions ........................................................................................... 33 Table 7.1 - Maximum Ratings............................................................................................ 34 Table 7.2 - Temperature Conditions ................................................................................. 34 Table 7.3 - I/O Type digital pins ........................................................................................ 34 Table 7.4 - Reference Clock Input Requirement.............................................................. 35 Table 7.5 - Reference Resistor Requirement .................................................................... 35 Table 9.1 - Ordering Information...................................................................................... 41
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GL830 Datasheet
CHAPTER 1 GENERAL DESCRIPTION
The GL830 is a highly-compatible, low cost USB 2.0 / PATA to SATA bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver/receiver and Serial ATA PHY. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and Serial ATA specification rev. 2.6. There are totally 4 endpoints in the GL830 controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL830 can support not only plug and play but also Windows Vista/ XP/ 2000/ ME default driver. The GL830 uses 25MHz crystal and slew-rate controlled pads to reduce the EMI issue. GL830 provides four package types –LQFP 48 pin (7x7mm), LQFN 46 pin (4.5x6.5mm), LQFP 64 pin (7x7mm) & LQFP 128 pin (14x14mm) for different target applications. 1. LQFP 48 pin package provides basic USB to SATA bridge function to fit standard USB 2.0 high speed storage class applications such as SATA HDD and ODD enclosure. It provides the best cost / performance solution in industry. In terms of cost, GL830 features on-chip 5V to 3.3V regulator and low pin count package to minimize overall system cost. In terms of performance, GL830 provides industry-leading data read / write speed and latency that powered by internal turbo 8051 micro processor. In terms of power consumption, GL830 features low-power mixed signal design to reduce silicon operating current. It also provides various power management options for system designer to reduce system level power consumption. LQFN 46 pin package provides the same function / performance as LQFP 48 pin. It features smaller silicon foot print and lower silicon operating temperature, which is perfect for mechanical limited PCB design. LQFP 64 pin (A) provides an additional SATA differential pair that enables USB / E-SATA (External SATA) to SATA function for HDD enclosures with both USB and E-SATA port. It features on-chip SATA switch that provides both E-SATA to SATA and USB to SATA data path in one single chip. LQFP 64 pin (B) supports dual LUN operation. It can connect to one ATA device and one SATA device. Main application is USB to PATA & SATA Combo Devices LQFP 128 pin integrates USB, PATA and SATA interface into one single chip. PATA interface can be configured as host or device that meet system requirement of various applications. For example, when PATA is in device mode, GL830 can be connected to embedded system’s legacy IDE port to serve as a multi-IO bridge for USB and SATA connection. When PATA is in host mode, GL830 is a USB to PATA and SATA bridge that enable concurrent data transfer on both USB to PATA and USB to SATA path.
2. 3.
4. 5.
Table 1.1 - 48/46/64/128 pin feature comparison
Applications USB host to SATA HDD / ODD USB / E-SATA host to SATA HDD USB / E-SATA / PATA host to SATA HDD USB host to PATA + SATA HDD
■
48 pin LQFP
■
46 pin LQFN
■
64 pin LQFP (A)
■ ■
64 pin LQFP (B)
■
128 pin LQFP
■ ■ ■ ■
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GL830 Datasheet
CHAPTER 2 FEATURES
· Complies with Universal Serial Bus specification rev. 2.0 (USB-IF test ID – 40000391) · Complies with USB Storage Class specification ver.1.0 (Bulk only protocol) · Operating system supported: Windows Vista32&64/XP/2000/Me/98/98SE, Mac OS 9.X/10.X, Linux Kernel 2.4.X/2.6.X. (Windows Submission ID : 1273643) · Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE) · Support 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3) · 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint · Complies with Serial ATA specification rev. 2.6 · Support SATA II asynchronous signal recovery feature(hot-plug) . Compliance with Serial ATA II Electrical Specification 1.0 . Complies with ATA/ATAPI-6 rev. 1.0 (only available for 128pin package) · On-chip SATA switch for E-SATA to SATA data path (only available for 64/128pin package) · Support Spread Spectrum Clocking to reduce EMI · Support Partial/Slumber power management (optional) . Support hard-disk power management feature (optional) . Support hard-disk write-protect function (only available for Windows XP/Vista, supported on 830-12 and later version) . Support hard-disk lock/unlock by EEPROM Key feature (complementary feature with Genesys Secured Backup software) · Provide adjustable TX signal amplitude and pre-emphasis level · Provide specified OOB signal detection and transmission · Embedded Turbo 8051 . On-chip Watch Dog Timer for auto error recovery (Supported on 830-12 and later version) · ROM size: 24K bytes; Bulk Buffer: 1K · Supports Power Down mode and USB suspend indicator · Supports USB 2.0 TEST mode features · Supports 4 PIO and 4 GPIO for programmable AP · Provides LED indicator for Full Speed and High Speed · Single 25 MHz external clock input · 3.3V power input; 5V tolerance pad · Embedded Regulator (3.3V to 1.8V) · Embedded Regulator (5V to 3.3V) · Provides SPI interface for Finger Print (only for 128 pin package) · Available in 48/64/128 pin LQFP and 46 pin LQFN
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GL830 Datasheet
CHAPTER 3 PIN ASSIGNMENT
3.1 Pinouts
AGND
AVDD
CVDD
CVDD
GND
VDD
GND
VDD
36
35
34
33
32
31
30
29
28
27
26 11 PIO1
10
HRST_
PIO3
GPIO0
GPIO3
CVDD
PIO0
Figure 3.1 - 48 Pin LQFP Pinout Diagram
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CVDD
GND
VDD
GND
TEST
12
1
2
3
4
5
6
7
8
9
25
DM
DP
X1
X2
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GL830 Datasheet
X12 CVDD RTERM PLLVDD PLLVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD GND RREF AVDD GPIO4 GPIO1 TXHIZ_ PIO2 GPIO2 PIO4 V5 VDD GND CVDD PIO1
AGND
Figure 3.2 - 46 Pin LQFN Pinout Diagram
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GL830 Datasheet
AGND3
AVDD3
RTERM
AGND
48 PLLVDD PLLVSS RXPEXT RXNEXT
TXNEXT
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33 32 31 30 29 28 27 26 25 NC NC GPIO1 NC NC PIO2 NC GPIO2 NC V5 VDD GND CVDD NC NC NC
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD GND
GL830
LQFP 64 (A)
AVDD 24 23 22 21 20 19 18 17 PIO1
CVDD
CVDD
CVDD
VDD
GND
MODE
TEST
NC
NC
NC
NC
HRST_
PIO3
NC
GPIO0
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GPIO3
Figure 3.3 - 64 Pin LQFP Pinout Diagram (A)
PIO0
RREF
GND
VDD
GND
VDD
DM
DP
X1
X2
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GL830 Datasheet
AVDD
AGND
48 CVDD RTERM PLLVDD PLLVSS
TXVSS
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33 32 31 30 29 28 27 26 25 AINTRQ DMACK_ AIORDY DIOR_ DIOW_ GPIO2 DMARQ VDD GND CVDD DD15 DD0 DD14 DD1 DD13 DD2
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD GND ARESET_ GPIO0
GL830
LQFP 64 (B)
AVDD 24 23 22 21 20 19 18 17 PIO0
CVDD
CVDD
VDD
GND
HRST_
TEST
DD7
DD8
DD9
DD5
DD4
DD10
DD11
DD3
Figure 3.4 - 64 Pin LQFP Pinout Diagram (B)
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DD12
DD6
RREF
CS1_
CS0_
VDD
VDD
DA2
DA0
DA1
DM
DP
X2
X1
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GL830 Datasheet 3.2 Pin List
Table 3.1 - 48 Pin List
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name GND GPIO0 GPIO3 PIO3 HRST_ CVDD VDD GND TEST PIO0 PIO1 CVDD Type Pin# P B B B I P P P I B B P 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name GND VDD V5 PIO4 GPIO2 PIO2 TXHIZ_ GPIO1 GPIO4 AVDD RREF AGND Type Pin# P P P B B B I B B P A P 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name DM DP AVDD AGND CVDD VDD GND VDD X2 X1 CVDD GND Type Pin# B B P P P P P P B I P P 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name RTERM PLLVDD PLLVSS TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD Type A P P P P O O I I P P P
Table 3.2 - 46 Pin List
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name Type Pin# GPIO0 GPIO3 PIO3 HRST_ CVDD VDD GND TEST PIO0 PIO1 CVDD GND B B B I P P P I B B P P 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name Type Pin# VDD V5 PIO4 GPIO2 PIO2 TXHIZ_ GPIO1 GPIO4 AVDD RREF AGND DM P P B B B I B B P A P B 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name Type Pin# DP AVDD AGND GND CVDD GND VDD X2 X1 CVDD RTERM PLLVDD B P P P P P P B I P A P 37 38 39 40 41 42 43 44 45 46 Pin Name Type PLLVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD GND P P O O I I P P P P
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GL830 Datasheet
Table 3.3 - 64 Pin List (A)
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name GPIO0 GPIO3 PIO3 NC HRST_ NC NC CVDD VDD MODE GND TEST NC NC PIO0 PIO1 Type Pin# B B B I P P I P I B B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name NC NC NC CVDD GND VDD V5 NC GPIO2 NC PIO2 NC NC GPIO1 NC NC Type Pin# P P P P B B B 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name AVDD RREF AGND DM DP AVDD3 AGND3 CVDD VDD GND VDD X2 X1 CVDD GND RTERM Type Pin# P A P B B P P P P P P B I P P A 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS CVDD GND Type P P I I O O P P O O I I P P P P
Table 3.4 - 64 Pin List (B)
Pin# 1 2 3 4 5 6 7 8 9 10 Pin Name DD7 DD8 HRST_ DD6 DD9 DD5 CVDD VDD GND DD10 Type Pin# B B I B B B P P P B 17 18 19 20 21 22 23 24 25 26 Pin Name DD2 DD13 DD1 DD14 DD0 DD15 CVDD GND VDD DMARQ Type Pin# B B B B B B P P P I 33 34 35 36 37 38 39 40 41 42 Pin Name AVDD RREF AGND DM DP AVDD CVDD DA1 DA0 DA2 Type Pin# P A P B B P P O O O 49 50 51 52 53 54 55 56 57 58 Pin Name CVDD RTERM PLLVDD PLLVSS TXVSS TXVDD TXP TXN RXN RXP Type P A P P P P O O I I
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Page 16

GL830 Datasheet
11 12 13 14 15 16
TEST DD4 DD11 DD3 DD12 PIO0
I B B B B B
27 28 29 30 31 32
GPIO2 DIOW_ DIOR_ AIORDY DMACK_ AINTRQ
B O O I O I
43 44 45 46 47 48
CS0_ CS1_ VDD VDD X2 X1
O O P P B I
59 60 61 62 63 64
RXVDD RXVSS CVDD GND ARESET_ GPIO0
P P P P O B
Table 3.5 - 128 Pin List
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Name GPIO0 GPIO3 PIO4 PIO3 ROM_A5 DD7 ROM_A11 DD8 HRST_ DD6 ROM_A4 DD9 ROM_A12 DD5 ROM_A3 CVDD CVDD VDD MOD0 GND DD10 ROM_A13 Type Pin# B B B B O B O B I B O B O B O P P P I P B O 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pin Name PIO0 PIO1 ROM_A0 DD2 ROM_D0 DD13 ROM_D7 DD1 ROM_D1 DD14 ROM_D6 DD0 ROM_D2 DD15 CVDD GND MODE1 VDD VDD V5 ROM_D5 DMARQ Type Pin# B B O B B B B B B B B B B B P P I P P I B B 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Pin Name AINTRQ AVDD AVDD RREF AGND AGND DM DP AVDD AGND GND GND CVDD DA1 DA0 NC DA2 ROM_D3 CS0_ ROM_D4 CS1_ GND Type Pin# B P P A P P B B P P P P P B B B B B B B P 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Pin Name NC NC NC NC NC NC NC PLLVDD PLLVDD PLLVSS RXPEXT RXNEXT TXNEXT TXPEXT TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS Type P P P I I O O P P O O I I P P
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GL830 Datasheet
23 24 25 26 27 28 29 30 31 32
TEST TXD RXD DD4 ROM_A2 DD11 ROM_A14 DD3 ROM_A1 DD12
I O B B O B O B O B
55 56 57 58 59 60 61 62 63 64
GPIO2 DIOW_ PIO2 DIOR_ T_ROM IORDY GPIO1 DMACK_ PHYRDY GPIO4
B B B B I B B B O B
87 88 89 90 91 92 93 94 95 96
VDD VDD GND GND VDD X2 X1 CVDD GND RTERM
P P P P P B I P P A
119 120 121 122 123 124 125 126 127 128
CVDD GND NC ROM_A8 ROM_A7 ROM_A9 ROM_A6 ROM_A10 ARESET_ SPDSEL
P P O O O O O B I
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Page 18

GL830 Datasheet 3.3 Pin Descriptions
Table 3.6 - 48 Pin Descriptions
USB Interface Pin Name RREF DM DP AVDD AGND Pin# 23 25 26 22,27 24,28 Type A B B P P Reference resistor USB DUSB D+ USB Analog 3.3V power USB Analog Ground Description
SATA Interface Pin Name RTERM PLLVDD PLLVSS TXVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS Pin# 37 38 39 40 41 42 43 44 45 46 47 Type A P P P P O O I I P P Reference resistor 1.8V Power Supplies for internal PLL Ground for internal PLL Ground for transceiver part 1.8V Power Supplies for transceiver part SATA Differential Transmit TX+ SATA Differential Transmit TXSATA Differential Receive RXSATA Differential Receive RX+ 1.8V Power Supplies for receiver part Ground for receiver part Description
Digital Power and Ground Pin Name CVDD VDD GND V5 Pin# 6,12,29, 35,48 7,14 30, 32 1,8,13, 31,36 15 Type P P P p Description 1.8V Digital Power (Pin #6 is 1.8V output) 3.3V Digital Power (Pin#14 is 3.3V output) Digital Ground 5V Power Input
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Page 19

GL830 Datasheet
Miscellaneous Interface Pin Name TEST X2 X1 HRST GPIO0~4 PIO0~4 TXHIZ_ Pin# 9 33 34 5 2,20,17,3, 21 10,11,18, 4, 16 19 Type I (pd) B I B (pu) B (pd) Description 0: Normal operation. 1: Chip will be put in test mode. Crystal Output Crystal Input
I (pu) HRST_ (Low active) General Purpose I/O #0~#4 Programmable I/O #0~#4
I (pu) 0: SATA TX is Hi-Z; 1: Normal
Table 3.7 - 46 Pin Descriptions
USB Interface Pin Name RREF DM DP AVDD AGND Pin# 22 24 25 21, 26 23, 27 Type A B B P P Reference resistor USB DUSB D+ USB Analog 3.3V power USB Analog Ground Description
SATA Interface Pin Name RTERM PLLVDD PLLVSS TXVDD TXP TXN RXN RXP RXVDD RXVSS Pin# 35 36 37 38 39 40 41 42 43 44 Type A P P P O O I I P P Reference resistor 1.8V Power Supplies for internal PLL Ground for internal PLL 1.8V Power Supplies for transceiver part SATA Differential Transmit TX+ SATA Differential Transmit TXSATA Differential Receive RXSATA Differential Receive RX+ 1.8V Power Supplies for receiver part Ground for receiver part Description
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Page 20