IDT7134LA35CI中文资料

IDT7134SA/LA

HIGH-SPEED

4K x 8 DUAL-PORT STATIC SRAM

Features

High-speed access

Military: 25/35/45/55/70ns (max.) Industrial: 55ns (max.)

Commercial: 20/25/35/45/55/70ns (max.)x

Low-power operation IDT7134SA

Active: 700mW (typ.)Standby: 5mW (typ.) IDT7134LA

Active: 700mW (typ.)Standby: 1mW (typ.)

x Fully asynchronous operation from either port x Battery backup operation 2V data retention x TTL-compatible; single 5V (±10%) power supply

x Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC x Military product compliant to MIL-PRF-38535 QML

Industrial temperature range ( 40°C to +85°C) is available for selected speeds

Functional Block Diagram

R/W L OE L

A 0L -A 11L

I/O 0L -I/O 7L

2720drw 01

CE L

A 0R -A 11R

I/O 0R -I/O 7R

OE R CE R

R/W R Description

The ID T7134 is a high-speed 4K x 8 D ual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when both sides simultaneously access the same Dual-Port RAM location.

The IDT7134 provides two independent ports with separate control,address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user s responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports. An automatic power down feature,controlled by CE , permits the on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT s CMOS high-performance technology, these Dual-Port typically operate on only 700mW of power. Low-power (LA)versions offer battery backup data retention capability, with each port typically consuming 200μW from a 2V battery.

The IDT7134 is packaged on either a sidebraze or plastic 48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

Pin Configurations (1,2,3)

NOTES:

1.All V CC pins must be connected to the power supply.

2.All GND pins must be connected to the ground supply.

3.P48-1 package body is approximately .55 in x .61 in x .19 in.C48-2 package body is approximately .62 in x 2.43 in x .15 in.J52-1 package body is approximately .75 in x .75 in x .17 in.L48-1 package body is approximately .57 in x .57 in x .68 in.F48-1 package body is approxiamtely .75 in x .75 in x .11 in.

4.This package code is used to reference the package diagram.

5.This text does not indicate orientation of actual part-marking.

A 10R 2720drw 02

I/O 0R

I/O 1R I/O 2R I/O 3R I/O 4R I/O 5R I/O 6R I/O 7R A 9R A 8R A 7R A 6R A 4R A 3R A 2R A 1R A 0R

A 0L A 1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O I/O I/O I/O I/O I/O CE L R/W L OE L V CC

A 5R R OE A 11R R/W R CE R A 11L A 10L 2720drw 03

INDEX

N /C G N D

I /O 4L

I /O 5L

I /O 6L

I /O 7L

I /O 0R

I /O 1R

I /O 2R

I /O 3R

I /O 4R

I /O 5R

I /O 6R

OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R N/C I/O 7R

E L

/W L

/W R

/C 2720drw 04

INDEX

G N D I /O 3L

I /O 4L

I /O 5L

I /O 6L

I /O 0R

I /O 1R

I /O 2R

I /O 3R

I /O 4R

I /O 5R

I /O 7L

A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R I/O 6R

I/O 7R C

Capacitance (1)

(T A = +25°C, f = 1.0MHz)

Absolute Maximum Ratings (1)

Recommended Operating

Temperature and Supply Voltage (1,2)

Recommended DC Operating Conditions

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (V CC = 5V ± 10%)

NOTES:

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.V TERM must not exceed Vcc + 10% for more than 25%of the cycle time or 10 ns

maximum, and is limited to < 20mA for the period of V TERM > Vcc +10%.3.V TERM = 5.5V.

NOTES:

1.This parameter is determined by device characterization but is not production tested.

2.3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V and from 3V to 0V.

NOTES:

1.This is the parameter T A .

2.Industrial temperature: for specific speeds, packages and powers contact your sales office.

NOTES:

1.V IL (min.) > -1.5V for pulse width less than 10ns.

2.V TERM must not exceed Vcc + 10%.

NOTES:

1.At Vcc <

2.0V input leakages are undefined.

Symbol Rating Commercial & Industrial Military Unit V TERM

(2)

T erminal Voltage with Respect to GND -0.5 to +7.0

-0.5 to +7.0

T BIAS T emperature Under Bias -55 to +125-65 to +135o

C T STG Storage T emperature -55 to +125

-65 to +150

P T (3)Power Dissipation 1.5 1.5W I OUT

DC Output Current

2720 tbl 01

Grade Ambient Temperature GND Vcc Military

-55O C to +125O C 0V 5.0V + 10%Commercial 0O C to +70O C 0V 5.0V + 10%Industrial

-40O C to +85O C

5.0V + 10%

2720 tbl 03

Symbol Parameter

Min.Typ.Max.Unit V CC Supply Voltage 4.5 5.0 5.5V GND Ground

0V V IH

Input High Voltage 2.2____ 6.0(2)V V IL

Input Low Voltage

-0.5(1)

____

0.8

2720 tbl 04

Symbol Parameter Conditions (2)Max.Unit C IN Input Capacitance V IN = 3dV 11pF C OUT

Output Capacitance

V OUT = 3dV

2720 tbl 02

Symbol Parameter

Test Conditions

7134SA

7134LA Unit Min.

Max.Min.

Max.|I LI |Input Leakage Current (1)V CC = 5.5V, V IN = 0V to V CC ___10___5μA |I LO |Output Leakage Current CE - V IH , V OUT = 0V to V CC ___10___5μA V OL

Output Low Voltage

I OL = 6mA ___0.4___0.4V I OL = 8mA

___

0.5

___

0.5

V V OH

Output High Voltage

I OH = -4mA

2.4___

2.4

___

2720 tbl 05

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (1,2,4) (V CC = 5.0V ± 10%)

NOTES:

1.'X' in part number indicates power rating (SA or LA).

2.V CC = 5V, T A = +25°C for typical, and parameters are not production tested.

3.f MAX = 1/t RC = All inputs cycling at f = 1/t RC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby I SB3.

4.Industrial temperature: for other speeds, packages and powers contact your sales office.

7134X20Com'l Only

7134X25Com'l &Military 7134X35Com'l &Military Symbol Parameter Test Condition

Version Typ.Max.Typ.Max.Typ.Max.Unit I CC

Dynamic Operating Current

(Both Ports Active)

CE = V IL

Outputs Open f = f MAX (3)

COM'L SA LA 170170

280240

160160280220150150260210mA

MIL &IND SA LA ________

________

160160310260150150300250I SB1

Standby Current (Both Ports - TTL Level Inputs)

CE L and CE R = V IH f = f MAX (3)

COM'L SA LA 2525

10080

2525805025257545mA

MIL &IND

SA LA ________

________

25251008025257555I SB2

Standby Current (One Port - TTL Level Inputs)

CE "A" = V IL and CE "B" = V IH Active Port Outputs Open,f=f MAX (3)

COM'L SA LA 105105

180150

95951801408585170130mA

MIL &IND SA LA ________

________

95952101708585200160I SB3

Full Standby Current (Both Ports -CMOS Level Inputs)

Both Ports CE L and CE R > V CC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V, f = 0(3)

COM'L SA LA 1.00.2

154.5

1.00.2154.0 1.00.2154.0mA

MIL &IND SA LA ________

________

1.00.23010 1.00.23010I SB4

Full Standby Current (One Port -CMOS Level Inputs)

One Port CE "A" or CE "B" > V CC - 0.2V

V IN > V CC - 0.2V or V IN < 0.2V Active Port Outputs Open,f = f MAX (3)

COM'L SA LA 105105

170130

95951701208585160110mA

MIL &IND

SA LA

________

9595

210150

8585

190130

2720 tbl 06a

7134X45Com'l &Military

7134X55Com'l, Ind & Military 7134X70Com'l &Military Symbol Parameter Test Condition

Version Typ.Max.Typ.Max.Typ.Max.Unit I CC

Dynamic Operating Current

(Both Ports Active)

CE = V IL

Outputs Open f = f MAX (3)

COM'L SA LA 140140240200140140240200140140240200mA

MIL &IND SA LA 140140280240140140270220140140270220I SB1

Standby Current (Both Ports - TTL Level Inputs)

CE L and CE R = V IH f = f MAX (3)

COM'L SA LA 252570402525704025257040mA

MIL &IND

SA LA 252570502525705025257050I SB2

Standby Current (One Port - TTL Level Inputs)

CE "A" = V IL and CE "B" = V IH Active Port Outputs Open,f=f MAX (3)

COM'L SA LA 757516013075751601307575160130mA

MIL &IND SA LA 757519015075751801507575180150I SB3

Full Standby Current (Both Ports -CMOS Level Inputs)

Both Ports CE L and CE R > V CC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V, f = 0(3)

COM'L SA LA 1.00.2154.0 1.00.2154.0 1.00.2154.0mA

MIL &IND SA LA 1.00.23010 1.00.23010 1.00.23010I SB4

Full Standby Current (One Port -CMOS Level Inputs)

One Port CE "A" or CE "B" > V CC - 0.2V

V IN > V CC - 0.2V or V IN < 0.2V Active Port Outputs Open,f = f MAX (3)

COM'L SA LA 757515010075751501007575150100mA

MIL &IND

SA LA

7575

180120

7575

170120

7575

170120

2720 tbl 06b

V CC

2720drw 05

Data Retention Characteristics Over All Temperature Ranges

(LA Version Only) V LC = 0.2V, V HC = V CC - 0.2V

Data Retention Waveform

AC Test Conditions

Figure 1. AC Output Test Load

Figure 2. Output Test Load (for t LZ , t HZ , t WZ , t OW )*Including scope and jig

DATA OUT

2720drw 06?

DATA OUT

2720drw 07

NOTES:

1.V CC = 2V, T A = +25°C, and are not production tested.

2.t RC = Read Cycle Time.

3.This parameter is guaranteed by device characterization, but not production tested.

Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load

GND to 3.0V

5ns 1.5V 1.5V Figures 1 and 2

2720 tbl 08

Symbol Parameter

Test Condition

Min.Typ.(1)

Max.

Unit V DR V CC for Data Retention V CC = 2V 2.0

___

V I CCDR

Data Retention Current

CE > V HC

V IN > V HC or < V LC

MIL. & IND.___1004000μA

COM'L.

___

100

1500

t CDR (3)Chip Dese lect to Data Retention Time 0______ns t R (3)

Operation Recovery Time

t RC (2)

___

2720 tbl 07

NOTES:

1.Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2.This parameter is guaranteed by device characterization, but is not production tested.

3.'X' in part number indicates power rating (SA or LA).

4.Industrial temperature: for other speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage (3,4)

7134X20Com'l Only

7134X25Com'l &Military 7134X35Com'l &Military Unit

Symbol Parameter Min.Max.

Min.

Max.

Min.

Max.

READ CYCLE t RC Read Cycle Time 20

____

ns t AA Address Access Time ____20____25____35ns t ACE Chip Enable Access Time ____20____25____35ns t AOE Output Enable Access Time ____

____

ns t OH Output Hold from Address Change 0____0____0____ns t LZ Output Low-Z Time (1,2)0

____

ns t HZ Output High-Z Time (1,2)

____

ns t PU Chip Enable to Power Up Time (2)0

____

ns t PD

Chip Disable to Power Down Time (2)

____

20____

25____

2720 tbl 09a

7134X45Com'l &Military

7134X55Com'l, Ind & Military 7134X70Com'l &Military Unit

Symbol Parameter Min.Max.

Min.

Max.

Min.

Max.

READ CYCLE t RC Read Cycle Time 45

____

ns t AA Address Access Time ____45____55____70ns t ACE Chip Enable Access Time ____45____55____70ns t AOE Output Enable Access Time ____

____

ns t OH Output Hold from Address Change 0____0____0____ns t LZ Output Low-Z Time (1,2)5

____

ns t HZ Output High-Z Time (1,2)

____

ns t PU Chip Enable to Power Up Time (2)0

____

ns t PD

Chip Disable to Power Down Time (2)

____

45____

50____

2720 tbl 09b

Timing Waveform of Read Cycle No. 1, Either Side (1,2,4)

Timing Waveform of Read Cycle No. 2, Either Side (1,3)

NOTES:

1.Timing depends on which signal is asserted last, OE or CE .

2.Timing depends on which signal is de-asserted first, OE or CE .

3.R/W = V IH .

4.Start of valid data depends on which timing becomes effective, t AOE , t ACE or t AA

5.t AA for RAM Address Access and t SAA for Semaphore Address Access.

ADDRESS

DATA OUT

2720drw 08

2720drw 09

DATA OUT

I CC

I SB

CURRENT

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage (5,7)

NOTES:

1.Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2.This parameter is guaranteed by device characterization, but is not production tested.

3.The specification for t DH must be met by the device supplying write data to the RAM under all operating conditions. Although t DH and t OW values will vary over voltage and temperature, the actual t DH will always be smaller than the actual t OW .

4.Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port-to-Port Read .

5.'X' in part number indicates power rating (SA or LA).

6.t DDD = 35ns for military temperature range.

7.Industrial temperature: for other speeds, packages and powers contact your sales office.

Symbol Parameter 7134X20Com'l Only

7134X25Com'l &Mil itary 7134X35Com'l &Mil itary Unit

Min.Max.

Min.

Max.

Min.

Max.

WRITE CYCLE t WC Write Cycle Time

20____25____35____ns t EW Chip Enable to End-of-Write 15____20____30____ns t AW Address Valid to End-of-Write 15____20____30____ns t AS Address Set-up Time 0____0____0____ns t WP Write Pulse Width 15____20____25____ns t WR Write Recovery Time 0____0____0____ns t DW Data Valid to End-of-Write 15

____

ns t HZ Output Hig h-Z Time (1,2)____

____

ns t DH Data Hold Time (3)

____

ns t WZ Write Enable to Output in High-Z (1,2)____

____

ns t OW Output Active from End-of-Write (1,2,3)3

____

ns t WDD Write Pulse to Data Delay (4)

____40____50____60ns t D DD

Write Data Valid to Read Data Delay (4,6)

____

2720 tbl 10a

Symbol Parameter 7134X45Com'l &Mil itary

7134X55Com'l, Ind & Military 7134X70Com'l &Mil itary

Unit

Min.Max.Min.

Max.

Min.Max.WRITE CYCLE t WC Write Cycle Time

45____55____70____ns t EW Chip Enable to End-of-Write 40____50____60____ns t AW Address Valid to End-of-Write 40____50____60____ns t AS Address Set-up Time 0____0____0____ns t WP Write Pulse Width 40____50____60____ns t WR Write Recovery Time 0____0____0____ns t DW Data Valid to End-of-Write 20

____

ns t HZ Output Hig h-Z Time (1,2)____

____

ns t DH Data Hold Time (3)

____

ns t WZ Write Enable to Output in High-Z (1,2)____

____

ns t OW Output Active from End-of-Write (1,2,3)3

____

ns t WDD Write Pulse to Data Delay (4)

____70____80____90ns t D DD

Write Data Valid to Read Data Delay (4,6)

____

2720 tbl 10b

R/W "A"(1)

ADDR "A"

DATA IN "A"

DATA OUT "B"

ADDR "B"Timing Waveform of Write Cycle No. 1, R/W Controlled Timing (1,5,8)

Timing Waveform of Write with Port-to-Port Read (1,2,3)

NOTES:

1.Write cycle parameters should be adhered to, in order to ensure proper writing.

2.CE L = CE R = V IL. OE "B" = V IL.

3.Port "A" may be either left or right port. Port "B" is the opposite from port "A".

NOTES:

1.R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t EW or t WP ) of a CE =V IL and R/W = V IL .

3.t WR is measured from the earlier of CE or R/W going to V IH to the end-of-write cycle.

4.During this period, the I/O pins are in the output state, and input signals must not be applied.

5.If the CE = V IL transition occurs simultaneously with or after the R/W = V IL transition, the outputs remain in the High-impedance state.

6.Timing depends on which enable signal (CE or R/W ) is asserted last.

7.This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load (Figure 2).

8.If OE = V IL during a R/W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be placed on the bus

for the required t DW . If OE = V IH during an R /W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .

DATA IN

ADDRESS

R/W

DATA OUT

Truth Table I Read/Write Control

Functional Description The IDT7134 provides two ports with separate control, address,and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by C E . The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE ). In the read mode, the port s OE turns on the output drivers when set LOW. Non-contention READ/WRITE conditions are illustrated in the table below.

Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,4)

NOTES:

1.R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t EW or t WP ) of a CE =V IL and R/W = V IL .

3.t WR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.

4.If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

5.Timing depends on which enable signal (CE or R/W ) is asserted last.

NOTE:

1.A 0L - A 11L ≠ A 0R - A 11R

"H" = V IH , "L" = V IL , "X" = Don t Care, and "Z" = High Impedance

Left or Right Port (1)

W CE OE D 0-7Function

X H X Z Port Deselected and in Power-Down Mode, I SB2 or I SB4

X H X Z CE R = CE L = H, Power Down Mode I SB1 or I SB3

L L X DAT A IN Data on port written into memory H L L DAT A OUT

Data in memory output on port X

High impedance outputs

2720 tbl 11

R/W

ADDRESS

DATA IN

Ordering Information

2720drw 13

IDT

XXXX A 999A A Device Type

Power

Speed

Package

Process/Temperature Range

Blank I (1)B P C J L48F 202535455570LA SA 7134

Commercial (0°C to +70°

C)Industrial (-40°C to +85°C)Military (-55°C to +125°C)

Compliant to MIL-PRF-38535QML 48-pin Plastic DIP (P48-1)48-pin Ceramic DIP (C48-2)52-pin PLCC (J52-1)48-pin LCC (L48-1)

48-pin Ceramic Flatpack (F48-1)Speed in nanoseconds

Low Power

Standard Power

32K (4K x 8-Bit)Dual-Port RAM

Commercial Only

Commercial &Military Commercial &Military Commercial &Military

Commercial,Industrial &Military Commercial &Military NOTE:

1.Industrial temperature is available for PLCC packages in standard power.

For other speeds, packages and powers contact your sales office.

Datasheet Document History

3/25/99

Initiated datasheet document history Converted to new format

Cosmetic and typographical corrections

Pages 2 Added additional notes to pin configurations 6/9/99:

Changed drawing format