SSD2825 Application Notes_120 pin_TS5K_v01_2 0

SSD2825

Application Note

640 x 960 with MIPI 4-Lane Master Bridge Chip

CONTENTS

1OVERVIEW (3)

2HARDWARE CONFIGURATION (4)

2.1P OWER (4)

2.2D ISPLAY T IMING (6)

3SOFTWARE CONFIGURATION (8)

Solomon Systech Aug 2011 P 2/10 Rev 0.20 SSD2825

1Overview

The SSD2825 is an MIPI master bridge chip that connects an application processor with traditional parallel LCD interface and an LCD driver with MIPI slave interface.

This document introduces how to drive the panel with 640 x 960 for both hardware and software configuration.

SSD2825 Rev 0.20 P 3/10 Aug 2011 Solomon Systech

Solomon Systech

Aug 2011 P 4/10

Rev 0.20 SSD2825

2 Hardware Configuration

2.1 Power

1. Power supply:

3.3V (TS5K connector) 5V (TS5K connector) Backlight = 16V GND

Ensure the 1.8V and 1.2V is regulated

Backlight

30 pin generic output

1.2V regulator

1.8 regulator

C r y s t a l SSD2825 Chip

With 120 pins connection

TS5K connector – 50 pins

Figure 2.1.1 D emo board layout

Figure 2.1.2 Pin assignment of the TS5K header

SSD2825 Rev 0.20

P 5/10

Aug 2011

Solomon Systech

Figure 2.1.3 Pin assignment of the standard 30 pin MIPI connector

Figure 2.1.4 Demo board

Backligh t

Solomon Systech

Aug 2011 P 6/10

Rev 0.20

SSD2825

2.2 Display Timing (Example for 640 x 960 display panel)

Provide the clock cycle to DOTCLK, DEN, VSYN, HSYN in “Input Signal”.

Item

Unit

Typical Vertical active period VACT line 960 Vertical front porch VFP line 12 Vertical back porch VBP line 12 Vertical low pulse width VS

line 16

Figure 2.2.1 Vertical timing

Item Unit Typical Horizontal active period HACT clk 640 Horizontal front porch HFP clk 14 Horizontal back porch HBP clk 14 Horizontal low pulse width HS clk 16

Below illustrate the timing diagram with DOTCLK=50MHz

VSYN

HSYN

DEN

Item Value

Vertical back porch VBP 164us

Vertical low pulse width VS 220us

Vertical front porch VFP 164us

Vertical active period VACT 13ms

Figure 2.2.3 Vertical timing with DOTCLK 50MHz

HSYN

DEN

Item Value

Horizontal back porch HBP 280ns

Horizontal low pulse width HS 320ns

Horizontal front porch HFP 280ns

Horizontal active period HACT 12.8ns

Figure 2.2.4 Horizontal timing with DOTCLK 50MHz

SSD2825 Rev 0.20 P 7/10 Aug 2011 Solomon Systech

3Software Configuration

The turn on sequence of 640 x 960 LCD driver is illustrated.

Interface: RGB + SPI (3 wire 24-bit)

MIPI: 4 lane

Figure 3.1.1 Illustration of Write Operation for 24 bit 3 wire Interface

Solomon Systech Aug 2011 P 8/10 Rev 0.20 SSD2825

SSD2825 Rev 0.20

P 9/10

Aug 2011

Solomon Systech

Figure 3.2 Flow chart for controlling SSD2825 and LCD module

1. Initial code 1: SSD2825 initialization

Vertical sync and horizontal sync active period 0xB2 1C1E Vertical and horizontal back porch period 0xB3 0C0E Vertical and horizontal front porch period 0xB4 0280 Horizontal active period 0xB5 03C0 Vertical active period 0xB6 0007 Video mode and video pixel format MIPI lane configuration 0xDE 0002 MIPI lane select 0xD6 0004 Color order and endianess 0xB9 0000 Disable PLL 0xC4 0001 BTA setting CABC brightness setting 0xE9 FF2F CABC control 0xEB 0100 CABC control

Communicate with LCD driver through MIPI 0xB7 0342 DCS mode 0xB8 0000 VC register 0xBC 0000 Packet size 0x11 LCD driver exit sleep mode 0x29 Set LCD driver display on PLL configuration 0xBA 8028 PLL setting 0xBB 0006 LP clock divider 0xB9 0001 PLL enable 0xB8 0000 VC register

0xB7 030B Generic mode, HS video mode

Wait 2000ms

2.Initial code 2: LCD driver initialization

MIPI lane and PLL configuration

0xB9 0001 PLL enable

0xB7 0302 Generic mode, LP mode

0xB8 0000 VC register

Send command and data through MIPI

0xBC 0002 Packet size

0xBF 00B2 Manufacturer command

0xBC 0005 Packet size

0xBF 03B7 Lane setting for LCD driver

0000 Lane setting for LCD driver

Wait 2000ms

3.Cmd code 3: Access video mode

RGB interface configuration

0xB1 1010 Vertical sync and horizontal sync active period

0xB2 1C1E Vertical and horizontal back porch period

0xB3 0C0E Vertical and horizontal front porch period

0xB4 0280 Horizontal active period

0xB5 03C0 Vertical active period

0xB6 0007 Video mode and video pixel format

MIPI lane configuration

0xDE 0003 MIPI lane select

0xD6 0004 Color order and endianess

0xB9 0000 Disable PLL

0xC4 0001 BTA setting

CABC brightness setting

0xE9 FF2F CABC control

0xEB 0100 CABC control

Wait 200ms

PLL configuration

0xBA 8028 PLL setting

0xBB 0006 LP clock divider

0xB9 0001 PLL enable

0xB8 0000 VC register

0xB7 030B Generic mode, HS video mode

Solomon Systech Aug 2011 P 10/10 Rev 0.20 SSD2825

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SSD2825 Rev 0.20 P 11/10 Aug 2011 Solomon Systech