M312L5628BT0-A2中文资料

DDR SDRAM Registered Module

( TSOP-II )

184pin Registered Module based on 512Mb B-die with 1,700 / 1,200mil Height & 72-bit ECC

Revision 1.0

December. 2003

Revison 1.0 December, 2003

Revision History

Revision 0.0 (February, 2003)

- First release

Revision 0.1 (July, 2003)

- Deleted speed B3

Revision 0.2 (August, 2003)

- Corrected typo.

Revision 1.0 (December, 2003)

- IDD current revision.

- Finalized

Revison 1.0 December, 2003

184Pin Registered DIMM based on 512Mb B-die (x4, x8)

Ordering Information

Part Number Density Organization Component Composition Heihgt M383L6523BTS-CAA/A2/B0/A0512MB64M x 72 64Mx8( K4H510838B) * 9EA1,700mil M383L2923BTS-CAA/A2/B0/A01GB128M x 72 64Mx8( K4H510838B) * 18EA1,700mil M383L2920BTS-CAA/A2/B0/A01GB128M x 72 128Mx4( K4H510438B) * 18EA1,700mil M383L5628BT1-CAA/A2/B0/A02GB256M x 72 st.256Mx4( K4H1G0638B) * 18EA1,700mil M312L6523BTS-CAA/A2/B0/A0512MB64M x 72 64Mx8( K4H510838B) * 9EA1,200mil M312L2923BTS-CAA/A2/B0/A01GB128M x 72 64Mx8( K4H510838B) * 18EA1,200mil M312L2920BTS-CAA/A2/B0/A01GB128M x 72 128Mx4( K4H510438B) * 18EA1,200mil M312L5628BT0-CAA/A2/B0/A02GB256M x 72 st.256Mx4( K4H1G0638B) * 18EA1,200mil

Operating Frequencies

AA(DDR266@CL=2)A2(DDR266@CL=2)B0(DDR266@CL=2.5)A0(DDR200@CL=2) Speed @CL2133MHz133MHz100MHz100MHz

Speed @CL2.5133MHz133MHz133MHz-

CL-tRCD-tRP2-2-22-3-3 2.5-3-32-2-2 Feature

? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

? Double-data-rate architecture; two data transfers per clock cycle

? Bidirectional data strobe(DQS)

? Differential clock inputs(CK and CK)

? DLL aligns DQ and DQS transition with CK transition

? Programmable Read latency 2, 2.5 (clock)

? Programmable Burst length (2, 4, 8)

? Programmable Burst type (sequential & interleave)

? Edge aligned data output, center aligned data input

? Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

? Serial presence detect with EEPROM

? 1,700mil / 1,200mil height & double sided

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Revison 1.0 December, 2003

Pin Configuration (Front side/back side)

Note :

1. * : These pins are not used in this module.

2. Pins 111, 158 are NC for 1row module [ M383(12)L6523BTS, M383(12)L2920BTS ] & used for 2row module [ M383(12)L2923BTS, M383(12)L5628BT1(0) ]

3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 12345678910111213141516171819202122232425262728293031

VREF DQ0VSS DQ1DQS0DQ2VDD DQ3NC /RESET VSS DQ8DQ9DQS1VDDQ *CK1*/CK1VSS DQ10DQ11CKE0VDDQ DQ16DQ17DQS2VSS A9DQ18A7VDDQ DQ19

323334353637383940414243444546474849505152535455565758596061

A5DQ24VSS DQ25DQS3A4VDD DQ26DQ27A2VSS A1CB0CB1VDD DQS8A0CB2VSS CB3BA1

DQ32VDDQ DQ33DQS4DQ34VSS BA0DQ35DQ40

62636465666768697071727374757677787980818283848586878889909192

VDDQ /WE DQ41/CAS VSS DQS5DQ42DQ43VDD */CS2DQ48DQ49VSS *CK2*/CK2VDDQ DQS6DQ50DQ51VSS VDDID DQ56DQ57VDD DQS7DQ58DQ59VSS NC SDA SCL

93949596979899100101102103104105106107108109110111112113114115116117118119120121122123

VSS DQ4DQ5VDDQ DM0/DQS9

DQ6DQ7VSS NC NC NC VDDQ DQ12DQ13DM1/DQS10

VDD DQ14DQ15CKE1VDDQ *BA2DQ20 A12VSS DQ21A11

DM2/DQS11

VDD DQ22A8DQ23

124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153

VSS A6DQ28DQ29VDDQ DM3/DQS12

A3DQ30VSS DQ31CB4CB5VDDQ CK0/CK0VSS DM8/DQS17

A10CB6VDDQ CB7

VSS DQ36DQ37VDD DM4/DQS13

DQ38DQ39VSS DQ44

154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184

/RAS DQ45VDDQ /CS0/CS1DM5/DQS14

VSS DQ46DQ47*/CS3VDDQ DQ52DQ53*A13VDD DM6/DQS15

DQ54DQ55VDDQ NC DQ60DQ61VSS DM7/DQS16

DQ62DQ63VDDQ SA0SA1SA2VDDSPD

Pin Description

Pin Name

Function

Pin Name Function

A0 ~ A12Address input (Multiplexed)DM0 ~ DM8Data - in mask BA0 ~ BA1Bank Select Address VDD Power supply (2.5V)

DQ0 ~ DQ63Data input/output VDDQ Power Supply for DQS(2.5V)DQS0 ~ DQS17Data Strobe input/output VSS Ground

CK0,CK0

Clock input VREF Power supply for reference

CKE0, CKE1(for 2 Row)Clock enable input VDDSPD Serial EEPROM Power/Supply ( 2.3V to 3.6V )CS0, CS1(for 2 Row)Chip select input SDA Serial data I/O RAS Row address strobe SCL Serial clock

CAS Column address strobe SA0 ~ 2Address in EEPROM WE Write enable

No connection

CB0 ~ CB7

Check bit(Data-in/data-out)

KEY

512MB, 64M x 72 ECC Module (M383(12)L6523BTS) (Populated as 1 bank of x8 DDR SDRAM Module)

1GB, 128M x 72 ECC Module (M383(12)L2923BTS) (Populated as 2 bank of x8 DDR SDRAM Module)

1GB, 128M x 72 ECC Module (M383(12)L2920BTS) (Populated as 1 bank of x4 DDR SDRAM Module)

2GB, 256M x 72 ECC Module [ M383(12)L5628BT1(0) ] (Populated as 2 bank of x4 DDR SDRAM Module)

Revison 1.0 December, 2003

Absolute Maximum Ratings

Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN , V OUT -0.5 ~ 3.6V Voltage on V DD supply relative to Vss V DD,V DDQ -1.0 ~ 3.6V Storage temperature T STG -55 ~ +150?C Power dissipation P D 1.5 * # of component

W Short circuit current

I OS

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :Power & DC Operating Conditions (SSTL_2 In/Out)

Notes : 1. Includes ??25mV margin for DC offset on V REF , and a combined total of ??50mV margin for all AC noise and DC offset on

V REF , bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V REF and internal DRAM noise coupled to V REF , both of which may result in V REF noise. V REF should be de-coupled with an inductance of ??3nH.

2. V TT is not applied directly to the device. V T T is a system supply for signal termination resistors, is expected to be set equal to

V REF , and must track variations in the DC level of V REF

3. V I D is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHz.

Recommended operating conditions (Voltage referenced to V SS =0V, T A =0 to 70?C)

Parameter

Symbol Min Max Unit

Note

Supply voltage(for device with a nominal V DD of 2.5V)V DD 2.3 2.7I/O Supply voltage V DDQ 2.3 2.7V I/O Reference voltage

V REF VDDQ/2-50mV VDDQ/2+50mV V 1I/O Termination voltage(system)V TT V REF -0.04V REF +0.04V 2Input logic high voltage V I H (DC)V REF +0.15

V DDQ +0.3V 4Input logic low voltage

V IL (DC)-0.3V REF -0.15V 4

Input Voltage Level, CK and CK inputs V I N (DC)-0.3V DDQ +0.3V Input Differential Voltage, CK and CK inputs V I D (DC)

0.3V DDQ +0.6

V 3Input leakage current I I -22uA Output leakage current

I OZ -55

uA Output High Current(Normal strengh driver) ;V OUT = V T T + 0.84V

I OH -16.8mA Output High Current(Normal strengh driver) ;V OUT = V T T - 0.84V

I OL 16.8mA Output High Current(Half strengh driver) ;V OUT = V T T + 0.45V

I OH -9mA Output High Current(Half strengh driver) ;V OUT = V T T - 0.45V

I OL

DDR SDRAM IDD spec table

M383(12)L6523BTS [ (64M x 8) * 9 , 512MB Module ]

(V DD=2.7V, T = 10?C) Symbol AA(DDR266@CL=2)A2(DDR266@CL=2)B0(DDR266@CL=2.5)A0(DDR200@CL=2)Unit Notes IDD01,6201,4901,4901,490mA

IDD11,8401,7201,7201,720mA

IDD2P370350350350mA

IDD2F895770770770mA

IDD2Q505480480480mA

IDD3P595570570570mA

IDD3N1,080950950950mA

IDD4R1,9801,8501,8501,850mA

IDD4W2,0201,9001,9001,900mA

IDD52,7902,6602,6602,660mA IDD6Normal370350350350mA Low power350330330330mA Optional IDD7A3,6703,5603,5603,560mA

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M383(12)L2923BTS [ (64M x 8) * 18 , 1GB Module ]

(V DD=2.7V, T = 10?C) Symbol AA(DDR266@CL=2)A2(DDR266@CL=2)B0(DDR266@CL=2.5)A0(DDR200@CL=2)Unit Notes IDD02,1902,1902,1902,190mA

IDD12,4202,4202,4202,420mA

IDD2P540540540540mA

IDD2F1,2901,2901,2901,290mA

IDD2Q810810810810mA

IDD3P990990990990mA

IDD3N1,6501,6501,6501,650mA

IDD4R2,5502,5502,5502,550mA

IDD4W2,6002,6002,6002,600mA

IDD53,3603,3603,3603,360mA IDD6Normal540540540540mA Low power500500500500mA Optional IDD7A4,2604,2604,2604,260mA

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Revison 1.0 December, 2003

DDR SDRAM IDD spec table

M383(12)L2920BTS [ (128M x 4) * 18 , 1GB Module ]

M383(12)L5628BT1(0) [ (st.256M x 4) * 18 , 2GB Module ]

(V DD =2.7V, T = 10?C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol AA(DDR266@CL=2)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

A0(DDR200@CL=2)

Unit Notes

IDD02,6102,6102,6102,610mA IDD13,0103,0103,0103,010mA IDD2P 420420420420mA IDD2F 1,1701,1701,1701,170mA IDD2Q 690690690690mA IDD3P 870870870870mA IDD3N 1,5301,5301,5301,530mA IDD4R 3,3303,3303,3303,330mA IDD4W 3,4203,4203,4203,420mA IDD54,9504,9504,9504,950mA IDD6

Normal 420420420420mA Low power 380380380380mA Optional IDD7A

6,750

(V DD =2.7V, T = 10?C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol AA(DDR266@CL=2)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

A0(DDR200@CL=2)

Unit Notes

IDD03,7603,7603,7603,760m A IDD14,2104,2104,2104,210m A IDD2P 760760760760m A IDD2F 1,9601,9601,9601,960m A IDD2Q 1,3001,3001,3001,300m A IDD3P 1,6601,6601,6601,660m A IDD3N 2,6802,6802,6802,680m A IDD4R 4,4804,4804,4804,480m A IDD4W 4,5704,5704,5704,570m A IDD56,1006,1006,1006,100m A IDD6

Normal 760760760760m A Low power 680680680680m A Optional IDD7A

7,900

m A

Revison 1.0 December, 2003

Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in

simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

V Input/Output Capacitance (VDD=2.5V, VDDQ=2.5V, TA= 25?C, f=1MHz)

Parameter

Symbol M383(12)L6523BTS, M383(12)L2920BTS

Unit

Min Max Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,W E )CIN1911pF Input capacitance(CKE0)CIN2911pF Input capacitance( CS0)

CIN3911pF Input capacitance( CLK0, CLK0 )CIN41112pF Input capacitance(DM0~DM8)

CIN51011pF Data & DQS input/output capacitance(DQ0~DQ63)Cout11011pF Data input/output capacitance (CB0~CB7)

Cout2

pF Parameter

Symbol M383(12)L2923BTS, M383(12)L5628BT1(0)

Unit

Min Max Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )CIN1911pF Input capacitance(CKE0,CKE1)CIN2911pF Input capacitance( CS0, CS1)CIN3911pF Input capacitance( CLK0, CLK0 )CIN41112pF Input capacitance(DM0~DM8)

CIN51416pF Data & DQS input/output capacitance(DQ0~DQ63)Cout11416pF Data input/output capacitance (CB0~CB7)

Cout2

AC Operating Conditions

Parameter/Condition

Symbol Min Max

Unit Note Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC)VREF + 0.31

V 3Input Low (Logic 0) Voltage, DQ, DQS and DM signals.VIL(AC)VREF - 0.31V 3Input Differential Voltage, CK and CK inputs VID(AC)0.7VDDQ+0.6V 1Input Crossing Point Voltage, CK and CK inputs

VIX(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

Output Load Circuit (SSTL_2)

Output

Z0=50?C LOAD =30pF

REF

=0.5*V DDQ

R T =50?

V tt =0.5*V DDQ

AC Timming Parameters & Specifications

Parameter Symbol

(DDR266@CL=2)

(DDR266@CL=2.5)

(DDR200@CL=2)Unit Note Min Max Min Max Min Max Min Max

Row cycle time tRC60656570ns Refresh row cycle time tRFC75757580ns Row active time tRAS45120K45120K45120K48120K ns RAS to CAS delay tRCD15202020ns Row precharge time tRP15202020ns Row active to Row active delay tRRD15151515ns Write recovery time tWR15151515ns Last data in to Read command tWTR1111tCK Col. address to Col. address delay tCCD1111tCK

Clock cycle time CL=2.0

tCK

7.5127.51210121012ns CL=2.57.5127.5127.512ns

Clock high level width tCH0.450.550.450.550.450.550.450.55tCK

Clock low level width tCL0.450.550.450.550.450.550.450.55tCK

DQS-out access time from CK/CK tDQSCK-0.75+0.75-0.75+0.75-0.75+0.75-0.8+0.8ns

Output data access time from CK/CK tAC-0.75+0.75-0.75+0.75-0.75+0.75-0.8+0.8ns

Data strobe edge to ouput data edge tDQSQ-0.5-0.5-0.5-0.6ns12 Read Preamble tRPRE0.9 1.10.9 1.10.9 1.10.9 1.1tCK

Read Postamble tRPST0.40.60.40.60.40.60.40.6tCK

CK to valid DQS-in tDQSS0.75 1.250.75 1.250.75 1.250.75 1.25tCK

DQS-in setup time tWPRES0000ns3 DQS-in hold time tWPRE0.250.250.250.25tCK

DQS falling edge to CK rising-setup time tDSS0.20.20.20.2tCK

DQS falling edge from CK rising-hold time tDSH0.20.20.20.2tCK

DQS-in high level width tDQSH0.35 0.35 0.35 0.35 tCK

DQS-in low level width tDQSL0.35 0.35 0.35 0.35 tCK

DQS-in cycle time tDSC0.9 1.10.9 1.10.9 1.10.9 1.1tCK Address and Control Input setup time(fast)tIS0.90.90.9 1.1ns i,5.7~9 Address and Control Input hold time(fast)tIH0.90.90.9 1.1ns i,5.7~9 Address and Control Input setup time(slow)tIS 1.0 1.0 1.0 1.1ns i, 6~9 Address and Control Input hold time(slow)tIH 1.0 1.0 1.0 1.1ns i, 6~9 Data-out high impedence time from CK/CK tHZ-0.75 +0.75-0.75 +0.75-0.75 +0.75 -0.8 +0.8ns1 Data-out low impedence time from CK/CK tLZ-0.75 +0.75-0.75 +0.75-0.75 +0.75 -0.8 +0.8ns1 Input Slew Rate(for input only pins)tSL(I)0.50.50.50.5V/ns

Input Slew Rate(for I/O pins)tSL(IO)0.50.50.50.5V/ns

Output Slew Rate(x4,x8)tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5V/ns

Output Slew Rate Matching Ratio(rise to fall)tSLMR

0.67 1.50.67 1.50.67 1.50.67 1.5

Revison 1.0 December, 2003

Parameter

Symbol

(DDR266@CL=2)A 2

(DDR266@CL=2)B 0

(DDR266@CL=2.5)A 0

(DDR200@CL=2)Unit

Note

Min

Max Min

Max

Mode register set cycle time tMRD 15151516ns DQ & DM setup time to DQS tDS 0.50.50.50.6ns j, k DQ & DM hold time to DQS tDH 0.50.50.50.6ns j, k Control & Address input pulse width tIPW 2.2 2.2 2.2 2.5ns 8DQ & DM input pulse width tDIPW 1.75 1.75 1.752ns 8

Power down exit time

tPDEX 7.57.57.510ns Exit self refresh to non-Read command tXSNR 75757580ns Exit self refresh to read command tXSRD 200

200

tCK

Refresh interval time tREFI 7.8

7.8

7.8us 4Output DQS valid window tQH tHP -tQHS -tHP -tQHS -tHP -tQHS -tHP -tQHS -ns 11Clock half period tHP tCLmin or tCHmin

-tCLmin or tCHmin

-ns 10, 11Data hold skew factor tQHS 0.75

0.75

0.8ns 11DQS write postamble time tWPST 0.40.6

0.40.6

tCK

Active to Read with Auto precharge command

tRAP 20202020Autoprecharge write recovery + Precharge time

tDAL

(tWR/tCK)

+tCK 13

System Characteristics for DDR SDRAM

The following specification parameters are required in systems using DDR266 & DDR200 devices to ensure proper sys-tem performance. these characteristics are for system simulation purposes and are guaranteed by design.

Table 1 : Input Slew Rate for DQ, DQS, and DM

Table 2 : Input Setup & Hold Time Derating for Slew Rate

Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate

AC CHARACTERISTICS

DDR266DDR200PARAMETER

SYMBOL MIN MAX MIN MAX Units Notes DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC)

DCSLEW

TBD

0.5

4.0

V/ns

a, m

Input Slew Rate

tIS tIH Units Notes 0.5 V/ns 00ps i 0.4 V/ns +500ps i 0.3 V/ns

+100

Input Slew Rate

tDS tDH Units Notes 0.5 V/ns 00ps k 0.4 V/ns +75+75ps k 0.3 V/ns

+150

Revison 1.0 December, 2003

Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)

Table 6 : Output Slew Rate Characteristice (X16 Devices only)

Table 7 : Output Slew Rate Matching Ratio Characteristics

Delta Slew Rate tDS tDH Units Notes +/- 0.0 V/ns 00ps j +/- 0.25 V/ns +50+50ps j +/- 0.5 V/ns

+100

Slew Rate Characteristic

Typical Range

(V/ns)Minimum (V/ns)Maximum (V/ns)

Notes Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5a,c,d,f,g,h Pulldown slew

1.2 ~

2.5

1.0

4.5

b,c,d,f,g,h

Slew Rate Characteristic

Typical Range

(V/ns)Minimum (V/ns)Maximum (V/ns)

Notes Pullup Slew Rate 1.2 ~ 2.50.7 5.0a,c,d,f,g,h Pulldown slew

1.2 ~

2.5

0.7

5.0

b,c,d,f,g,h

AC CHARACTERISTICS

DDR266DDR200PARAMETER

MIN MAX MIN MAX NOTES Output Slew Rate Matching Ratio (Pullup to Pulldown)

TBD

0.67

1.5

e,m

System Notes :

a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.

Test point

Output

50?

VSSQ

Figure 1 : Pullup slew rate test load

b. Pulldown slew rate is measured under the test conditions shown in Figure 2.

VDDQ

50?

Output

Test point

Figure 2 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output

switching.

Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions

Typical : 25 ?C (T Ambient), VDDQ = 2.5V, typical process

Minimum : 70 ?C (T Ambient), VDDQ = 2.3V, slow - slow process

Maximum : 0 ?C (T Ambient), VDDQ = 2.7V, fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process v ariation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divices only.

h. Only intended for operation up to 266 Mbps per pin.

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns

as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or

VIH(DC) to VIL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Table s 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter

mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.

m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tra nsi

tions through the DC region must be monotony.

Revison 1.0 December, 2003

Command Truth Table (V=Valid, X=Don?t Care, H=Logic High, L=Logic Low)

COMMAND CKEn-1CKEn CS RAS CAS WE BA0,1A10/AP A0 ~ A9

A11, A12

Note

Refresh Auto Refresh

L L L H X

Self

Refresh

Entry L3

Exit L H

L H H H

H X X X3

Bank Active & Row Addr.H X L L H H V Row Address

(A0~A9, A11,A12)

Read &

Column Address Auto Precharge Disable

H X L H L H V

Column

Address

4 Auto Precharge Enable H4

Write &

Column Address Auto Precharge Disable

H X L H L L V

Column

Address

4 Auto Precharge Enable H4, 6

Burst Stop H X L H H L X7

Precharge Bank Selection

H X L L H L

V L

All Banks X H5

Active Power Down Entry H L

H X X X

L V V V

Exit L H X X X X

Precharge Power Down Mode Entry H L

H X X X

L H H H

Exit L H

H X X X

L V V V

DM H X X8

No operation (NOP) : Not defined H X H X X X

9 L H H H9

Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t RP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Revison 1.0 December, 2003

Physical Dimensions : 64M x 72 (M383L6523BTS)

Physical Dimensions: 128Mx72 (M383L2923BTS), 128Mx72 (M383L2920BTS)

Physical Dimensions: st.256Mx72 (M383L5628BT1)