A Provably Passive and Cost-Efficient Model for Inductive Interconnects

A Provably Passive and Cost-Efficient Model for Inductive Interconnects
A Provably Passive and Cost-Efficient Model for Inductive Interconnects

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A Provably Passive and Cost-Ef?cient Model for

Inductive Interconnects

Hao Yu and Lei He

Abstract—To reduce the model complexity for inductive interconnects,the vector potential equivalent circuit (VPEC)model was introduced recently and a localized VPEC model was developed based on geometry integration.In this paper,the authors show that the localized VPEC model is not accurate for interconnects with nontrivial sizes.They derive an accurate VPEC model by inverting the inductance matrix under the partial element equivalent circuit (PEEC)model and prove that the effec-tive resistance matrix under the resulting full VPEC model is passive and strictly diagonal dominant.This diagonal dominance enables truncating small-valued off-diagonal elements to obtain a sparsi?ed VPEC model named truncated VPEC (tVPEC)model with guaranteed passivity.To avoid inverting the entire inductance matrix,the authors further present another sparsi?ed VPEC model with preserved passivity,the windowed VPEC (wVPEC)model,based on inverting a number of inductance sub-matrices.Both full and sparsi?ed VPEC models are SPICE compatible.Experiments show that the full VPEC model is as accurate as the full PEEC model but consumes less simulation time than the full PEEC model does.Moreover,the sparsi?ed VPEC model is orders of magnitude

(1000)faster and produces a waveform with small errors (3%)compared to the full PEEC model,and wVPEC uses less (up to

90)model building time yet is more accurate compared to the tVPEC model.

Index Terms—Circuit simulation,inductance sparsi?cation,interconnect modeling.

I.I NTRODUCTION

As very large scale integration (VLSI)technology advances with de-creasing feature size as well as increasing operating frequency,induc-tive effects of on-chip interconnects become increasingly signi?cant in terms of delay variations,degradation of signal integrity,and aggrava-tion of signal crosstalk [1],[2].Since inductance is de?ned with re-spect to the closed current loop,the loop–inductance extraction needs to simultaneously specify both the signal net current and its returned current.To avoid the dif?culty of determining the path of the returned current,the partial element equivalent circuit (PEEC)model [3]can be

Manuscript received March 7,2003;revised June 3,2004.This paper is par-tially supported by the National Science Foundation (NSF)CAREER award CCR-0401682,SRC grant 1100,a UC MICRO grant sponsored by Analog De-vices,Fujitsu Laboratories of America,Intel,and LSI Logic,and a Faculty Partner Award by IBM.The authors used computers donated by Intel.This paper was recommended by Associate Editor C.-J.R.Shi.

The authors are with the Electrical Engineering Department,Univer-sity of California at Los Angeles,Los Angeles,CA 90095USA (e-mail:hy255@https://www.360docs.net/doc/8b19105106.html,;lhe@https://www.360docs.net/doc/8b19105106.html,).

Digital Object Identi?er 10.1109/TCAD.2005.850820

used,where each conductor forms a virtual loop with the in?nity and the partial inductance is extracted.

To accurately model inductive interconnects in the high frequency region,resistor–inductor–capacitor–mutual inductance (RLCM)net-works under the PEEC formulation are generated from discretized con-ductors by volume decomposition according to the skin depth and lon-gitudinal segmentation according to the wavelength at the maximum operating frequency.The extraction based on this approach [4]–[6]has high accuracy but typically results in a huge RLCM network with densely coupled partial inductance matrix L .A dense inductively cou-pled network sacri?ces the sparsity of the circuit matrix and slows down the circuit simulation or makes the simulation infeasible.Because the primary complexity is due to the dense inductive coupling,ef?cient yet accurate inductance sparsi?cation becomes a need for extraction and simulation of inductive interconnects in the high-speed circuit design.Because the partial inductance matrix in the PEEC model is not diag-onal dominant,simply truncating off-diagonal elements leads to neg-ative eigenvalues and the truncated matrix loses passivity [7].There are several inductance sparsi?cation methods proposed with guaran-teed passivity.The return-limited inductance model [8]assumes that the current for a signal wire returns from its nearest power/ground (P/G)wires.This model loses accuracy when the P/G grid is sparsely dis-tributed.The shift truncation model [9]calculates a sparse inductance matrix by assuming that the current returns from a shell with shell ra-dius r 0.But it is dif?cult to determine the shell radius to obtain the desired accuracy.Because the inverse of the inductance matrix called K element (susceptance)matrix is strictly diagonal dominant,off-di-agonal elements can be truncated without affecting the passivity [10],[11].Because K is a new circuit element not included in a conven-tional circuit simulator such as SPICE,new circuit analysis tools con-sidering K have been developed [12],[13].Alternatively,double-in-version-based approaches have been proposed in [11]and [14].Using the control volume to extract adjacently coupled effective resistances to model inductive effects,the vector potential equivalent circuit (VPEC)model is recently introduced [15].Its sparsi?ed and SPICE-compat-ible circuit model is obtained based on a locality assumption that the coupling under the VPEC model exists only between adjacent wire ?l-aments.

This paper presents an in-depth study on the VPEC model.The au-thors ?nd that the locality assumption in [15]does not hold in gen-eral and its integration-based extraction becomes impractical for large-sized interconnects as it requires to optimize the size of the control volume for each ?lament.The authors rigorously derive an accurate full VPEC model considering the coupling between any pair of ?laments by inverting the partial inductance matrix.The authors further prove that the resulting circuit matrix for the full VPEC model is passive and strictly diagonal dominant.The diagonal dominance enables truncating small-valued off-diagonal elements to obtain a sparsi?ed VPEC model named truncated VPEC (tVPEC)model with guaranteed passivity.To avoid inverting the entire inductance matrix,the authors also present another sparsi?ed VPEC model with preserved passivity,the windowed VPEC (wVPEC)model,by inverting a number of inductance subma-trices.Both full and sparsi?ed VPEC models are SPICE compatible.The rest of this paper is organized as follows.Section II introduces an accurate inversion-based VPEC model with detailed derivation in the Appendix.The resulting full VPEC model considers coupling between any pair of ?laments.In contrast,the VPEC model in [15]is integration based,localized but not accurate in general.In Section III,the authors

prove that the effective resistance matrix ^G

in the full VPEC model is passive and strictly diagonal dominant.Section IV presents a trunca-tion-based sparsi?cation that leverages the passivity of the ^G

matrix.It 0278-0070/$20.00?2005IEEE

TABLE I

T ABLE OF N

OTATIONS

truncates small-valued off-diagonal elements of the ^G

matrix obtained from the full inversion of the inductance matrix.In Section V ,the au-thors further present a more ef?cient sparsi?cation approach based on windowing.It avoids inverting the full inductance matrix and is more ef?cient and more accurate compared to the truncation-based sparsi?-cation.Section VI further presents the scalability of the runtime and model size for the sparsi?ed VPEC,full VPEC,and PEEC model.Fi-nally,Section VII concludes the paper.

II.I NVERSION -B ASED F ULL VPEC M ODEL

The VPEC model from [15]considering coupling only between ad-jacent ?laments can be called the localized VPEC model.In this sec-tion,the authors ?rst derive the system equation of the full VPEC to model the inductive effect between any pair of ?laments and then show that the localization assumption in [15]does not hold in general.They then introduce the inversion-based method to calculate the full VPEC model.Finally,experiments are presented to show that the full VPEC is as accurate as the PEEC model.A.Full VPEC

Same as in FastHenry [5]with the magneto-quasi-static assumption,the conductor can be divided into a number of rectilinear ?laments.The current density is constant over the cross section of the ?lament.In this paper,the authors use superscripts x;y;z to denote spatial components of a vector variable.Let A be the vector potential determined by the dis-tribution of the current density J .Then J k and A k are the components in the k direction (k =x;y;z ).The authors further use the subscript i for variables associated with ?lament a i (i 2N ),and every ?lament a i has a length l by adequately discretizing in the k direction.Table I summarizes the notations used in this paper with detailed de?nitions in the Appendix.

To extract the VPEC,the integration-based approach in [15]needs

to determine the localized ?ux B k

ij

(j 2n i ),where n i is the set of ?l-aments adjacent to a i .The explicit calculation of B k

ij

is hard,and only considering the localized ?ux as in [15]loses the accuracy.The integra-tion-based VPEC model in [15]needs to use a control volume for each ?lament,but no method was presented in [15]to ?nd an accurate con-trol volume.To avoid explicitly calculating B k

ij

and using the locality assumption,the authors derive a full VPEC model and then present an inversion-based extraction in Section II-B.The detailed derivation of the full VPEC model is presented in the Appendix,where the authors obtain two Kirchhoff’s current law (KCL)and Kirchhoff’s current law (KVL)equations

A k i ^R k i 0

+j =i;i;j 2N

A k i 0A k

j ^R k ij =^I k i (1)@A k i @t

=^V k i (2)

where the vector potential current and voltage are related to the elec-trical branch current and voltage by

^I

k i =lI k i and

^V

k i =V k

i l

:(3)

Clearly,we can see the physical meaning of the effective resistance by

(1):given a unit current change at the i th ?lament,the vector potential

observed at the j th ?lament is exactly ^R

k ij when all other ?laments are connected to vector potential ground.Furthermore,(2)describes the relation between the vector potential and its corresponding electrical voltage drop caused by the inductive effect.

The authors present a SPICE-compatible VPEC model for three ?l-aments in Fig.1.The model consists of two blocks:the electrical cir-cuit (PEEC resistance and capacitance)and the magnetic circuit (VPEC effective resistance and unit inductance).They are connected by con-trolled sources.It includes the following components.

1)The resistance R i and capacitance C i in the electrical circuit are

the same as those in the PEEC model.

2)A dummy voltage source to the sense current I k

i in the electrical

circuit controls ^I k i in the magnetic circuit [see (32)in the Ap-pendix].

3)A voltage-controlled current source is used to relate ^V

k i and ^I k i with gain g =1in the magnetic circuit.

4)A voltage source V k i in the electrical circuit is controlled by ^V

k i in the magnetic circuit [see (34)in the Appendix].

5)Effective resistances including ground ^R k i 0and coupling ^R k ij

[see (30)and (29)in the Appendix]are used to represent the strength of inductances in the magnetic circuit.

6)A unit inductance L i in the magnetic circuit a)takes into account

the time derivative of A k i [see (2)]and b)preserves the magnetic energy from the electrical circuit.

Although the number of magnetic circuit blocks increases with more ?laments,sparsi?ed VPEC models will be introduced in Sections III–V to greatly reduce coupling resistances in magnetic circuit blocks with preserved passivity.Moreover,because the VPEC model largely re-duces reactive elements (i.e.,inductance)and its effective resistance is less densely stamped in the modi?ed nodal analysis (MNA)ma-trix compared to the partial inductance under the PEEC model,the full VPEC model reduces the simulation time compared to the PEEC model (see experiments in Section VI).

Note that the summation in KCL (1)for the full VPEC model is carried out over each pair of ?laments.In contrast,this summation in [15]is carried out only for adjacent ?laments.Pacelli [15]obtained the

localized model by modeling the ?ux B k

ij

as a “current”?ow through ^R

k ij .It is based on the analogy with the conducting current ?ow at a surface S (Ohm’s law)

I =0

S

r 1d S :(4)

Equation (4)means that the conducting current I (x;y;z )is locally re-lated to the ?ux of the electrical ?eld E (x;y;z )(0r )on the surface S .Equation (4)is correct because electrons only locally transport in the

conductor.However,for the magnetic coupling problem,the ?ux B k

ij is caused by the magnetic ?eld that is not localized.Therefore,the au-thors still need nonlocal resistances to accurately model the long-range effect of inductance.Hence,the KCL (1)in this paper is related to not

only the localized ^R

k ij (j 2n i )but also all other ^R k ij (j =i ,j 2N ).The experimental results below will show that compared to the PEEC model,the full VPEC model considering all ?laments is accurate,but not the localized VPEC model from [15].

Fig.1.VPEC model for three?laments.

B.VPEC via PEEC Inversion

Due to the dif?culty of explicitly determining B k ij,there is no

ef?cient calculation method for effective resistances in[15].In this

part,the authors will derive the circuit-level system equation based on

the VPEC effective resistance matrix^G and then present an ef?cient method to calculate effective resistances from the inversion of the

partial inductance matrix.

The authors take the time derivative at both sides of(1)and then use

(2)to replace the time derivative of the vector potential.Consequently,

the authors

obtain

1 ^R k i0

+

j=i

1

^R k

ij

V k i

+

j=

i

01^

R k

ij

V k j=l2@I

k

i

@t

:(5)

The authors de?ne the circuit matrix^G of the VPEC model as

^G k ij =01^

R k ij

;^G k ii

=1^

R k i0

+

j=i

1

^R k

ij

:(6)

Then,the system equations can be rewritten as

^G k ii V k i

+

j=i

^G k

ij

V k j=l2@I

k

i

@t

:(7)

Compared to the system equation based on the inductance matrix L k and its inverse S k=(L k)01

L k ii@I k i

@t

+

j=i

L k ij

@I k j

@t

=V k i

S k ii V k i

+

j=i

S k ij V k j=@I

k

i

@t

:(8)

The authors?nd that^G k and S k only differ by a geometrical factor l2

^G k=l2S k:(9)Therefore,starting with the L matrix under the PEEC model,the au-thors?rst obtain the inverse of L and then have^R under the VPEC model the extraction formula

^R k

ij

=01

l S k ij

;^R k i0=1

l S k ii

+j=i l S k ij

:(10)

Because the major computation effort is the inversion of the L matrix, the authors call this method as an inversion-based VPEC model,where effective resistances are obtained from a unique relation(10).This in-version-based VPEC model leverages the existing PEEC extractor.In contrast,the localized VPEC model is integration based and needs to explicitly calculate the local?ux B k ij(j2n i)from scratch,where its accuracy is sensitive to the size of the control volume during the inte-gration[15].Therefore,it has a high accuracy only for a few number of?laments and needs to optimize the size of the control volume for each?lament when system has a large number of?laments.Clearly,it becomes impractical for the full-chip extraction.

Note that the above(7)–(10)can be used to derive the K element (susceptance)based model in[10]and[11]from?rst principles.Al-though the K element method and VPEC are both derived from the inverse of L,the VPEC model is realized quite differently from the K element:1)the VPEC model is SPICE compatible but the K element needs to introduce the new circuit element to the simulator;and2)the current K element simulator is based on nodal analysis[13],where the admittance form of the K element is0=A l L01A T l=s(A l is the inci-dent matrix for the inductance)in the frequency domain.Clearly,the0 matrix becomes inde?nite when s!0.Therefore,it will lose correct dc information.On the other hand,the VPEC model can be stamped in the MNA matrix with the correct dc information in both frequency and time-domain simulations[16],which enables the correct circuit reduc-tion[17]to further reduce the model order.

C.Accuracy Comparisons

In this part,the authors use the aligned parallel bus to compare the PEEC model with the full VPEC model and localized VPEC model.

1)PEEC Model Extraction:The experiment setting is illustrated as follows.The authors assume the copper conductor( =1:72

Fig.2.For a5-bit bus,(a)a1-V step voltage with10ps of rising time and(b)a1-V ac voltage are applied to the?rst bit and all other bits are quiet.The responses of the PEEC model,full VPEC model,and localized VPEC model are measured at the far end of the second bit.

1008 m)and low-k( =2)dielectric.The conductor is volume dis-cretized according to skin depth and longitudinal segmented by one-

tenth of the wavelength.Capacitance is extracted by a lookup table

[18]interpolated from FastCap[4].Because capacitive coupling is a

short-range effect,only adjacent couplings are considered.Partial in-

ductance is extracted by FastHenry[5]at10GHz(as the maximum

operating frequency),where each wire segment is modeled by one?la-

ment,and coupling between any pair of segments(including segments

in a same line)is considered.The authors then generate the distributed type RLCM circuit under the PEEC model.Furthermore,intercon-nect drivers and receivers are modeled by the resistance R d=120 and the loading capacitance C L=10fF.All circuit models are sim-ulated by HSPICE on a SUN Ultra-5workstation.Note that the same

experiment setting is applied for all other experiments in this paper un-

less speci?ed otherwise.

2)Simulation of Aligned Parallel Bus:A5-bit bus with one seg-

ment per line is considered.Each bus line is1000 m long,1 m wide,

and1 m thick.The space between lines is2 m.With the extracted

RLCM parameters under the PEEC model,the authors further construct

the full VPEC model(with coupling^R ij between all bits)from this paper and the localized VPEC model(with coupling^R ij between ad-jacent bits)from[15].They measured responses at the far-end of all ?ve bits and compared waveforms of the second bit in Fig.2(a)and(b) for both time-domain and frequency-domain simulations,where a1-V step voltage with10ps of rising time is used for time-domain transient simulation and a1-V ac voltage for the frequency-domain(1Hz to10 GHz)simulation.Clearly,the full VPEC model and the PEEC model obtain identical waveforms in both frequency-and time-domain simu-lations,but the localized VPEC model introduces nonnegligible error and is not accurate compared to the PEEC model,where the time-do-main response shows15%waveform difference and the frequency-do-main response shows a large deviation beyond5GHz.

Note that when the number of conductors is small,there is no sim-ulation speedup observed.However,for larger sized interconnect ex-amples in Sections IV–VI,the simulation time of the full VPEC model (without sparsi?cation)is less than that for the PEEC model.The de-tailed analysis of complexity scaling can be found in Section VI.Fur-thermore,in the comparison,the authors did not use the implementa-tion of the localized model from[15],which depends on the height of the integration box(i.e.,the size of the controlled volume)and is an approximated solution without a method to?nd the accurate size of the controlled volume.Instead,the authors?nd an accurate full VPEC model and then only keep the adjacently coupled resistances to obtain an accurate localized VPEC model.1

III.I NDUCTANCE S PARSIFICATION U NDER THE VPEC M ODEL This section?rst derives the magnetic energy under the VPEC model and then proves that the circuit matrix^G under the VPEC model is

positive de?nite.Moreover,the authors prove that^G is also strictly di-agonal dominant.This property enables the passivity preserved matrix sparsi?cation methods.Finally,the authors present the sparsi?cation ?ow for the VPEC model.

A.Magnetic Energy in VPEC Model

Generally,the magnetic energy is given by the space integral[19]

u m=1

2

A1J d

=

k=x;y;z

u k m:(11)

1Based on the communication with[15],the localized VPEC model used in this paper has a similar accuracy compared to the one used in[15].

For the full VPEC model,(11)can be rewritten to

u k m=1

2

A k J k d

=1

2

i

A k i lI k i

=1

2

i

A k i^I k i:(12)

Furthermore,when the KCL(31)is rewritten in terms of the^G

matrix

j

G k ij A k i=^I k i(13)

the authors have for the magnetic energy under the full VPEC model the relation

u k m=1

2

i;j

G k ij A k i A k j:(14) It is proven below that the^G matrix is positive de?nite.

B.Property of the^G Matrix

Theorem1:The circuit matrix^G k(k=x;y;z)in the VPEC model is positive de?nite.

Because^G only differs from the K matrix by a positive geometric constant,the proof of the matrix property(passivity and strict diag-onal dominance)for K is equivalent for^G.The existing proofs in[10] and[13]are based on the analogy[L]= [C01],which holds when [C][L]=constant.However,this relation does not hold in general as shown in[20].Below,the authors present a direct proof for the VPEC model.

Proof:According to(14),because the energy u k m(k=x;y;z) is positive,it automatically results in a positive de?nite matrix^G k[21]. Therefore,the corresponding VPEC model is passive.However,to further guarantee a passive model after truncating small-valued off-diagonal elements from the original positive de?nite matrix,the authors will prove that the matrix^G is strictly diagonal dominant[21],i.e.,

^G k ii

>j j^G k ij j.

Lemma1:All the effective resistances^R k i0and^R k ij(k=x;y;z) in the VPEC model are positive.

Proof:The authors present the proof based on the KCL(1).Since effective resistances are only determined by the geometry of the?la-ments,it will not depend on the applied external sources.Without loss of generality,the authors assume that an impulse current I k i is applied at?lament a i along the z direction and all other?laments a j are con-nected to the vector potential ground.Note that for the?lament a i, its average vector potential A k i is in the same direction of I k i;for any other grounded?lament a j,its average vector potential A k j is zero,but its induced current0I k j is in the opposite direction to I k i according to Lenz’s law.Hence,for?lament a j,(31)becomes

A k j0A k i

^R k

ij =0A

k

i

^R k

ij

=0lI k j

where the induced current I k j is determined by the coupling?ux be-tween a i and a j.Equation(1)can be further rewritten to

^R k ij =A

k

i

lI k j

>0:(15)

The positiveness of the ground resistance^R k i0can be easily proved in

a similar fashion.With this lemma,the authors can further prove the

following theorem.

Theorem2:The circuit matrix^G k(k=x;y;z)in the VPEC model

is strictly diagonal dominant.

Proof:According to

(6)

j=i

^G k

ij

=

j=i

1

^R k

ij

(16)

and

j=i

^G k

ij

<1^

R k i0

+

N

j=i

1

^R k

ij

=^G k ii

or

^G k

ii

>

j=i

^G k

ij

:(17)

That is,the circuit matrix^G is strictly diagonal dominant.Note that

truncating small off-diagonal entries from a strictly diagonal dominant

matrix still leads to a positive de?nite matrix,i.e.,a passive circuit

model[21].Based on Theorem2,such a truncation-based sparsi?ca-

tion still leads to passive circuit models.Intuitively,truncating small

off-diagonal entries in the^G matrix(equivalent to truncating larger

off-diagonal entries in^R matrix)results in ignoring larger resistors in

the equivalent resistance network.Because larger resistors are less sen-

sitive to and also contribute less to current change,the resulting spar-

si?ed model can still have a good waveform accuracy as presented in

Section IV.Moreover,the proof assumes that wires can be decomposed

into short wires with similar length.Therefore,in the experiments,the

authors always segment wires to one-tenth of the maximum operating

frequency when wire lengths are different(see spiral inductor in Sec-

tion V).

C.VPEC-Based Inductance Sparsi?cation

With Theorem2,the authors present the?ow below for the induc-

tance sparsi?cation based on the VPEC model.

?Generate the partial inductance matrix L by FastHenry or the

formula from[22]and[23].

?(Option1:tVPEC model)Invert the full L matrix to obtain matrix

^G,^R,and full VPEC model,and then generate the sparsi?ed

VPEC model by truncating the full VPEC model.

?(Option2:wVPEC model)Find a sparse approximated inverse

matrix S0of L to obtain^G0,^R0,and the sparsi?ed VPEC model

simultaneously.

Note that during the inductance extraction at low frequency,the au-

thors assume that each wire segment is modeled by one?lament.When

the frequency is beyond10GHz,the volume?lament[5]or conduc-

tion mode[24]based decomposition can be applied to consider the skin

and proximity effects.In this paper,the authors use the three-dimen-

sional(3-D)frequency-dependent solver FastHenry[5]to accurately

extract the partial inductance matrix.Because inductance has weak de-

pendence on geometry,the formula-based[23]or lookup table-based

[25]approaches can also be applied to ef?ciently obtain the full-chip

inductance.

As further discussed in Sections VI and V,the authors will apply two

sparsi?cations that depend on the scale of the interconnect:1)when

the scale of interconnect is small(less than1000wires),the direct

LU or Cholesky factorization-based inversion is suf?ciently ef?cient

TABLE II

S ETTINGS AND R ESULTS OF G EOMETRICAL tVPEC M

ODELS

[O (N 3)],and the authors can apply simple truncation-based sparsi?-cations;2)when the scale of interconnect is large,the authors extend a window-based extraction [11]to obtain a sparse approximated inverse of L and simultaneously extract a sparsi?ed VPEC model.It reduces the computation expense to O (Nb 3),where b is the size of the window.As shown by experiments,the wVPEC model also reduces the error in-troduced by the sparsi?cation when compared to the tVPEC model.

IV .tVPEC M ODEL

This section presents the tVPEC model.After the full inversion of

L ,the authors obtain a strictly diagonal dominant matrix ^G

.As ex-plained in Section III,its small-valued off-diagonal elements can be truncated without loss of passivity.The authors present two truncating approaches below:the geometrical VPEC (gtVPEC)and numerical VPEC (ntVPEC)truncations.The ?rst one is applicable to the aligned parallel bus,and the second is applicable to conductors of any shapes.A.Geometrical Truncation

For the aligned parallel bus,the authors can de?ne a truncating window (N W ,N L )for each wire segment,where N W and N L are the numbers of coupled segments in the directions of wire width and length,respectively.The coupling along the wire length is the forward coupling,and the one along the wire width is the aligned coupling.Because of the symmetry introduced by aligning and paralleling,each wire segment will have the same sized truncating window.As a result,

the tVPEC model only contains ^R

ij within the truncating window for each wire segment and is called gtVPEC in Table II.

The authors consider a 32-bit bus with eight segments per line and four differently sized truncating windows,(32,8),(32,2),(16,2),and (8,2),and summarize the experiment setting and result in Table II.Clearly,there is a smooth tradeoff between runtime and accuracy for different truncating window sizes,where the average voltage differ-ences and associated standard deviations are calculated for all time steps in SPICE simulation.The authors ?rst compare results of dif-ferent truncating windows.The truncating window (8,2)achieves the highest speedup of 302and the largest difference of about 0.2mV on average,less than 2%of the noise peak,and the truncating window (32,2)has the highest accuracy with 0.06mV on average but a reduced speedup of 102.Furthermore,the small difference between windows (32,8)and (32,2)implies that the forward couplings between nonad-jacent segments are negligible.However,an N W larger than N L (as shown in Table II)is needed to achieve a high accuracy.This implies that the aligned coupling is stronger than the forward coupling and con-sidering only the adjacent aligned coupling may lead to a large error.B.Numerical Truncation

For numerical truncation,the authors de?ne the coupling strength as the ratio of an off-diagonal element to its correspondent diagonal ele-ment at each row of ^G

.They then truncate those off-diagonal elements with coupling strength smaller than a speci?ed threshold.

Fig.3plots simulation results under the numerical sparsi?cation for the nonaligned parallel bus with 128bits and one segment per line.The

sparse factor is the ratio between the numbers of circuit elements in the truncated and full VPEC models.The waveform difference is small in terms of the noise peak for sparse factors up to 30.5%.Table III sum-marizes the truncation setting and simulation result,where values in parentheses of column 1are truncating thresholds,and the runtime in-cludes both SPICE simulation and matrix inversion in case of VPEC models.One can see from the table that up to 302speedup is achieved when the average waveform differences is up to 0.377mV ,less than 1%of the noise peak.A larger speedup factor can be expected as a higher waveform difference can be tolerated in practice.The authors also com-pare the full VPEC model and the PEEC model.The full VPEC simu-lation is 7times faster and has a negligible waveform difference.

V .wVPEC M ODEL

The sparsi?cation in Section IV needs full matrix inversion and be-comes computationally expensive for the large-sized interconnect.Fur-thermore,the directly truncated matrix ^G

may be not accurate enough to represent the original full ^G

matrix.As shown in [11],all entries of the L inverse matrix can be approximately reconstructed from entries of the submatrices in L corresponding to the coupling window of the active https://www.360docs.net/doc/8b19105106.html,ing this windowing technique,the authors further present two wVPEC models based on the geometry (gwVPEC)and nu-merical value (nwVPEC),respectively.A.Geometrical Windowing

Owing to the regularity of the aligned parallel bus,a coupling window with uniform size b for each wire can also be de?ned.For each wire in turn as the aggressor,the authors ?rst construct N small submatrices (coupling windows)all with size b ,then invert each sub-matrix and build a sparse approximated inverse for L .It is described in details in the following two steps.

1)Submatrix Construction:For aggressor m and all its victims within a window of size b ,the authors construct a submatrix L (m )as

L (m )

ij

=

L ij ;if (i,j)inside the window 0;if (i,j)outside the window.

The authors then solve vector s (m )from L (m )s (m )=i (m ),where i (m )is the unit vector,correspondent to applying a unit current source

at the m th aggressor,i.e.,i (m )

n = mn .With further iterating the above procedure for all conductors in turn as the active aggressor,the authors obtain N dimension-reduced vectors s (m ).Because this process is only related to the submatrix,the complexity of full inversion is reduced from O (N 3)to O (Nb 3)when b is small.

2)Heuristic Selection:The authors then merge all s m vectors into one complete and sparse matrix S 0that can approximate L 01,the in-verse of inductance matrix.The entry of S 0is

S 0mn =S 0nm =

max s (m )n ;s (n )

m

(18)

where s (m )

n is the element between the m th aggressor and its n th victim

inside the coupling window.Note that s (m )

n is always negative with suf-?cient discretizations [13].The circuit matrix of a stable system needs

Fig.3.For a 128-bit bus by numerical truncation,a 1-V step voltage with 10ps of rising time is applied to the ?rst bit and all other bits are quiet.The responses of the PEEC model,the full VPEC model,and the tVPEC model are measured at the far end of the second bit.

TABLE III

S ETTINGS AND R ESULTS OF N UMERICAL tVPEC M ODELS

to be symmetric positive de?nite (s.p.d.).This is guaranteed by the

heuristic in (18).That is,the authors always have

S 0mm

n =m

S 0

mn :

(19)

As a result,the authors can construct the sparsi?ed yet passive VPEC

model based on (10)with the sparse approximated inverse S 0.

The authors ?rst compare the extraction ef?ciency of geometrical tVPEC and wVPEC models in Fig.4by extracting the VPEC model for buses up to 2000bits.The size for geometrical truncation is (N W ;N L )=(8;1)and for the geometrical wVPEC is b =8.The extraction time for a truncation-based method includes the full inver-sion and truncation.When the scale of interconnects is small (below 128bits),the truncation-based method is actually as ef?cient as the window-based method.But when the scale of interconnects becomes larger,the window-based extraction is faster than the truncation-based approach with a 902speedup for the 2048-bit bus (8.6s versus 543.1

Fig.4.Extraction time comparisons of bus lines with one segment each line using geometrical tVPEC and wVPEC models.

Fig.5.For a 128-bit bus by geometrical windowing,a 1-V step voltage with 10ps of rising time is applied to the ?rst bit and all other bits are quiet.The responses of the PEEC model,full VPEC model,gtVPEC model,and gwVPEC model are measured at the far end of the second and 64th bits,respectively.

TABLE IV

W A VEFORM A CCURACY C OMPARISONS OF gtVPEC AND gwVPEC M

ODELS

s).Therefore,it is more ef?cient to apply the winnowed VPEC model for large-scale interconnects.

The authors further compare the waveforms between gtVPEC and ntVPEC models for the 128-bit bus with one segment per line.The authors apply a pulse voltage at the ?rst bit and observe the transient responses at the far ends of second and 64th bit bus,respectively.The window size is b =32for the gwVPEC model and (N W ;N L )=(32;1)is set for the gtVPEC model to achieve the same sparsi?ca-tion ratio.Fig.5shows waveforms of the PEEC model,full VPEC model,gtVPEC model,and gwVPEC https://www.360docs.net/doc/8b19105106.html,pared to accurate models such as the PEEC model and full VPEC model,the gwVPEC and gtVPEC models have virtually no error at the second bit bus.But for the 64th bit,the gtVPEC model has nonnegligible error but the gwVPEC model still has a high accuracy.More accuracy comparisons are presented in Table IV by changing the window size b to 64,32,16,and 8,where the waveform difference is calculated from responses at far ends of the 64th bit between the sparsi?ed VPEC and PEEC models.The authors ?nd that the window-based extraction has 22higher ac-curacy than the truncation-based approach on average.It is due to the fact that the matrix element generated from windowing is interpolated with other elements in the inductance matrix.

B.Numerical Windowing

The coupling window usually has different sizes for different wires because the general layout does not have the regularity as the aligned parallel bus.Therefore,the authors ?rst need to determine the size of coupling window for each wire.Similar to the numerical truncation approach,the authors de?ne the coupling strength as the ratio of an off-diagonal element to its correspondent diagonal element at each row of the L matrix.The authors then construct the coupling window by only considering those off-diagonal elements that have coupling strength larger than a speci?ed threshold value.With the heuristic selection (18),the authors can build the sparse approximated inverse and consequently a sparsi?ed VPEC model.

In an example shown in Fig.6,the authors extract the partial induc-tance by FastHenry at 10GHz for a three-turn spiral inductor on the lossy substrate.The heavily doped substrate modeled as lossy ground plane with =1:021005 m .The metal is volume discretized ac-cording to skin depth and longitudinal segmented by one-tenth of the wavelength,resulting in 92segments.The substrate is also discretized according to [26],and its contribution (Eddy current loss)is lumped to the segmented conductor on top of the substrate.

Fig.6.Discretized spiral inductor on the lossy substrate for the generation of the distributed RLCM PEEC/VPEC model.

The authors construct the distributed RLCM PEEC model with5120 circuit elements and then apply the numerical window-based method by setting the threshold as1.5e-4.It results in a56.7%sparsi?cation ratio.To check the accuracy of the resulting model,the authors apply a1-V pulse voltage at input and observe the response at the output port.Fig.7shows the waveforms obtained by the PEEC model,full VPEC model,and nwVPEC model.The three waveforms are virtually identical to each other but the wVPEC model results in an82runtime speedup compared to the full PEEC model(9.3s versus70.5s).

VI.C OMPLEXITY S CALING OF VPEC M ODELS

The authors further compare runtimes and model size by extracting and simulating a number of aligned parallel buses using the PEEC model,full VPEC model,and gwVPEC model(b=8),respectively. The runtime for the full or wVPEC model includes both VPEC extrac-tion and SPICE simulation times.The model size refers to the?le size of the resulting SPICE netlists.The authors plot the runtime versus the bus size in Fig.8(a)and the model size versus the bus size in Fig.8(b). Due to the additional introduced circuit elements,the size of SPICE netlist for the full VPEC model is around10%larger than the full PEEC model on average.Further,when the scale of wire number is small, there is no runtime speedup observed for the full VPEC model.How-ever,when the scale of wire becomes larger(greater than64bits),the runtime of the full VPEC model is found to be10times faster than the PEEC model on average.For the256-bit bus,the full VPEC model is472(185.39s versus8726.85s)faster than the PEEC model.This is due to the fact that:1)its resultant network has fewer reactive ele-ments(i.e.inductances);and2)its resultant MNA matrix in SPICE is sparser than the direct inductance formulation.SPICE converges faster with fewer time derivatives and integrals,and its internal sparse solver is more ef?cient for a less dense matrix.

Moreover,both PEEC and full VPEC models can only handle a bus circuit with up to256bits due to memory limitations.On the other hand,the gwVPEC model(b=8)can handle a larger size of up to thousand bits.Moreover,it is easy to see that the scalability of the gwVPEC models shows a slow increase with respect to the increase of the bus line numbers.For example,it achieves over10002(9.71s versus8726.85s)speedup for a256-bit bus in runtime compared to the PEEC model.In all the simulation,the wVPEC model has a very small waveform difference(less than3%)in terms of delay when compared to the PEEC model.

VII.C ONCLUSION

Using the equivalent resistance network and controlled voltage and current sources to replace the inductance network,the authors develop the full VPEC model that is as accurate as the PEEC model but takes less simulation time.Although the full VPEC model has a slightly higher circuit complexity compared to the PEEC model,SPICE can handle the VPEC model more ef?ciently because the VPEC model has fewer reactive elements(i.e.,inductances)and the modi?ed nodal ad-mittance matrix becomes sparser under VPEC model than that under the PEEC model.

Moreover,the resulting circuit matrix^G for the equivalent resis-tance network in the full VPEC model is passive and strictly diagonal dominant.This enables truncation-based sparsi?cation methods with guaranteed passivity.The authors have presented the truncation-based method and have achieved orders of magnitude speedup in circuit simu-lation with small errors compared to the PEEC model.Furthermore,the window-based extraction method has been developed to avoid the full inductance matrix inversion and can obtain a higher accuracy compared to the truncation-based approach.The authors have also shown that the matrix^G can be used to justify the K element or susceptance-based simulation[10]–[14]from?rst principles.Note that SPICE is able to directly simulate the VPEC model but not the K element-based model. The primary contribution of this paper is to derive the inversion-based full VPEC model for multiple inductive interconnects and illus-trate how to build sparsi?ed VPEC for SPICE simulation with guaran-teed passivity.To further reduce the complexity of the resulting sparsi-?ed VPEC models,the authors intend to develop model order reduction for the VPEC model.

A PPENDIX

To model the inductive effect,the authors start with differential Maxwell equations in terms of A[19]

r2A k=0 J k(20)

@A k

@t

=0E k(21)

where the vector potential A is in the z direction same as the current density J,E is the electrical?eld,and is the permeability constant. Note that the resistive voltage drop by(0r k )is not included in(21) since the authors are interested in the inductive voltage drop here.Given the distribution of the current density J k,the vector potential A k is determined by

A k=

4

J k

j r0r0i j

d r0i:(22)

To construct the system equation in the form of the integral equation, the authors apply the volume and line integration to(20)and(21),re-spectively.For?lament a i,when(20)is integrated within the volume i of?lament a i,using Gauss’law

S

a1d S =

r1a d (23) the authors can obtain

J k d =

S

r A k1d S

=B k i0

+

j=i

B k ij:(24)

Fig.7.For a three-turn spiral inductor with92segments by the numerical windowing,a1-V step voltage with10ps of rising time is applied to the input port.

The responses of the PEEC model,full VPEC model,and nwVPEC model are measured at the output

port.

Fig.8.Runtime and memory usage comparisons of bus lines with one segment each line using the PEEC model,full VPEC model,and gwVPEC model(b= 8).

Note that the surface integral

S d S r A k is actually the?ux of the gra-

dient of k th component of the vector potential caused by the?lament current of a i in i.It consists of following parts[15]:1)the?ux to the in?nity(vector potential ground)B k i0

B k i0=

S r A k1d S(25)

and2)the?ux to all other?laments a j(j2N,j=i)B k ij

B k ij =

S

r A k1d S:(26)

However,to explicitly determine the value of B k ij is dif?cult because it

is hard to partition the?ux between?lament a i,all other?laments a j,

and the vector potential ground.

Moreover,integrating(21)along the projected length in the k direc-

tion of?lament a i leads to

l

@A k

@t

d l=0

l

E k1d l:(27)

Based on(24)and(27),the authors can further construct the cir-

cuit-level system equation in matrix form.By de?ning the?lament

vector potential[15]as the average volume integral of A k within i

(surrounded by the surface S i)

A k i=1

i

A k(r)d (r):(28)

The authors can de?ne an effective coupling resistance

^R k

ij

=0

A k i0A k j

B k ij(29)

Fig.9.(a)Electronic current-controlled vector potential current source.(b)Kirchhoff’s current law for the vector potential circuit.An invoking vector potential current source is employed at a i and the responding vector potential at a j A k j determined by the full effective resistance network.

to model(i.e.,replace)the mutual inductive coupling between a i and

a j.In addition,there also exists an effective ground resistance to model

the self-inductive effect

^R k i0=0 A

k

i

B k i0

:(30)

Because the?lament current is invariant along the k direction,the volume integral of the current density inside the volume i is reduced to lI k i,where I k i is the electrical current at the cross section of a i.There-fore,(24)becomes the KCL under the full VPEC model

A k i ^R k i0

+

j=i

A k i0A k j

^R k

ij

=lI k i(31)

where a vector potential current source^I k i can be de?ned as

^I k

i

=lI k i(32) that is controlled by the electrical current I k i.An equivalent circuit to illustrate the VPEC KCL(31)is shown in Fig.9.Clearly,we can see the physical meaning of the effective resistance:given a unit current change at the i th?lament,the vector potential observed at the j th?la-ment is exactly^R k ij when all other?laments are connected to the vector potential ground.

Similar for(27),the authors have the inductive nodal voltage equa-tion

l@A k i

@t

=V k i(33)

that describes the relation between the vector potential and its corre-sponding electrical voltage drop caused by the inductive effect.As a result,a voltage-controlled vector potential voltage source^V k i is

^V k i =V

k

i

l

:(34)

A CKNOWLEDGMENT

The authors thank the reviewers for insightful comments that im-proved the manuscript.

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Sequential Circuit ATPG Using Combinational Algorithms Xiaoming Yu and Miron Abramovici,Fellow,IEEE Abstract—In this paper,we introduce two design-for-testability(DFT) techniques based on clock partitioning and clock freezing to ease the test generation process for sequential circuits.In the?rst DFT technique,a cir-cuit is mapped into overlapping pipelines by selectively freezing different sets of registers so that all feedback loops are temporarily cut.An oppor-tunistic algorithm takes advantage of the pipeline structures and detects most faults using combinational techniques.This technique is feasible to circuits with no or only a few self-loops.

In the second DFT technique,we use selective clock freezing to tem-porarily cut only the global feedback loops.The resulting circuit,called a loopy pipe,may have any number of self-loops.We present a new clocking technique that generates clock waves to test the loopy pipe.Another oppor-tunistic algorithm is proposed for test generation for the loopy pipe.Exper-imental results show that the fault coverage obtained is signi?cantly higher and test generation time is one order of magnitude shorter for many cir-cuits compared to conventional sequential circuit test generators.The DFT techniques do not introduce any delay penalty into the data path,have small area overhead,allow for at-speed application of tests,and have low power consumption.

Index Terms—Automatic test pattern generation,clock freezing,clock partitioning,clock waves,design for testability,power consumption,se-quential circuit test generation.

I.I NTRODUCTION

Automatic test-pattern generation(ATPG)for sequential circuits has long been recognized as a dif?cult and time-consuming problem [1]–[3],so that ATPG algorithms working on complex circuits can spend many hours of CPU time and still obtain poor results in terms Manuscript received March2,2004;revised July1,2004.This paper is based on preliminary versions in the2001Latin American Test Workshop and the 39th Design Automation Conference2002.This paper was recommended by Associate Editor N.K.Jha.

X.Yu is with Intel Corporation,Hillsboro,OR97124USA(e-mail: xiaoming.yu@https://www.360docs.net/doc/8b19105106.html,).

M.Abramovici is with DAFCA Inc.,Framingham,MA01701USA(e-mail: miron.abramovici@https://www.360docs.net/doc/8b19105106.html,).

Digital Object Identi?er10.1109/TCAD.2005.850835of fault coverage.Among the factors contributing to the complexity

of this problem[3]are:1)the dif?culty in controlling and observing

deeply buried?ip-?ops(FFs);2)the need to work with a model

consisting of an iterative array of time-frames whose number is,in

the worst case,an exponential function(4n)of the number of FFs in the circuit(n);3)the existence of illegal states,which may cause the

ATPG algorithm to waste a lot of time trying to justify them;and4)the

existence of untestable faults,which require the ATPG algorithm to

complete an exhaustive search before they are identi?ed as untestable. Several different approaches have been proposed for sequential circuit test generation,including deterministic techniques,genetic techniques,symbolic techniques,and various combinations of the three[4]–[15].Deterministic algorithms tend to be highly complex and time consuming[4]–[6].As an example,the HITEC test generator [6]uses both forward and reverse time processing to generate a test for a target fault.During test generation,each target fault must be excited and the fault effects propagated to a primary output(PO), either in the same time-frame in which the fault is excited or in a subsequent time-frame.The required state must then be justi?ed.If con?icts are found,backtracking is required,and alternative decisions must be made.Genetic algorithm(GA)based approaches simplify test generation by processing in the forward direction only[8]–[12]. Populations of candidate test sequences are evolved over several generations,with more highly?t sequences propagating from one generation to the next.Fitness is determined based on fault detection capabilities,amount of circuit activity induced,and other factors related to detecting the target faults.GA-based techniques have been especially effective for data-dominant circuits.Symbolic techniques [7],[14]based on binary decision diagrams(BDDs)have also been used very effectively on control-dominant circuits.Very high fault coverages have been achieved,although the size of the circuit that can be handled is limited.

Various design-for-testability(DFT)techniques have also been proposed to ease the test generation process and improve the fault coverage for sequential circuits,including full scan design[16], [17],partial scan design[18]–[21],clock control[22],[23],and probe point insertion[24],[25].With full scan design,all?ip-?ops are arranged in a chain when a circuit is being tested,and node values at the?ip-?ops are scanned in before each test and scanned out after each https://www.360docs.net/doc/8b19105106.html,plete controllability and observability are thus provided at the?ip-?ops,reducing the complexity of the test generation process to that for a combinational circuit.In partial scan design,only a subset of?ip-?ops are placed in the scan chain. Partial scan design is a cost effective alternative;delay and area penalties are reduced,and test application time may be reduced as well.However,the remaining circuit is still sequential,so a sequential circuit test generator is needed.With clock control,?ip-?ops in a circuit are divided into groups,and each group is controlled by a single clock signal,thus reducing the correlation between?ip-?ops and increasing the number of reachable states.By using probe points, the observability of some internal lines,including the outputs of ?ip-?ops and any other lines,can be enhanced.

In this paper,we propose two DFT techniques based on clock partitioning and clock freezing,selective clock freezing and CLOCK-WAVE,to ease the test generation process for sequential circuits and two opportunistic ATPG algorithms that take advantage of the DFT techniques and detect most faults using combinational techniques [26],[27].With the selective clock freezing DFT technique,a circuit is mapped into various overlapping pipeline con?gurations by selectively freezing different sets of registers.An opportunistic algorithm,called PIPEXPRESS,is then used for test generation on different pipeline

0278-0070/$20.00?2005IEEE

创意绘画公开课

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公开课心得体会 -标准化文件发布号:(9556-EUATWK-MWUB-WUNN-INNUL-DDQTY-KII

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学校举行的公开课,讲课、评课结束了,通过这一次公开课,我有了很多的收获,从中又学到了很多的知识,我作为一名老教师,公开课对我来说又是一次提升的机会,这一次公开课,我能感悟许多。 说到公开课的真实,不能回避的是公开课与常规课的区别。由于公开课的特殊性,它比常规课更要求完美是必然的。一节好的公开课我认为应具备以下素质: 一是应该能够体现新课程理念,对新课程的推进具有引领和示范作用; 二是应该让学生有实实在在的认知收获和或多或少的生命感悟,应是一堂有效的课; 三是应该是真实的,能客观反映师生的真实水平和教学的实际情况,让人有真实感、亲近感、亲切感,可看、可学、可用; 四是应该具有研究的价值,公开课不仅要成为教师自我反思的对象,同时也要成为教师同行或专家共同讨论的领域,从而对促进教学改革和教师专业成长起到实质性的作用。 通过本次公开课,我感受到要上好一节课,如下环节不可忽视: 1.课前做好充分的准备老师要深入钻研授课内容,注重研究教材教法,注重把知识和能力既深入浅出又扎扎实实的传授给学生,注重研究教材教法,注重把知识和能力既深入浅出又扎扎实实的传授给学生。要充分做好课前准备工作。不同的文体、不同的内容,就会有不同的授课方法。在备课过程中,必须要考虑到学生对课文所描述的对象熟不熟悉,能否理解课文的内容。我们在课堂上怎样做才能使学生有所收获。这些都需任课老师在课前仔细琢磨,做好设计。只有这样,才有可能上好每一节课。 2.在讲课前,要懂得如何引发学生的兴趣,如何激起学生的热情。学生的情绪高涨起来,整节课的气氛就会很活跃,他们的注意力就会集中在课堂中,思维活跃,对老师所提问题会做出很快的反应,于是师生配合能呈现出较好的效果。 3.课堂要真正体现出以教师为主导、以学生为主体的教学理念。目前,正提倡把课堂还给学生,让学生具有自主学习和思考的时间和空间。在课堂中,尽可能让学生自己去解决问题,尽量多给学生练习的机会的。例如小组间进行竞赛,分任务完成老师提出的问题,从而调动学生的积极性。 4.要重视课堂中的教学用语,力求生动活泼,简明精炼,多做师生间的情感交流。多说些赏识性的语言,不仅维护学生自尊,还能使师生关系更为亲密融洽,有利于开展教学活动。 让学生成为课堂的主体。学生是学习的主人,是学习的主体。教学中只有充分调动学生认知的,心理的,生理的,情感的,行为的等方面的因素,让学生进入一种自主的学习境界,才能充分发挥学生的主观能动性,融自己的主见于主动发展中。为了让学生更好的发挥他们的主体作用,把他们的被动学习变为主动参与,我觉得我要在以下两方面下功夫。 (1)创设情境,引人入胜。 (2)巧设疑问,激发求知。古人云,学起于思,源于疑。巧妙的疑问,扣人心弦的悬念设置,能激起学生强烈的求知欲,促进学生积极思维,主动参与课堂活动。亚里士多德说过,思维自疑问和惊奇开始。问题是思维的向导,只有把问题设计的巧妙,学生才会积极思考。因此,教师应该在问题的设计上花点心思。 通过上公开课,我更加认识到自己的缺点和不足,做到取长补短。在教学中如果能把学生的学习主动性和积极性发挥好的话,我们的教学将会起到事半功倍的作用,教师教得轻松,学生学得愉快。我想在以后教学中,我会更加注重对于课堂教学的重视和把握,不断地学习,从而提高自己的教学水平,使枯燥的专业教学具有一定的特色,让更多的学生喜欢上专业课。 再次,通过这次的公开课,我感受到要上好一节课,如下环节不可忽视: 1、课前做好充分的准备。老师要深入钻研授课内容,注重研究教材教法,注重把知识和能力既深入浅出又扎扎实实的传授给学生,注重研究教材教法,注重把知识和能力既深入浅出又扎扎实实的传授给学生。 2、让学生成为课堂的主体。学生是学习的主人,是学习的主体。教学中只有充分调动学生认知的,心理的,生理的,情感的,行为的等方面的因素,让学生进入一种自主的学习境界,才能充分发挥学生的主观能动性,融自己的主见于主动发展中。为了让学生更好的发挥他们的主体作用,把他们的被动学习变为主动参与。 3、情景教学设计。为了能够让学生在课堂上能有所收获,在课堂设计上也尽量从学生的实际水平出发,设计一节学生能接受的情景教学场景。

关于小学公开课的心得体会

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状态,由自发的好奇心变为强烈的求知欲,产生跃跃欲试的主体探索意识,实现课堂教学中师生心理的同步发展。揭示知识的新矛盾,让学生用数学思想去思考问题,解决问题。使他们在质疑中思考,“山重水复疑无路”,在思考中学到知识,寻求“柳暗花明又一村”的效果。总之,赵教师注重从学生的生活实际出发,为学生创设现实的生活情景,充分发挥学生的主体作用,引导学生自主学习、合作交流的教学模式,让人人学有价值的数学,不同的人在数学上得到不同的发展,体现了新课程的教学理念。 篇二 实验小学举办了“教学艺术节”活动,我校老师积极参加了听课评课活动。在活动结束后,我们数学教研组又组织开展了听课反思活动。在教研活动中,老师们就所听的课,积极地进行了评价,并对照自己的课堂教学找出了存在的问题。 本次听课我们共听了6节课,分别是一年级《9的认识》,二年级《5的乘法口诀》,三年级《有余数的除法》,四年级《神奇的莫比乌斯带》,五年级《用字母表示数》,六年级《鸡兔同笼》。这几节课整堂课的教学形式就是一堂常态课、没有更多的修饰和虚华的成分,没有令人眼花缭乱的动画,没有临场作秀的氛围,自然、得体、和谐。 一、课题引入简单快捷。有的以小游戏等活动导入新课。有的以谈话的形式导入,有的是复习导入。

上公开课的心得体会

上公开课的心得体会 上公开课的心得体会 为了让家长了解孩子在学校的一日生活、学习情况,了解老师的讲课水平,加强学校与家长之间的沟通交流,我校于2017年11月23日举行了“家长开放日”活动。家长开放日过去了,忙碌过后,收获甚多。作为二年级四班的英语科任老师,在本次家长开放日活动中,我所担任的任务是组织二年级四班家长于11月23日下午第一节课在本校二四班教室聆听我在本班所讲授的英语公开课,清华版二年级英语上册第三单元《long and short》一课。开放日过去了,公开课结束了,收到的结果,自我感觉还需继续努力。下面就本次开放日活动,谈几点自我的反思。首先,也是最重要的一个方面,就是这堂公开课。在准备阶段,首先自己认真阅读教材,明确教学目标,分清本课的重点,难点,想办法如何以学生喜闻乐见的方式去突破难点,在参阅了各种教参以及网络备课资源的基础上,我大体设计出了自己的教学思路,又抽时间观看了多位优秀教师关于本节课的优质课教学视频,充实环节与环节之间的自然过渡,模仿精准的英语课堂用语,学习他们用多种方式激励学生的技巧。并在二年级其他班试讲多次后,认真听取同学科教师的建议,进行自我反思琢磨,认真修改教案。然而,真正上完这堂公开课之后,我才意识到问题的多方面性,才忽然发现自己准备的远远不够。整堂课下来,大体的教学流程还是比较顺利的,问题出在细节,第一是上课铃还没响,就已经引导学生做热身活动了,速度有些快,第二,时间安排太紧凑,课堂教学内容比较多,导致最后一道练习题没有及时处理,就匆匆下课。其实,课堂练习不足,一直是我讲课的症结所在,日后得提高课堂做题效率。最后,课堂提问照顾不到各个学习层次的学生,出现只提问中等或中等偏上的,积极举手的,对于上课注意力不集中,不积极举手发言的孩子没有及时纠正,正确引导。家长开放日,是学校开展的一项面向学生家长的活动,目的在于让学生家长深入了解自己孩子在学校的表现情况,了解老师的讲课水平,增加学校办学的透明度。学校领导安排我进行课堂展示,是对我的信任,也是给我一次自我展示的机会,这堂课的好坏不仅关系到我个人的利益,还关系到学校在社会中的影响。作为一名青年教师要重视自身的师德形象,为人师表最重要的就是要有良好的道德品质,积极向上的

精选公开课心得体会

精选公开课心得体会 精选公开课心得体会1 我代表徐汇区向全市小学语文教师上了一堂公开课,意在向老师传达一些二期课改的理念。 说句实话,二期课改的理念我们都会说,但关键是如何在课堂上体现出来,这就要求老师在上课时,不仅要考虑教学内容的圆满,更要考虑先进理念转变为教学行为的可操作性,也就是我们常说的“从备教材到备学生”的转变。在这儿,我就想谈谈通过这堂课我的一些启发与收获,让我们共同切磋、学习。 这堂课主要强调学生的主体参与性,因为学生只有主动参与才能获得发展,而发展又应当首先体现在创新精神的树立和实践能力的提高,因此,我们采取了以下教学策略: 一、创设情景,“疑”中求“新” “疑”即质疑问难,古人云“学贵有疑”,“学则须疑”,疑是思之源,思是智之本,疑是探求新知的开始,也是探求新知的动力。进一步说,疑是创新的开始,也是创新的动力。因此,在教学过程中教师要鼓励学生大胆质疑,主动探索,创造性地释疑。 就拿《爸爸和书》这堂公开课来说吧,在学习新课之前我就安排学生质疑。学生开始提出的问题多为“‘珍宝’什么意思”等这样的表层问题,而在课堂上,经过深入思考后,学生进一步提出了“‘我’为什么会视这么一本又薄又破旧的书为珍宝”这样较有价值的问题。

而我在教学时则就以此为突破口,引导学生采用“联系上下文,边读边思”的方法来解决这一疑问。 二、尊重主体,“放”中寓“新” “放”即开放,传统的语文教学大多是“牵牛式”的,教师严格地牵着行,学生小心地跟着走,大量的时间在分析讲解中虚度,这样的做法不仅不利于发展学生的思维,而且难以提高教学效果,而教师如果善于设计开放性的问题,就能充分发挥学生的个性,激活学生思维的热情,启迪学生的创新思维。 因此这堂课上,我就针对学生提出的疑问,让学生展开讨论,通过找出文中相关的词、句,来证明自己的观点。学生在讨论后,纷纷举手,各抒己见,有人认为“因为这本书是‘我’省下车钱好不容易买来的,所以会视它为‘珍宝’。”也有学生抓住“临时工”、“干零活”这两个词,说“这本书书是爸爸在生活十分窘迫的情况下给‘我’买的,其中包含着深深的父爱,所以我会如此珍惜。”再往下学,同学们又发现了另一个原因,那就是读书给‘我’带来了许多快乐。至此,同学们通过“联系上下文,边读边思”的方法,自己总结出了“我们”视这么一本又薄又破旧的书为“珍宝”的两个原因。 三、树立信心,“异”中见“新” “异”即求异,它是创新思维的核心,教学中要引导学生大胆提出自己的见解,展开不同意见的争论,使学生突破常规和经验的禁锢,积极、独立地探索问题。学生摒弃了单向线形的狭隘思路,就可以求得多种设想、方案和结论,从而创造性地解决问题,思维的广阔

农村中小学信息技术教育调查报告

农村中小学信息技术教育调查报告 镇平县贾宋镇贾宋小学李玉俭 2009.4

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