R8A66162SP中文资料

R8A66162SP

32-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH REJ03F0263-0100

Rev. 1.00

Jan. 24. 2008

DESCRIPTION

The R8A66162SP is a semiconductor integrated circuit for LED array driver with 32-bit serial-input, parallel -output shift register, equipped with direct set input and output latches.

The R8A66162SP guarantees sufficient 24mA (Vcc=5.0V case) output current to drive anode common LED, allowing 32-bit simultaneous and continuous current output. The parallel outputs are open-drain outputs.

In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures the realization of an easy printed circuit. R8A66162SP is the succession product of M66313FP. FEATURES

● Anode common LED drive

● V CC 5V or 3.3V single power supply

● High output current: All parallel outputs Q1~Q32I OL=24mA (at V CC=5.0V), I OL=12mA (at V CC=3.3V), LEDs can be turned on simultaneously.

● Low power dissipation: 200uW/package (max) (V CC=5.0V, Ta=25O C, quiescent state)

● High noise margin: Employment of Schmitt-trigger circuit on all inputs allows application with long wiring.

● Direct set input (S D)

●132

● Serial data output for cascading (SQ32)

● Wide operating temperature range (Ta=-40o C~+85o C)

● Pin configuration for easy layout on PCB. (Pin configuration allows easy cascade connection or LED connection)

APPLICATION

● LED array drive, The various LED display modules

● PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipments

BLOCK DIAGRAM

PIN CONFIGURATION ( TOP VIEW )

FUNCTIONAL DESCRIPTION

The employment of silicon gate CMOS process of the R8A66162SP guarantees low power dissipation and maintains high noise margin as well as high output current and high speed required to drive LEDs. Each shift register bit consists of a flip-flop for shifting and an output latch.

The shift operation takes place when the shift clock input CK changes from low-level to high-level.

The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is

shifted in sequence when a pulse is applied to CK.

If the latch-enable input LE is turned high-level, the content of the shift register at that instant is latched. The parallel data outputs Q 1~Q 32 are open-drain outputs.

To expand the number of bits, use the serial data output SQ 32 which shows the output of the shift register of the 32nd bit.

If the direct set input S D is turned low-level, Q 1~Q 32 and SQ 32 are set. Then shift register and latches are set. If the high-level input is applied to the output enable input OE, Q 1~Q 32 are set to the high-impedance state, but SQ 32

P P P P P P AR ALLE L D ATA

OU TPUTS

SERIAL DATA INPUT DIRECT SET INPUT SHIFT CLOCK INPUT

AR ALLE L D ATA

OU TPUTS

AR ALLE L D ATA

OU TPUTS

AR ALLE L D ATA

OU TPUTS

AR ALLE L D ATA

OU TPUTS

AR ALLE L D ATA

OU TPUTS

FUNCTION TABLE (Note: 1)

(Ta=-40~85o

C, unless otherwise noted)

RECOMMENDED OPERATING CONDITIONS (Ta=-40~85o

C, unless otherwise noted)

Limits Symbol

Parameter

Min. Typ. Max. Unit

5.0V support 4.5 5.0 5.5 V Vcc Supply voltage 3.3V support

3.0 3.3 3.6 V V I Input voltage

0 Vcc V V O Output voltage 0 Vcc V

T opr Operating temperature range

-40 85 o

OUTPUT

0N ote 1. Q X q q Z 0 Tran sition from lo w-to-high-le vel

Sho ws the statu s o f output Q befo re C K input changes

Irrele vant The content o f shi f t regi s ter be fo re C K changes The content o f shi f t regi s ter H igh-im pedance state 0OPER A TION M O DE SHIFT LATCH INPUT

PARALLEL OUTPUTS

SERIAL SQ 32

CK A SD LE OE Q 1

Q 2

Q 3

Q 4

Q 5

Q 6

Q 7

Q 8

Q 9

Q 10

Q 11

Q 12

Q 13

Q 14Q 15Q 16Q 17Q 18Q 19Q 20Q 21Q 22Q 23Q 24Q 25Q 26Q 27Q 28Q 29Q 30Q 31Q 32

H L H L H L L L H X H X L SET L X X X L L L L L L L L L L L L L

0Q 2

0Q 3

0Q 4

Q 5

0Q 6

00Q 7

0Q 8

0Q 9

Q 12

0Q 140

Q 150

0Q 190

Q 200

0Q 230

Q 240

Q 250

Q 260

0Q 280

Q 290

Q 300

0Q 2

0Q 3

Q 4

00Q 5

0Q 6

0Q 7

Q 8

0Q 9

00Q 10

Q 11

0Q 12

Q 13

Q 140

Q 150

Q 16

Q 17

Q 18

Q 190

Q 200

0Q 21

Q 22

Q 230

Q 240

Q 250

Q 260

Q 27

Q 280

Q 290

Q 300

Q 31

q 31

L Z Z L 0Q 1

0Q 3

Q 4

0Q 5

00Q 6

0Q 7

0Q 8

Q 9

00Q 10

0Q 11

Q 12

0Q 13

Q 150

Q 160

Q 200

Q 210

Q 240

Q 250

Q 260

Q 270

Q 290

Q 300

Q 310

320

L 0Q 1

0Q 1

0Q 2

Z OUTPUT DIS-ABLE X X X X H Z Z Z Z Z Z Z Z Z Z Z

Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z q

0Q 10

Q 11

ELECTRICAL CHARACTERISTICS

(Ta=-40~85o C, Vcc=4.5V~5.5V, unless otherwise noted)

(Ta=-40~85 o

C, Vcc=5.0V or 3.3V, unless otherwise noted)

(1) The pulse generator(PG)Note3. Test circuit

has the following characteristics(10%~90%):t r =6ns,t f =6ns (2)The capacitance C L includes stray wiring capacitance and the probe input capacitance.

TIMING DIAGRAM

SQ32

Q1 Q32

t w

50%50%50%

t PLH t PHL

50%50%

V C C

GND

V OH

V OL

10%

t w

t PLZ t PZL

50%

V OL

V C C

50%

10%

t PZL

V OL

V C C

GND

1 Q32

V C C

50%

t PLZ

50%

t PZL

t PLZ

50%

V C C

GND

V OL

Q1 Q32

t w

50%

V C C

50%

t h

V C C

GND

V C C

GND

50%

Q1 Q32V OL

V C C

SQ32

Q1 Q32

50%50%

50%

V C C

GND

V OH

V OL

V C C

GND

V OL

S D

t w

t rec

t PLH

t PZL

V C C

50%

t su t h

50%

V C C

GND

V C C

GND

PACKAGE OUTLINE

Package RENESAS Code Previous Code

48pin SSOP PRSP0048ZB-A 48P2X-A

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