delay-locked loop

ECE658Project-Delay Locked Loop Design

Y.Sinan Hanay

December20,2007

Chapter1

Introduction

Generation and distribution of clock signals inside the VLSI systems is one of the most important problems in the design of VLSI systems.Because of the process variations and interconnect parasitics,clock signals delays vary for di erent paths.The clock signals should have zero clock skew,that is to say all the clock signals should arrive at the inputs of registers at the same time.Otherwise latches and ip- ops get clock signal at di erent time instances.In order to circuit to operate correctly these di erences should be eliminated,ideally to zero.However it is not possible practically and10%of the clock cycle is expended in order to compensate for clock skew[1].To handle this problem,several solutions are proposed.One of which is usage of H-tree clock networks,in which con guration the distance to all circuit blocks is same thus the clock delay would be same.But this technique is hard to implement since the di erent fan-out requirements for di erent blocks and routing constraints.Also some CAD techniques and heuristics are used in the routing of the clock trees[6].

The reduction of clock skew is one of the important problems in the VLSI design.Passive techniques such as clock network optimization techniques cannot completely reduce the clock skew[2].Phase-locked loops and delay-locked loops(DLL)are extensively used in VLSI circuits in order to decrease clock screw in the clock networks.DLL is a rst order loop that compares it`s input with a reference signal,than delay it`s output so that it can synchronize with the reference signal in a feedback fashion.

DLL consists of4units:

1.Phase Detector

2.Charge Pump

3.Filter

4.Voltage Controlled Delay Line(VCDL)

It`s working principle is as follows:First,phase detect block compares the reference clock signal with the output signal,depending on the di erence,if reference signal is leading the output Up(U)signal,else if the reference signal lagging the output signal Down(D)signal is asserted,and thus controls the delay line appropriately.VCDL adjusts the phase of the output signal proportional to the di erence between reference signal until the output signal is high%50

of the time.In the gure below this principle is illustrated

DLL Design

DLLs are notoriously di cult to build correctly.They require expertise in both feedback control systems and analog design.

(N.Weste,D.Harris,A.Banerjee,2005:490[14])

In this project some part of the design required Analog design and control systems background. DLLs can be classi ed in two groups:Analog and Digital DLLs.Digital DLLs have the advantage of higher exibility on supply voltage and low design complexity,while Analog DLLs o er better jitter[9],smaller area,low noise sensitivity and power consumption[8].The DLL consists of four main components,and they will be discussed in the following sections.

1.1Phase Detector

In order to deskew the clock, rst of all the skew must be known.This skew can be detected by the phase detectors.Its function is to detect the phase di erence between reference clock signal with the input clock signal.It takes these clock signals as input and produces an output that is proportional to the phase di erence.Phase detectors can be analog or digital.The rst phase detectors used in locked-loops was the linear multiplier phase detector,but as the PLLs became to implemented by digital components,digital phase detectors become popular[7].Simplest digital detector is an XOR gate,of which output is zero if the two inputs have same phase, and one as long as they are not equal.Phase detectors can be implemented digitally by J-K ip- ops.In this work,linear phase detector proposed in[4]is implemented is shown in Figure 1.1.Schematic and layout of the phase detector are shown in Figure1.2and1.3.

Figure1.2:Phase Detector

Figure1.3:Layout of the Phase Detector

1.2Charge Pump

Charge pump design was one of the most complicated part of the DLL.The zero-o set charge pump that was mentioned in[5]was used.Figures1.4and1.5shows the schematic and layout of the charge pump.

1.3Filter

Figure1.4:Schematic of the Charge Pump

eleminating the higher frequency terms(odd-harmonics)in the product.This elemination,or ltering,is done by a low pass lter.In DLLs there is no need to include a low pass lter, instead a capacitor is used in order to integrate the phase error mainly,and thus increasing control voltage appropriately.So lter block is simply a capacitor,and a100fF capacitor was used.Increasing capacitor increases the lock time while decreases the bandwidth and the ripples on the control voltage,and decreasing it decreases lock time and increases the ripples.

1.4Voltage Controlled Delay Line

The function of Voltage Controlled Delay Line(VCDL)is to delay the reference signal so that there is no skew between the output clock and reference signal.Its transfer function is simply, t d=κDL V filter

where V filter is the ltered control input to the VCDL fromcharge pump,t d is the delay(the output)andκis the gain of VCDL.The minimum and maximum delay should be T c

and1.5×T c

2 For the voltage controlled line,there are several di erent techniques can be employed by analog or digital circuitry.The most common techniques use cascaded inverters.Inverters are used speci cally for the highest delay resolution.Two main usage of cascaded inverters are called: 1)Current-Starved Inverter Delay Line(in Figure1.6)and2)Shunt Capacitor Delay Stage(or Capacitor-Loaded Inverter Delay Line in Figure1.7[10].

The delay range of Current-starved inverter circuit is higher than Shunt-capacitor circuit, however Shunt-capacitor transfer function is more linear and has lower gain than the that of Current-starved one[11,10].Lower gain is important because higher gain also ampli es the

Figure1.5:Layout of the Charge Pump

the VCDL is modeled as linear with gainκdl.In this project I used a two-stage shunt-capacitor delay circuit for the reasons mentioned above.The reason for using two stage is because its noise immunity is higher.Increasing delay stages increasesκd,and which in turn will increase the jitter[13].I also implemented8stage VCDL but did not get satisfactory results.Figure1.8 shows the implemented VCDL`s transfer characteristics.Maximum achievable delay is around

1.4ns.

Figure1.6:Current-Starved Inverter Delay Line[10]

Figure1.7:Shunt Capacitor Delay Stage[12]

Figure1.8:Implemented VCDL`s Transfer Characteristics

1.5Simulations

Figure1.11shows the simulation results for250MHz.As it can be seen from the gure,the locking is achieved aroung14th cycle with a static phase error of194ps when the clock is leading the reference signal.By decreasing charge pump`s output resistance it is possible to delay in a shorter time and suppressing the phase error.The results of decreasing charge pump`s output resistance is show in Figure1.12.It reveals that locking is achieved at6th clock cycle,but drawback here is the pulse-width of the clock is decreased too.Figures also show that in the lock state,both UP and DOWN signals are asserted for same duration,and the charge pump current rst increases then decreases by the same amount,e ectively putting no net charge to lter.Figure1.13shows the static error of192ps for DLL running at1GHz,when the clock is lagging the reference signal.

Figure1.9:Layout of the VCDL

Figure1.10:Layout of the DLL

Figure1.11:DLL at250MHz

Figure1.12:DLL at250MHz

Figure1.13:DLL at1GHz

Results and Conclusions

In this section implemented DLL`s performance is compared with some previous works.

This Work JSSC99[9]Thesis[8]

Process0.25μm CMOS0.40μm CMOS0.18μm CMOS Max Operating Frequency800MHz667MHz700MHz

Min Operating Frequency200MHz250MHz160MHz

Lock Time14cycles 2.9μs11cycles Static Phase Error192ps 80ps The DLL`s noise immunity can be improved by employing Self Biased techniques mentioned in which the process dependent variables in the system dynamics are eliminated[5].In another work,noise immunity is increased by using regulated Supply CMOS Bu ers[4].However since these techniques require di erential elements it increases the circuit complexity

Appendix

L VS Reports

1)L VS Report of the Phase Detector

@(#)$CDS:LVS version5.0.006/02/200321:50(cds11620)$

Like matching is https://www.360docs.net/doc/a91609595.html, swapping is https://www.360docs.net/doc/a91609595.html,ing terminal names as correspondence https://www.360docs.net/doc/a91609595.html,piling Diva LVS rules...

Net-list summary for/grads/h/hanay/Dokuman/proje/LVS/layout/netlist count18nets6 terminals14pmos16nmos

Net-list summary for/grads/h/hanay/Dokuman/proje/LVS/schematic/netlist count18nets 6terminals14pmos16nmos

Terminal correspondence points1DN2UP3ckin4ckref5gnd!6vdd!

The net-lists match.

instances layout schematic

un-matched00

rewired00

size errors00

pruned00

active3030

total3030

nets un-matched00merged00pruned00active1818total1818

terminals un-matched00matched but di erent type00total66

Probe les from/grads/h/hanay/Dokuman/proje/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

prunenet.out:

prunedev.out:

audit.out:

2)L VS Report of the Charge Pump

@(#)$CDS:LVS version5.0.006/02/200321:50(cds11620)$

Like matching is https://www.360docs.net/doc/a91609595.html, swapping is https://www.360docs.net/doc/a91609595.html,ing terminal names as correspondence https://www.360docs.net/doc/a91609595.html,piling Diva LVS rules...

Net-list summary for/grads/h/hanay/LVS/layout/netlist

count

13nets

6terminals

10pmos

8nmos

Net-list summary for/grads/h/hanay/LVS/schematic/netlist

count

13nets

6terminals

10pmos

8nmos

Terminal correspondence points1DN2OUT3UP4VBN5gnd!6vdd!

The net-lists match.

instances layout schematic

un-matched00

rewired00

size errors00

pruned00

active1818

total1818

nets un-matched00merged00pruned00active1313total1313

terminals un-matched00matched but di erent type00total66

Probe les from/grads/h/hanay/LVS/schematic

devbad.out:

netbad.out:

Probe les from/grads/h/hanay/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

2)L VS Report of the Voltage Controlled Delay Line

@(#)$CDS:LVS version5.0.006/02/200321:50(cds11620)$

Like matching is https://www.360docs.net/doc/a91609595.html, swapping is https://www.360docs.net/doc/a91609595.html,ing terminal names as correspondence https://www.360docs.net/doc/a91609595.html,piling Diva LVS rules...

Net-list summary for/grads/h/hanay/LVS/layout/netlist count8nets5terminals2pmos 14nmos

Net-list summary for/grads/h/hanay/LVS/schematic/netlist count8nets5terminals2pmos 6nmos

Terminal correspondence points1gnd!2out3vctrl4vdd!5vin

The net-lists match.

instances layout schematic

un-matched00

rewired00

size errors00

pruned00

active168

total168

nets un-matched00merged00pruned00active88total88

terminals un-matched00matched but di erent type00total55

Probe les from/grads/h/hanay/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

Probe les from/grads/h/hanay/LVS/layout devbad.out:

netbad.out:

mergenet.out:

termbad.out:

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audit.out:

Bibliography

[1]S.M.Kang,Y.Leblebici,CMOS Digital Integrated Circuits,McGraw Hill,2003.

[2]Z.Zilic,Phase-and Delay-Locked Loop Clock Control in Digital Systems,

https://www.360docs.net/doc/a91609595.html,.

[3]J.M.Rabaey,A.Chandrakasan,and B.Nikolic,Digital Integrated Circuits,2nd ed.,Prentice

Hall,2003.

[4]S.Sidiropoulos,D.Liu,J.Kim,G.Wei,and M.Horowitz.Adaptive bandwidth DLLs and

PLLs using regulated supply CMOS bu ers.In Proc.IEEE Symposium on VLSI Circuits, pages124 127,June2000.

[5]Maneatis,et al.,"Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Tech-

niques,"IEEE Journal of Solid-State Circuits,Vol.31,No.11,November1996.

[6]N.Menezes,S.Pullela,A.Balivada and L.T.Pillage,Skew Reduction in Clock Trees Using

Wire Width Optimization,Proceedings Custom Integrated Circuits Conference,May1993.

[7]R.E.Best,Phase-Locked Loops,6th Edition,McGraw Hill,2007.

[8]C.Jia,A Delay-Locked Loop for Multiple Clock Phases/Delays Generation,Doctoral Thesis,

Georgia Institute of Technology,2005.

[9]B.W.Garlepp,K.S.Donnelly,J.Kim,P.S.Chau,J.L.Zerbe,C.Huang,C.V.Tran,C.

L.Portmann,D.Stark,Y.-F.Chan,T.H.Leen,and M.A.Horowitz, A Portable Digital DLL for High-Speed CMOS Interface Circuits, IEEE J.Solid-State Circuits,vol.34,pp.

632 644,May1999.

[10]M.G.Johnson and M.E.Hudson, A variable delay line PLL for CPUcoprocessor synchro-

nization, IEEE J.Solid-State Circuits,vol.23,pp.1218 1223,Oct.1988.

[11]W.J.Dally and J.W.Poulton, Digital Systems Engineering ,Cambridge University Press,

1998.

[12]S.Liu,J.Lee and H.Tsao,"Low-power clock-deskew bu er for high-speed digital circuits",

IEEE Journal of Solid-State Circuits,SC-34,pp.554-558,April1999.

[14]N.H.E.Weste,D.Harris and A.Banerjee, CMOS VLSI Design A Circuits and Systems

Perspective ,Pearson Addison-Wesley,2005.

[15]B.Razavi, Design of CMOS Analog Integrated Circuits ,McGraw Hill,2001.

[16]P.Gray,P.J.Hurst,S.H.Lewis,R.G.Meyer, Analysis and Design of Analog Integrated

Circuits ,John Wiley Sons,Inc,2001.