Design for Testability (DFT) - The University of Texas at Austin

406040

6080mm With scan chain ,problem of testing any the combinational logic

ECE Department,University of Texas at Austin Lecture 21.Design for Testability 40604060

mm Level-Sensitive Scan Design (LSSD)

Structured DFT developed at IBM

All internal storage implemented in latches (SRLs),part of a scan chain

Latches controlled by two or more with rules for clocking

All clock inputs to SRLs must be in primary inputs (PIs)are “o?”

Clock signal at any clock input to from one or more clock PIs

No clock can be ANDed with another Clock PIs cannot feed data inputs through combinational logic ECE Department,University of Texas at Austin Lecture 21.Design for Testability

Department,University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November 9,20114/49406080100120

mm Scannable Flip-Flops

University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November 9,

406080100 of Texas at Austin Lecture21.Design for Testability J.A.Abraham,

40608010040

mm University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November 406080100406080

mm Boundary Scan Interface

Boundary scan is accessed through ?ve pins

TCK:test clock TMS:test mode select

TDI:test data in

TDO:test data out

TRST*:test reset (optional)

Chips with internal scan chains can access the chains through boundary scan for uni?ed test strategy

University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November

406080100 of Texas at Austin Lecture21.Design for Testability J.A.Abraham,November

Department,University of Texas at Austin Lecture21.Design for Testability

40608040

6080

mm ECE Department,University of Texas at Austin Lecture 21.Design for Testability 40604060

80mm Testability Issues –Custom Microprocessors

Chip complexity,large volumes,costs

Area/performance penalties

Fault (defect)coverage goals

Test

generation (fault simulation)costs Development time

Tester time (manufacturing costs)

ASICs generally use a “full scan”methodology Some of the ad-hoc techniques used in custom be described in the following slides ECE Department,University of Texas at Austin Lecture 21.Design for Testability

6080Department,University of Texas at Austin

Lecture 21.Design for 40604060

mm Microrom Test in MC68881Floating ROM physically split into two sections

In test mode,ROM is addressed command register Exhaustive addresses fed to ROM (address/address complement)

Outputs of ROM go to two 16-bit CCITT-16polynomial x 15+x 12Monitor both the quotient and test pin (Probability of aliasing Department,University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,

Austin Lecture 21.Design for Testability J.406080406080Entry PLA Test

PLAs,A0,A1,A2and A3

PLA contains the entry point reset vectors completely tested functionally

tested like the ROMs

Command register patterns and outputs through a bus to register

Test patterns generated test generator

PLA Inputs A16A213A35Response 25Department,University of Texas at Austin

Lecture 21.Design for Testability J.

406080Responses compressed using multiple-input Department,University of Texas at Austin Lecture 21.Design for Testability 40604060

mm Testing Cache Memory Arrays in MC68030

Cache cell layout design is resistant and capacitive coupling

Most likely bridging defect is between Memory fault model:

One or more cells stuck at 0or 1

Coupling between cells

11n March Test (Marinescu,1982)

Refresh and data retention tests for the dynamic memory cells

Department,University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November

406080100

University of Texas at Austin Lecture21.Design for Testability J.A.Abraham,November

40608010040

mm University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November 40608010040

80mm IBM Risc System/6000

with pseudo-random BIST

University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November Common Engineer-

Processor (COP),

on-card sequencer

engineering

processor (ESP)

406080100120

80mm Hardware for pseudo-random vector generation and result

compression (31-bit LFSR)

Department,University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November 9,201128/49Small processor controls operation 406080

100120

406080

mm BIST in IBM/Motorola Power-PC

Variety of test techniques applied to the Power-PC 603

Full LSSD test of logic BIST of “large”embedded RAMS

Functional test of small RAMS

I DDQ tests BIST for cache and tag RAMs Functional vectors (good for data cache,not instruction cache)

and random BIST (size,complexity,test coverage)not

applicable

Use modi?ed march test of Dekker (1988)

log 2n pattern for data

Overhead:BIST is 2.9%of RAM array,0.58%of total chip

Performance impact:less than 100pS due to extra MUX

input leg All four RAMs tested in parallel,2.5mS at 80MHz

Department,University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November 9,201129/49

4060

80mm Source/Sink for test:Embedded processor

Test access mechanisms:Busses

Core test “wrapper”for Test Access

Interface (TAI)

Department,University of Texas at Austin Lecture 21.Design for Testability

4060406080mm Issues with Built-In Self Test

Technique can run test sequences at operating capture results within the chip

Pseudorandom pattern generators,Can also use weighted random

patterns or deterministic patterns

Example (Synopsys):(Deterministic

Logic BIST

Problems:

Hardware overhead

Test power

Non-functional modes during test Department,University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November 9,201131/

406080100mm Pseudo-code for software signature analyzer general register or memory,holds signature each register R i to be compressed Shift Right Through Carry(R i );(Carry){S =XOR(S,feedback polynomial)}XOR(S,R i );of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November 406080100Functional BIST

Functional Random Instruction Testing at Speed (FRITS)Itanium processor family and Pentium 4line (ITC 2002)(kernels)are instruction sequences

Kernels loaded into cache and executed in real time during

application

They generate and execute pseudo-random or directed

sequences of machine code

Pentium-4,FRITS

added 5%unique coverage to manual tests

screened 10%–15%of chips which passed wafer

sort/package tests,but failed system tests

enabled low-cost testers:40%increase in defect screening structural tester

Kernels execute 20loops in ≈8mSecs

of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November

406080100mm DAFCA

of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November 406080100406080

mm Analysis and Signal Capture

DEMON implements Signals Tracer

Software trace bu?er prepares FSDB ?les

Source:DAFCA

Department,University of Texas at Austin Lecture 21.Design for Testability J.A.Abraham,November