LC320EUD-SCA1

LC320EUD-SCA1
LC320EUD-SCA1

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LC320EUD
Product Specification
SPECIFICATION
FOR APPROVAL
(
) Preliminary Specification
( ● ) Final Specification
Title
BUYER MODEL General
32.0” WUXGA TFT LCD
SUPPLIER *MODEL SUFFIX LG Display Co., Ltd. LC320EUD SCA1
*When you obtain standard approval, please use the above model name without suffix SIGNATURE DATE
APPROVED BY /
APPROVED BY P.Y. Kim / Team Leader
SIGNATURE DATE
REVIEWED BY / T.H. Lee / Project Leader
PREPARED BY / Y.H. Lee / Engineer
Please return 1 copy for your confirmation with your signature and comments.
Ver. 1.0
TV Product Development Dept. LG Display Co., Ltd.
1 /38

LC320EUD
Product Specification
CONTENTS
Number
COVER CONTENTS RECORD OF REVISIONS 1 2 3 3-1 3-2 3-3 3-4 3-5 3-6 4 5 6 7 7-1 7-2 7-3 8 8-1 8-2 9 9-1 9-2 9-3 9-4 9-5 9-6 Ver. 1.0 GENERAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS ELECTRICAL SPECIFICATIONS ELECTRICAL CHARACTERISTICS INTERFACE CONNECTIONS SIGNAL TIMING SPECIFICATIONS LVDS SIGNAL SPECIFICATIONS COLOR DATA REFERENCE POWER SEQUENCE OPTICAL SPECIFICATIONS MECHANICAL CHARACTERISTICS RELIABILITY INTERNATIONAL STANDARDS SAFETY EMC ENVIRONMENT PACKING INFORMATION OF LCM LABEL PACKING FORM PRECAUTIONS MOUNTING PRECAUTIONS OPERATING PRECAUTIONS ELECTROSTATIC DISCHARGE CONTROL PRECAUTIONS FOR STRONG LIGHT EXPOSURE STORAGE HANDLING PRECAUTIONS FOR PROTECTION FILM
ITEM
Page
1 2 3 4 5 6 6 8 11 12 15 16 18 22 25 26 26 26 26 27 27 27 28 28 28 29 29 29 29 2 /38

LC320EUD
Product Specification
RECORD OF REVISIONS
Revision No.
1.0
Revision Date
Feb, 25, 2010
Page
Final Specifications
Description
Ver. 1.0
3 /38

LC320EUD
Product Specification
1. General Description
The LC320EUD is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED) b a c k l i g h t s ys t e m . T h e m a t r i x e m plo ys a- S i T h in F i lm T r ans is to r as the ac t i ve e lem ent. It is a transmissive display type which is operating in the normally black mode. It has a 31.55 inch diagonally measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot. Therefore, it can present a palette of more than 1.06Bilion colors. It has been designed to apply the 10-bit 4-port LVDS interface. It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast response time are important.
CN2
(41pin)
LVDS
EEPROM LVDS 3,4 SCL SDA
Mini-LVDS(RGB)
Source Driver Circuit
S1 G1 S1920
2Port
LVDS
2Port
LVDS Select Bit Select +12.0V CN1
(51pin)
LVDS 1,2 Option signal
Timing Controller
LVDS Rx + OPC + DGA + ODC Control Integrated Signals
TFT - LCD Panel
(1920 × RGB × 1080 pixels) [Gate In Panel]
G1080
I2C
Power Circuit Block
Power Signals
+24.0V, GND, On/Off ExtVBR-B
LED Driver
Back light Assembly
General Features
Active Screen Size Outline Dimension Pixel Pitch Pixel Format Color Depth Luminance, White Viewing Angle (CR>10) Power Consumption Weight Display Mode Surface Treatment 31.55 inches(801.31mm) diagonal 741.4(H) × 435.8 (V) X 10.8(B)/23.6(D) mm (Typ.) 0.36375 mm x 0.36375 mm 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement 10bit(D), 1.06Billon colors 450 cd/m2 (Center 1point ,Typ.) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.)) Total 81.32W (Typ.) [Logic= 7.32W, LED Driver=74W (ExtVbr_B=100% )] (TBD) 6.9 Kg (Typ. TBD) Transmissive mode, Normally black Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%) 4 /38
Ver. 1.0

LC320EUD
Product Specification
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or damage to the LCD module. Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter LCD Circuit Driver Driver Control Voltage ON/OFF Brightness T-Con Option Selection Voltage Operating Temperature Storage Temperature Panel Front Temperature Operating Ambient Humidity Storage Humidity Symbol Min Power Input Voltage VLCD VBL VOFF / VON EXTVBR-B VLOGIC TOP TST TSUR HOP HST -0.3 -0.3 -0.3 0.0 -0.3 0 -20 10 10 Value Max +14.0 + 27.0 +5.5 +5.5 +4.0 +50 +60 +68 90 90 VDC VDC VDC VDC VDC °C °C °C %RH 2,3 %RH 2,3 4 1 Unit Note
Note1. Ambient temperature condition (Ta = 25 ± 2 °C ) 2. Temperature and relative humidity range are shown in the figure below. Wet bulb temperature should be Max 39°C, and no condensation of water. 3. Gravity mura can be guaranteed below 40°C condition. 4. The maximum operating temperatures is based on the test condition that the surface temperature of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area from being over 68℃. The range of operating temperature may degraded in case of improper thermal management in final product design.
90% 60 60% Wet Bulb Temperature [°C] 30 20 10 0 10% 10 20 30 40 50 60 70 80 Humidity [(%)RH] 50 40 Storage
40%
Operation
-20
0
Dry Bulb Temperature [°C]
Ver. 1.0
5 /38

LC320EUD
Product Specification
3. Electrical Specifications 3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED backlight and LED Driver circuit. Table 2. ELECTRICAL CHARACTERISTICS
Value Parameter Circuit : Power Input Voltage Power Input Current Power Consumption Rush current VLCD ILCD PLCD IRUSH 800 7.32 1040 9.49 5.0 mA Watt A 2 1 3 10.8 12.0 610 13.2 790 VDC mA 1 Symbol Min Typ Max Unit Note
Note 1. The specified current and power consumption are under the VLCD=12.0V, Ta=25 ± 2°C, fV=120Hz condition whereas mosaic pattern(8 x 6) is displayed and fV is the frame frequency. 2. The current is specified at the maximum current pattern. 3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
White : 1023 Gray Black : 0 Gray
Mosaic Pattern(8 x 6)
Ver. 1.0
6 /38

LC320EUD
Product Specification
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
Values Parameter LED Driver : Power Supply Input Voltage Power Supply Input Current Power Supply Input Current (In-Rush) Power Consumption On On/Off Off VBL IBL_A Irush PBL V on V off ExtVBR-B PAL NTSC High Level Low Level 2.5 0.0 22.8 2.5 -0.3 10 24.0 3.1 74 0.0 100 120 5.0 0.8 25.2 3.3 5.3 79 5.0 0.8 100 Vdc A A W Vdc Vdc % Hz Hz Vdc Vdc On Duty 3 3 HIGH : on duty LOW : off duty 1 Ext VBR-B = 100% VBL = 22.8V Ext VBR-B = 100% 4 Ext VBR-B = 100% Symbol Min Typ Max Unit Notes
Brightness Adjust PWM Frequency for NTSC & PAL Pulse Duty Level (PWM) LED : Life Time
30,000
50,000
Hrs
2
Notes : 1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60 minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage 24Vand VBR (ExtVBR-B : 100%), it is total power consumption. 2. The life time(MTTF) is determined as the time which luminance of the LED is 50% compared to that of initial value at the typical LED current (ExtVBR-B :100%) on condition of continuous operating in LCM state at 25±2°C. 3. LGD recommend that the PWM freq. is synchronized with One time harmonic of Vsync signal of system. Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected. 4. The duration of rush current is about 10ms. 5. Even though inrush current is over the specified value, there is no problem if I2T spec of fuse is satisfied.
Ver. 1.0
7 /38

LC320EUD
Product Specification 3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector and 41-pin connector are used for the module electronics and 14-pin connector is used for the integral backlight system. 3-2-1. LCD Module - LCD Connector : FI-R51S-HF(manufactured by JAE) or KN25-51P-0.5SH(manufactured by Hirose) (CN1) Refer to below and next Page table - Mating Connector : FI-R51HL(JAE) or compatible Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION
No
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Symbol
NC NC NC NC NC NC LVDS Select VBR EXT OPC OUT OPC Enable GND R1AN R1AP R1BN R1BP R1CN R1CP GND R1CLKN R1CLKP GND R1DN R1DP R1EN R1EP NC
Description
No Connection No Connection No Connection No Connection (Reserved for LGD) No Connection (Reserved for LGD) No Connection (Reserved for LGD) ‘H’ =JEIDA , ‘L’ or NC = VESA External VBR (From System) OPC output (From LCM) ‘H’ = Enable , ‘L’ or NC = Disable Ground FIRST LVDS Receiver Signal (A-) FIRST LVDS Receiver Signal (A+) FIRST LVDS Receiver Signal (B-) FIRST LVDS Receiver Signal (B+) FIRST LVDS Receiver Signal (C-) FIRST LVDS Receiver Signal (C+) Ground FIRST LVDS Receiver Clock Signal(-) FIRST LVDS Receiver Clock Signal(+) Ground FIRST LVDS Receiver Signal (D-) FIRST LVDS Receiver Signal (D+) FIRST LVDS Receiver Signal (E-) FIRST LVDS Receiver Signal (E+) No Connection
No
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 -
Symbol
Bit Select R2AN R2AP R2BN R2BP R2CN R2CP GND R2CLKN R2CLKP GND R2DN R2DP R2EN R2EP NC NC GND GND GND NC VLCD VLCD VLCD VLCD -
Description
‘H’ or NC= 10bit(D) , ‘L’ = 8bit SECOND LVDS Receiver Signal (A-) SECOND LVDS Receiver Signal (A+) SECOND LVDS Receiver Signal (B-) SECOND LVDS Receiver Signal (B+) SECOND LVDS Receiver Signal (C-) SECOND LVDS Receiver Signal (C+) Ground SECOND LVDS Receiver Clock Signal(-) SECOND LVDS Receiver Clock Signal(+) Ground SECOND LVDS Receiver Signal (D-) SECOND LVDS Receiver Signal (D+) SECOND LVDS Receiver Signal (E-) SECOND LVDS Receiver Signal (E+) No Connection No Connection Ground Ground Ground No connection Power Supply +12.0V Power Supply +12.0V Power Supply +12.0V Power Supply +12.0V -
Note 1. All GND(ground) pins should be connected together to the LCD module’s metal frame. 2. All VLCD (power input) pins should be connected together. 3. All Input levels of LVDS signals are based on the EIA 644 Standard. 4. Specific pins(pin No. #2~#6) are used for internal data process of the LCD module. These pins should be no connection. 5. Specific pins(pin No. # 8~#10) are used for OPC function of the LCD module. If not used, these pins are no connection 6. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module. If used for 8Bit(R), these pins are no connection. 7. Specific pin No. #44 is used for “No signal detection” of system signal interface. It should be GND for NSB(No Signal Black) during the system interface signal is not. If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
Ver. 1.0 8 /38

LC320EUD
Product Specification
-LCD Connector : FI-RE41S-HF (manufactured by JAE) or KN25-41P-0.5SH (manufactured by Hirose) (CN2) - Mating Connector : FI-RE41HL Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
No
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Symbol
NC NC NC NC NC NC NC NC GND RA3N RA3P RB3N RB3P RC3N RC3P GND RCLK3N RCLK3P GND RD3N RD3P
Description
No connection(Reserved) No connection No connection No connection No connection No connection No connection No connection Ground THIRD LVDS Receiver Signal (A-) THIRD LVDS Receiver Signal (A+) THIRD LVDS Receiver Signal (B-) THIRD LVDS Receiver Signal (B+) THIRD LVDS Receiver Signal (C-) THIRD LVDS Receiver Signal (C+) Ground THIRD LVDS Receiver Clock Signal(-) THIRD LVDS Receiver Clock Signal(+) Ground THIRD LVDS Receiver Signal (D-) THIRD LVDS Receiver Signal (D+)
No
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 -
Symbol
RE3N RE3P GND GND RA4N RA4P RB4N RB4P RC4N RC4P GND RCLK4N RCLK4P GND RD4N RD4P RE4N RE4P GND GND
Description
THIRD LVDS Receiver Signal (E-) THIRD LVDS Receiver Signal (E+) Ground Ground FORTH LVDS Receiver Signal (A-) FORTH LVDS Receiver Signal (A+) FORTH LVDS Receiver Signal (B-) FORTH LVDS Receiver Signal (B+) FORTH LVDS Receiver Signal (C-) FORTH LVDS Receiver Signal (C+) Ground FORTH LVDS Receiver Clock Signal(-) FORTH LVDS Receiver Clock Signal(+) Ground FORTH LVDS Receiver Signal (D-) FORTH LVDS Receiver Signal (D+) FORTH LVDS Receiver Signal (E-) FORTH LVDS Receiver Signal (E+) Ground Ground
Note :
1. All GND(ground) pins should be connected together to the LCD module’s metal frame. 2. LVDS pin (pin No. #22,23,38,39) are used for 10Bit(D) of the LCD module. If used for 8Bit(R), these pins are no connection.
#1 #1
CN1
#51
#1
CN2
#41
CN1
#51
#1
CN2
#41
Rear view of LCM
Ver. 1.0 9 /38

LC320EUD
Product Specification
3-2-2. Backlight Module Master - LED Driver Connector : 20022WR-14B1(Yeonho) or Equivalent - Mating Connector : 20022HS-14 or Equivalent Table 5. LED DRIVER CONNECTOR PIN CONFIGURATION Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol
VBL VBL VBL VBL VBL GND GND GND GND GND NC VON/OFF EXTVBR-B GND
Description
Power Supply +24.0V Power Supply +24.0V Power Supply +24.0V Power Supply +24.0V Power Supply +24.0V Backlight Ground Backlight Ground Backlight Ground Backlight Ground Backlight Ground No connection Backlight ON/OFF control External PWM Backlight Ground
Master
VBL VBL VBL VBL VBL GND GND GND GND GND OPEN or GND VON/OFF EXTVBR-B GND
Note
1
2 3
Notes : 1. GND should be connected to the LCD module’s metal frame. 2. High : on duty / Low : off duty, Pin#13 can be opened. ( if Pin #13 is open , EXTVBR-B is 100% ) 3. #14 of Input CNT Must be Connected to Backlight Ground. 4. Each impedance of pin #12 and 13 is over 50 [K?] and over 50 [K?]. ◆ Rear view of LCM
PCB 14 … 1
10 /38
Ver. 1.0

LC320EUD
Product Specification 3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timings should be satisfied with the following specification for normal operation. Table 6-1. TIMING TABLE for NTSC (DE Only Mode)
ITEM Display Period Horizontal Blank Total Display Period Vertical Blank Total DCLK Frequency Horizontal Vertical Symbol tHV tHB tHP tVV tVB tVP fCLK fH fV Min 480 40 520 1080 16 1096 66.97 121.8 108 Typ 480 70 550 1080 45 1125 74.25 135 120 Max 480 200 680 1080 86 1166 78.00 140 122 Unit tCLK tCLK tCLK Lines Lines Lines MHz KHz Hz 2 2 1 Note 1920 / 4 1
Table 6-2 TIMING TABLE for DVB/PAL (DE Only Mode)
ITEM Display Period Horizontal Blank Total Display Period Vertical Blank Total DCLK Frequency Horizontal Vertical Symbol tHV tHB tHP tVV tVB tVP fCLK fH fV Min 480 40 520 1080 228 1308 66.97 121.8 95 Typ 480 70 550 1080 270 1350 74.25 135 100 Max 480 200 680 1080 300 1380 78.00 140 104 Unit tCLK tCLK tCLK Lines Lines Lines MHz KHz Hz 2 2 1 Note 1920 / 4 1
Note 1. The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode). If you use spread spectrum for EMI, add some additional clock to minimum value for clock margin. 2. The performance of the electro-optical characteristics may be influenced by variance of the vertical refresh rate and the horizontal frequency.
Ver. 1.0 11 /38

LC320EUD
Product Specification 3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
DE, Data
0.7VDD 0.3VDD
DCLK
tCLK
0.5 VDD
Valid data First data
Invalid data
Pixel 0
Pixel 4
Invalid data
Valid data Second data
Invalid data
Pixel 1
Pixel 5
Invalid data
Valid data Third data
Invalid data
Pixel 2
Pixel 6
Invalid data
Valid data Forth data
Invalid data
Pixel 3
Pixel 7
Invalid data
DE(Data Enable) * tHB = tHFP + tWH +tHBP * tVB = tVFP + tWV +tVBP
1
DE(Data Enable)
1080
tVV
tVP
Ver. 1.0
12 /38

LC320EUD
Product Specification
3-4-2. LVDS Input Signal Characteristics 1) DC Specification
LVDS -
LVDS
+
V CM # V CM = {( LVDS +) + ( LVDS - )} /2 0V
V IN _ MAX
V IN _ MIN
Description LVDS Common mode Voltage LVDS Input Voltage Range Change in common mode Voltage 2) AC Specification
Symbol VCM VIN ΔVCM
Min 1.0 0.7
Max 1.5 1.8 250
Unit V V mV
Note -
Tclk LVDS Clock
A
LVDS Data
tSKEW tSKEW
( F clk = 1/T clk )
A
Tclk
80%
LVDS 1’st Clock LVDS 2nd / 3rd / 4th Clock
20% tRF
tSKEW_min tSKEW_max
Description LVDS Differential Voltage High Threshold Low Threshold
Symbol VTH VTL tSKEW tRF teff
Min 100 -300
Max 300 -100 |(0.25*Tclk)/7|
Unit mV mV ps ps ps
Note 3 2 -
LVDS Clock to Data Skew Margin LVDS Clock/DATA Rising/Falling time Effective time of LVDS
260 ±360
(0.3*Tclk)/7 1/7* Tclk
LVDS Clock to Clock Skew Margin (Even to Odd) tSKEW_EO
Tclk
Note 1. All Input levels of LVDS signals are based on the EIA 644 Standard. 2. If tRF isn’t enough, teff should be meet the range. 3. LVDS Differential Voltage is defined within teff
Ver. 1.0 13 /38

LC320EUD
Product Specification
360ps 0.5tui V+ data tui
VTH Vcm VTL
Vdata
360ps teff
V+ clk
tui : Unit Interval
Vcm
Vclk
Ver. 1.0
14 /38

LC320EUD
Product Specification 3-5. Color Data Reference
The brightness of each primary color(red,green,blue) is based on the 10bit gray scale data input for the color. The higher binary input, the brighter the color. Table 7 provides a reference for color versus data input. Table 7. COLOR DATA REFERENCE
Input Color Data Color RED MSB LSB MSB GREEN LSB MSB BLUE LSB
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ... 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ... 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
Black Red (1023) Green (1023) Basic Color Blue (1023) Cyan Magenta Yellow White RED (0000) RED (0001) RED … RED (1022) RED (1023) GREEN (0000) GREEN (0001) GREEN ... GREEN (1022) GREEN (1023) BLUE (0000) BLUE (0001) BLUE … BLUE (1022) BLUE (1023)
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ... 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ver. 1.0
15 /38

LC320EUD
Product Specification
3-6. Power Sequence
3-6-1. LCD Driving circuit
90%
90% 10% T8 T2 30% T5 10%
Power Supply For LCD VLCD
0V
10% T1
Valid Data
Vcm : LVDS Common mode Voltage
Interface Signal (Tx_clock)
0V 100% T6 T3 T4
User Control Signal (LVDS_select, BIT _select, L-DIM Enable) Power for LED
T7
LED ON
Table 8. POWER SEQUENCE
Value Parameter Min T1 T2 T3 T4 T5 T6 T7 T8 0.5 0 200 200 1.0 0.5 100 Typ Max 20 T2 ms ms ms ms s ms s ms 6 4 3 3 5 4 Unit Notes
Note :1. Please avoid floating state of interface signal at invalid period. 2. When the power supply for LCD (VLCD) is off, be sure to pull down the valid and invalid data to 0V. 3. The T3 / T4 is recommended value, the case when failed to meet a minimum specification, abnormal display would be shown. There is no reliability problem. 4. If the on time of signals(Interface signal and user control signals) precedes the on time of Power(VLCD), it will be happened abnormal display. When T6 is NC status, T6 doesn’t need to be measured. 5. T5 should be measured after the Module has been fully discharged between power off and on period. 6. It is recommendation specification that T8 has to be 100ms as a minimum value.
Ver. 1.0 16 /38

LC320EUD
Product Specification
3-6-2. Sequence for LED Driver Power Supply For LED Driver
24V (typ.) 90% 90%
VBL
10% 0V
T1 VON/OFF
T2
T3
LED ON
Ext-VBR-B
T4 T5
3-6-3. Dip condition for LED Driver
T8 VBL : 24V
VBL(Typ.) x 0.8 0V
Table 9. Power Sequence for LED Driver
Values Min 20 500 10 0 0 Typ Max 10
Parameter T1 T2 T3 T4 T5 T6
Units ms ms ms ms ms ms
Remarks 1
VBL(Typ) x 0.8
Notes : 1. T1 describes rising time of 0V to 24V and this parameter does not applied at restarting time. Even though T1 is over the specified value, there is no problem if I2T spec of fuse is satisfied.
Ver. 1.0 17 /38

LC320EUD
Product Specification
4. Optical Specification
Optical characteristics are determined after the unit has been ‘ON’ and stable in a dark environment at 25±2°C. The values are specified at an approximate distance 50cm from the LCD surface at a viewing angle of Φ and θ equal to 0 °. It is presented additional information concerning the measurement equipment and method in FIG. 1. Optical Stage(x,y) LCD Module Pritchard 880 or equivalent
50cm FIG. 1 Optical Characteristic Measurement Equipment and Method
Ta= 25±2°C, VLCD=12.0V, fV=120Hz, Dclk=74.25MHz, EXTVBR-B =100% Value Min 900 360 5P Typ 1300 450 5 8 0.651 0.332 0.308 Typ -0.03 0.597 0.149 0.059 0.279 0.292 10,000 72 x axis, right(φ=0°) x axis, left (φ=180°) y axis, up (φ=90°) y axis, down (φ=270°) Gray Scale Ver. 1.0 θr θl θu θd 89 89 89 89 7 18 /38 degree 6 K % Typ +0.03 Max 1.3 8 12 1 1 ms ms cd/m2 Unit Note 1 2 3 4,5
Table 10. OPTICAL CHARACTERISTICS
Parameter Contrast Ratio Surface Luminance, white Luminance Variation Gray-to-Gray Response Time MPRT Uniformity Uniformity RED GREEN BLUE WHITE Color Temperature Color Gamut Viewing Angle (CR>10) Symbol CR LWH δ WHITE G to G MPRT δ MPRT δ G TO G Rx Ry Gx Gy Bx By Wx Wy
Color Coordinates [CIE1931]

LC320EUD
Product Specification
Note : 1. Contrast Ratio(CR) is defined mathematically as : Surface Luminance with all white pixels Surface Luminance with all black pixels It is measured at center 1-point. 2. Surface luminance are determined after the unit has been ‘ON’ and 1 Hour after lighting the backlight in a dark environment at 25±2°C. Surface luminance is the luminance value at center 1-point across the LCD surface 50cm from the surface with all pixels displaying white. For more information see the FIG. 2. Contrast Ratio = 3. The variation in surface luminance , δ WHITE is defined as : δ WHITE(5P) = Maximum(Lon1,Lon2, Lon3, Lon4, Lon5) / Minimum(Lon1,Lon2, Lon3, Lon4, Lon5) Where Lon1 to Lon5 are the luminance with all pixels displaying white at 5 locations . For more information, see the FIG. 2. 4. Response time is the time required for the display to transit from G(N) to G(M) (Rise Time, TrR) and from G(M) to G(N) (Decay Time, TrD). For additional information see the FIG. 3. (NGray Level L0 L15 L31 L47 L63 L79 L95 L111 L127 L143 L159 L175 L191 L207 L223 L239 L255 Ver. 1.0 Luminance [%] (Typ) 0.077 0.28 1.05 2.50 4.69 7.67 11.47 16.11 21.64 28.07 35.43 43.73 52.99 63.23 74.47 86.72 100 19 /38

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