BC41B143A蓝牙芯片datasheet

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm Device Features Fully Qualified Bluetooth v2.0+EDR system Enhanced Data Rate (EDR) compliant with v2.0 of

specification for both 2Mbps and 3Mbps modulation modes Full Speed Bluetooth Operation with Full Piconet Support Scatternet Support

1.8V core, 1.7 to 3.6V I/O Split Rails

Ultra Low Power Consumption

Excellent Compatibility with Cellular Telephones

Minimum External Components Required

Integrated 1.8V Regulator

USB and UART Port to 3Mbits/s

Support for 802.11 Co-existence

RoHS Compliant

Low Profile Package

Single Chip Bluetooth ? v2.0 + EDR System

Pre-Production Information Data Sheet for BC41B143A February 2007General Description Applications

The _?ìé`?êé?QJolj=r?íê~íüá?=ti`pm is a

single-chip radio and baseband IC for Bluetooth 2.4GHz systems including EDR to 3Mbps. Cellular Handsets

Personal Digital Assistants

Digital cameras and other high-volume consumer products

Space-critical applications

With the on-chip CSR Bluetooth software stack it provides a fully compliant Bluetooth system to v2.0+EDR of the specification for data and voice communications.System Architecture

BlueCore4-ROM Ultrathin WLCSP is designed to

reduce the number of external components required.

This ensures that production costs are minimised.

The device incorporates auto-calibration and built in

self test (BIST) routines to simplify development, type

approval and production test. All hardware and device firmware is fully compliant with the Bluetooth v2.0+EDR Specification (all mandatory and optional features).

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

Contents

1Key Features (8)

2Package Information (9)

2.1BlueCore4-ROM Ultrathin WLCSP (BC41B143A) Pinout Diagram (9)

2.2Device Terminal Functions (10)

3Electrical Characteristics (14)

3.1Absolute Maximum Ratings (14)

3.2Recommended Operating Conditions (14)

3.3Linear Regulator (15)

3.4Digital Terminals (16)

3.5USB Terminals (17)

3.6Power on Reset (17)

3.7Auxilliary ADC (17)

3.8Auxilliary DAC (18)

3.9Clocks (19)

3.10Power Consumption (20)

4Radio Characteristics - Basic Data Rate (21)

4.1Temperature +20°C (21)

4.1.1Transmitter (21)

4.1.2Receiver (23)

4.2Temperature -40°C (25)

4.2.1Transmitter (25)

4.2.2Receiver (25)

4.3Temperature -25°C (26)

4.3.1Transmitter (26)

4.3.2Receiver (26)

4.4Temperature +85°C (27)

4.4.1Transmitter (27)

4.4.2Receiver (27)

4.5Temperature +105°C (28)

4.5.1Transmitter (28)

4.5.2Receiver (28)

5Radio Characteristics - Enhanced Data Rate (29)

5.1Temperature +20°C (29)

5.1.1Transmitter (29)

5.1.2Receiver (30)

5.2Temperature -40°C (31)

5.2.1Transmitter (31)

5.2.2Receiver (32)

5.3Temperature -25°C (33)

5.3.1Transmitter (33)

5.3.2Receiver (34)

5.4Temperature +85°C (35)

5.4.1Transmitter (35)

5.4.2Receiver (36)

6Device Diagram (37)

7Description of Functional Blocks (38)

7.1RF Receiver (38)

7.1.1Low Noise Amplifier (38)

7.1.2Analogue to Digital Converter (38)

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

7.2RF Transmitter (38)

7.2.1IQ Modulator (38)

7.2.2Power Amplifier (38)

7.2.3Auxiliary DAC (38)

7.3RF Synthesiser (38)

7.4Power Control and Regulation (38)

7.5Clock Input and Generation (38)

7.6Baseband and Logic (39)

7.6.1Memory Management Unit (39)

7.6.2Burst Mode Controller (39)

7.6.3Physical Layer Hardware Engine DSP (39)

7.6.4System RAM (39)

7.6.5ROM (39)

7.6.6USB (39)

7.6.7Synchronous Serial Interface (39)

7.6.8UART (39)

7.6.9Audio PCM Interface (39)

7.7Microcontroller (40)

7.7.1Programmable I/O (40)

7.7.2802.11 Co-Existence Interface (40)

8CSR Bluetooth Software Stacks (41)

8.1BlueCore HCI Stack (41)

8.1.1Key Features of the HCI Stack: Standard Bluetooth Functionality (42)

8.1.2Key Features of the HCI Stack: Extra Functionality (43)

8.2BCHS Software (44)

8.3Additional Software for Other Embedded Applications (44)

8.4CSR Development Systems (44)

9Device Terminal Descriptions (45)

9.1RF Ports (45)

9.1.1RF_A and RF_B (45)

9.1.2Transmit RF Power Control for Class 1 Applications (TX_PWR) (46)

9.1.3Control of External RF Components (47)

9.2External Reference Clock Input (XTAL_IN) (47)

9.2.1External Mode (47)

9.2.2XTAL_IN Impedance in External Mode (47)

9.2.3Clock Timing Accuracy (48)

9.2.4Clock Start-Up Delay (49)

9.2.5Input Frequencies and PS Key Settings (50)

9.3Crystal Oscillator (XTAL_IN, XTAL_OUT) (50)

9.3.1XTAL Mode (50)

9.3.2Load Capacitance (52)

9.3.3Frequency Trim (53)

9.3.4Transconductance Driver Model (54)

9.3.5Negative Resistance Model (54)

9.3.6Crystal PS Key Settings (55)

9.3.7Crystal Oscillator Characteristics (55)

9.4UART Interface (57)

9.4.1UART Bypass (60)

9.4.2UART Configuration While RESET is Active (60)

9.4.3UART Bypass Mode (60)

9.4.4Current Consumption in UART Bypass Mode (60)

9.5USB Interface (60)

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

9.5.1USB Data Connections (61)

9.5.2USB Pull-Up Resistor (61)

9.5.3USB Power Supply (61)

9.5.4Self-Powered Mode (62)

9.5.5Bus-Powered Mode (62)

9.5.6Suspend Current (63)

9.5.7Detach and Wake_Up Signalling (63)

9.5.8USB Driver (64)

9.5.9USB 1.1 Compliance (64)

9.5.10USB 2.0 Compatibility (64)

9.6Serial Peripheral Interface (65)

9.6.1Instruction Cycle (65)

9.6.2Writing to the Device (66)

9.6.3Reading from the Device (66)

9.6.4Multi-Slave Operation (66)

9.7I/O Parallel Ports (67)

9.7.1PIO Defaults (67)

9.8I2C Master (67)

9.9TCXO Enable OR Function (68)

9.10RESETB (69)

9.10.1Pin States on Reset (70)

9.10.2Status after Reset (70)

9.11PCM CODEC Interface (71)

9.11.1PCM Interface Master/Slave (71)

9.11.2Long Frame Sync (72)

9.11.3Short Frame Sync (72)

9.11.4Multi-slot Operation (73)

9.11.5GCI Interface (73)

9.11.6Slots and Sample Formats (74)

9.11.7Additional Features (75)

9.11.8PCM Timing Information (76)

9.11.9PCM Configuration (79)

9.12Power Supply (81)

9.12.1Voltage Regulator (81)

9.12.2Sequencing (81)

9.12.3Sensitivity to Disturbances (81)

10Application Schematic (82)

11Package Dimensions (83)

12PCB Design and Assembly Considerations (84)

12.1 3.8 x 4.0 x 0.35mm Ultrathin WLCSP 47-Bump Package (84)

13Solder Profiles (85)

13.1Typical Solder Re-flow Profile for Devices with Lead-Free Solder Balls (85)

14RoHS Statement with a List of Banned Materials (86)

14.1RoHS Statement (86)

14.1.1List of Banned Materials (86)

15Ordering Information (87)

15.1BlueCore4-ROM Ultrathin WLCSP (87)

16Document References (88)

17Terms and Definitions (89)

18Document History (92)

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

List of Figures

Figure 2.1BlueCore4-ROM Ultrathin WLCSP Package (9)

Figure 6.1BlueCore4-ROM Ultrathin WLCSP Device Diagram (37)

Figure 8.1BlueCore HCI Stack (41)

Figure 9.1Circuit TX/RF_A and TX/RF_B (45)

Figure 9.2TCXO Clock Accuracy (48)

Figure 9.3Crystal Driver Circuit (51)

Figure 9.4Crystal Equivalent Circuit (51)

Figure 9.5Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency (55)

Figure 9.6Crystal Driver Transconductance vs. Driver Level Register Setting (56)

Figure 9.7Crystal Driver Negative Resistance as a Function of Drive Level Setting (57)

Figure 9.8Universal Asynchronous Receiver (58)

Figure 9.9Break Signal (58)

Figure 9.10UART Bypass Architecture (60)

Figure 9.11USB Connections for Self-Powered Mode (62)

Figure 9.12USB Connections for Bus-Powered Mode (63)

Figure 9.13USB_DETACH and USB_WAKE_UP Signal (64)

Figure 9.14SPI Write Operation (66)

Figure 9.15SPI Read Operation (66)

Figure 9.16Example EEPROM Connection (67)

Figure 9.17Example TCXO Enable OR Function (68)

Figure 9.18BlueCore4-ROM Ultrathin WLCSP as PCM Interface Master (71)

Figure 9.19BlueCore4-ROM Ultrathin WLCSP as PCM Interface Slave (72)

Figure 9.20Long Frame Sync (Shown with 8-bit Companded Sample) (72)

Figure 9.21Short Frame Sync (Shown with 16-bit Sample)..........................................................................73Figure 9.22Multi-slot Operation with Two Slots and 8-bit Companded Samples (73)

Figure 9.23GCI Interface (74)

Figure 9.2416-Bit Slot Length and Sample Formats (75)

Figure 9.25PCM Master Timing Long Frame Sync (77)

Figure 9.26PCM Master Timing Short Frame Sync (77)

Figure 9.27PCM Slave Timing Long Frame Sync (78)

Figure 9.28PCM Slave Timing Short Frame Sync (79)

Figure 10.1Application Circuit for Radio Characteristics Specification (82)

Figure 11.1BlueCore4-ROM Ultrathin WLCSP Package Dimensions (83)

Figure 13.1Typical Lead-Free Re-flow Solder Profile...................................................................................85List of Tables

Table 9.1TXRX_PIO_CONTROL Values (47)

Table 9.2External Clock Specifications (47)

Table 9.3PS Key Values for CDMA/3G Phone TCXO Frequencies (50)

Table 9.4Crystal Specification (52)

Table 9.5Possible UART Settings (58)

Table 9.6Standard Data Rates (59)

Table 9.7USB Interface Component Values (62)

Table 9.8Instruction Cycle for an SPI Transaction (65)

Table 9.9Pin States of BlueCore4-ROM Ultrathin WLCSP on Reset (70)

Table 9.10PCM Master Timing (76)

Table 9.11PCM Slave Timing (78)

Table 9.12PSKEY_PCM_CONFIG32 Description (81)

Table 9.13PSKEY_PCM_LOW_JITTER_CONFIG Description (81)

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

List of Equations

Equation 9.1Output Voltage with Load Current ≤ 10mA (46)

Equation 9.2Output Voltage with No Load Current (46)

Equation 9.3Internal Power Ramping (46)

Equation 9.4Load Capacitance (52)

Equation 9.5Trim Capacitance (53)

Equation 9.6Frequency Trim (53)

Equation 9.7Pullability (53)

Equation 9.8Transconductance Required for Oscillation (54)

Equation 9.9Equivalent Negative Resistance (54)

Equation 9.10Data Rate (59)

Equation 9.11PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock (79)

Equation 9.12PCM_SYNC Frequency Relative to PCM_CLK (79)

Status Information

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

Status Information

The status of this Data Sheet is Pre-Production Information .

CSR Product Data Sheets progress according to the following format:

Advance Information

Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values.

All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.Pre-Production Information

Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values.

All electrical specifications may be changed by CSR without notice.

Production Information

Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.

Production Data Sheets supersede all previous document versions.

Life Support Policy and Use in Safety-Critical Applications

CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.

Trademarks, Patents and Licenses

Unless otherwise stated, words and logos marked with ? or ? are trademarks registered or owned by CSR plc or its affiliates. Bluetooth ? and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have been trademarked by their respective owners.

The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc.

CSR reserves the right to make technical changes to its products as part of its development programme.

While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors.

Key Features

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

1Key Features

Radio Common TX/RX terminals simplify external matching and eliminates external antenna switch BIST minimises production test time. No external trimming is required in production Full RF reference designs are available Bluetooth v2.0+EDR specification compliant Transmitter +6dBm RF transmit power with level control from on-chip 6-bit DAC over a dynamic range >30dB Class 2 and Class 3 support without the need for an external power amplifier or TX/RX switch Class1 support using external power amplifier with RF power controlled by an internal 8-bit DAC Supports DQPSK (2Mbps) and 8DPSK (3Mbps) modulation Receiver Integrated channel filters Digital demodulator for improved sensitivity and

co-channel rejection Real-time digitised RSSI available on HCI interface Fast AGC for enhanced dynamic range Supports DQPSK and 8DPSK modulation Channel classification Synthesiser Fully integrated synthesiser requires no external VCO varactor diode, resonator or loop filter Compatible with crystals between 8 and 40MHz (in multiples of 250kHz) or an external clock Accepts 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44,

19.68, 19.8 and 38.4MHz TCXO frequencies for GSM and CDMA devices with sinusoidal or logic level signals Auxiliary Features Crystal oscillator with built-in digital trimming Power management includes digital shutdown, and wake up commands with an integrated low-power oscillator for ultra low Park/Sniff/Hold mode

Clock request output to control external clock

Auxilliary Features (Continued)

Device can run in low power modes from an external

32kHz clock signal

Auto Baud Rate setting for different TCXO

frequencies

On-chip linear regulator, producing 1.8V output from 2.2-5.6V input

Power-on-reset cell detects low supply voltage Baseband and Software

Internal 48-KByte RAM, allows full-speed data

transfer, mixed voice and data, and full piconet

operation, including all medium rate preset types Logic for forward error correction, header error

control, access code correlation, CRC, demodulation, encryption bit stream generation, whitening and

transmit pulse shaping. Supports all Bluetooth v2.0 +

EDR features including eSCO and AFH

Transcoders for A-law, μ-law and linear voice from host and A-law, μ-law and CVSD voice over air Physical Interfaces

Synchronous serial interface up to 4Mbit/s for system debugging

UART interface with programmable baud rate up to

3Mbits/s with an optional bypass mode Full-speed USB v2.0 interface supports OHCI and UHCI host interfaces

Synchronous bi-directional serial programmable

audio interface

Optional I 2C? compatible interface

Optional 802.11 co-existence interfaces

Bluetooth Stack

CSR's Bluetooth Protocol Stack runs on the on-chip MCU in a variety of configurations:

Standard HCI (UART or USB)

Customised builds with embedded application code Package Options

47-Bump WLCSP 3.8 x 4.0 x 0.35mm

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

2Package Information

2.1BlueCore4-ROM Ultrathin WLCSP (BC41B143A) Pinout Diagram

Figure 2.1: BlueCore4-ROM Ultrathin WLCSP Package

A B C D E F G 1234567

A2A3A4A5A6A7

B1B2B3B4B5B6B7

C1C2C3C4C5C6C7

D2D3E1E2E3F1F2F3G1G2G3D5D6D7

E5E6E7

F5F6F7

G5G6G7

D4E4F4G4Orientation from top of device

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2.2Device Terminal Functions

Radio Bump Pad Type Description

RF_A E2Analogue Transmitter output/switched

receiver input

RF_B E1Analogue Complement of RF_A

AUX_DAC D2Analogue Voltage DAC

Synthesiser and Oscillator Bump Pad Type Description

XTAL_IN A3Analogue For crystal or external clock input XTAL_OUT B3Analogue Drive for crystal

PCM Interface Bump Pad Type Description

PCM_OUT E4CMOS output, tri-state, with weak

internal pull-down Synchronous data output

PCM_IN B7CMOS input, with weak internal

pull-down Synchronous data input

PCM_SYNC D5Bi-directional with weak internal

pull-down Synchronous data sync

PCM_CLK B6Bi-directional with weak internal

pull-down Synchronous data clock

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

USB and UART Bump Pad Type Description

UART_TX C5CMOS output, tri-statable with

weak internal pull-up UART data output active high

UART_RX D4CMOS input with weak internal

pull-down UART data input active high

UART_RTS A7CMOS output, tri-statable with

weak internal pull-up UART request to send active low

UART_CTS C4CMOS input with weak internal

pull-down USB clear to send active low

USB_DP B5Bi-directional USB data plus with selectable

internal 1.5? pull-up resistor

USB_DN A6Bi-directional USB data minus

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

PIO Port Bump Pad Type Description

PIO[0]F3Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[1]F4Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[2]G1Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[3]G2Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[4]E6Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[5]F5Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[6]D7Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[7]E5Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[8]E3Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[9]F1Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

PIO[10]F2Bi-directional with programmable

strength internal pull-up/down Programmable input/output line

AIO[0]D3Bi-directional Programmable input/output line AIO[2]C3Bi-directional Programmable input/output line

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet Power Supplies and

Control Bump Pad Type Description

VREG_IN A2Regulator input Regulator input

VDD_USB A5VDD Positive supply for UART ports and AIOs VDD_PIO G4VDD Positive supply for PIO [3:0] and [10:8] VDD_PADS D6VDD Positive supply for all digital Input/Output

ports and PIO[7:4]

VDD_CORE C6VDD Positive supply for internal digital

circuitry

VDD_LO B2VDD Positive supply for VCO and synthesiser

circuitry

VDD_RADIO C2VDD Positive supply for RF circuitry

VDD_ANA A4VDD/Regulator output Positive supply for analogue circuitry

and 1.8V regulated output

VSS_DIG C7VSS Ground connection for internal digital

circuitry and digital ports

VSS_PADS G3VSS Ground connection for digital ports VSS_RADIO C1VSS Ground connections for RF circuitry VSS_ANA B4VSS Ground connections for analogue

circuitry

VSS_LO B1VSS Ground connection for VCO and

synthesiser circuitry

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

3Electrical Characteristics

3.1Absolute Maximum Ratings

3.2Recommended Operating Conditions

(a)Typical figures are given for RF performance between -40°C and +105°C (b)The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is not guaranteed

above 4.2V

Rating Min Max

Storage Temperature -40°C +150°C

Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA and

VDD_CORE -0.4V 2.2V

Supply Voltage: VDD_PADS, VDD_PIO and VDD_USB -0.4V 3.7V

Supply Voltage: VREG_IN -0.4V 5.6V

Other Terminal Voltages VSS-0.4V VDD+0.4V

Operating Condition Min Max

Operating Temperature Range -40°C +105°C

Guaranteed RF performance range (a) -40°C +85°C

Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA and

VDD_CORE 1.7V 1.9V

Supply Voltage: VDD_PADS, VDD_PIO and VDD_USB 1.7V 3.6V

Supply Voltage: VREG_IN 2.2V 4.2V (b)

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

3.3Linear Regulator

(a)Regulator output connected to 47nF pure and 4.7μF 2.2? ESR capacitors

(b)Frequency range is 100Hz to 100kHz (c)1mA to 70mA pulsed load (d)Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to damage the rest

of BlueCore4-ROM Ultrathin WLCSP , but output regulation and other specifications are no longer guaranteed at input

voltages in excess of 4.2V

(e)Low power mode is entered and exited automatically when the chip enters/leaves Deep Sleep mode

(f)Regulator is disabled when VREG_IN is either open circuit or driven to the same voltage as VDD_ANA Linear Regulator Min Typ Max Unit Normal Operation

Output voltage (I load = 70 mA / VREG_IN = 3.0V)) 1.70 1.78 1.85V Temperature coefficient -250-250ppm/°C Output noise (a) (b) --1mV rms Load regulation (I load < 70 mA)--50mV/A Settling Time (a) (c) --50μs Maximum output current 70--mA Minimum load current 5--μA Input voltage -- 4.2(d) V Dropout voltage (I load = 70 mA)--350mV Quiescent current (excluding Ioad, I load < 1mA)253550μA Low Power Mode (e)

Quiescent current (excluding Ioad, I load < 100μA)4710μA Disabled Mode (f)

Quiescent Current 1.5 2.5 3.5μA

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

3.4Digital Terminals

(a)Current sunk into terminal

(b)Current sourced out of terminal

Digital Terminals Min Typ Max Unit Input Voltage Levels

V IL input logic level low 2.7V ≤ VDD ≤ 3.0V -0.4-+0.8V 1.7V ≤ VDD ≤ 1.9V -0.4-+0.4V V IH input logic level high 0.7VDD -VDD+0.4V Output Voltage Levels

V OL output logic level low,

--0.2V (l o = 4.0mA)(a) , 2.7V ≤ VDD ≤ 3.0V

V OL output logic level low,

--0.4V (l o = 4.0mA)(a) , 1.7V ≤ VDD ≤ 1.9V

V OH output logic level high,

VDD-0.2--V (l o = -4.0mA)(b) , 2.7V ≤ VDD ≤ 3.0V

V OH output logic level high,

VDD-0.4--V (l o = -4.0mA)(b) , 1.7V ≤ VDD ≤ 1.9V

Input and Tri-state Current with:

Strong pull-up -100-40-10μA Strong pull-down 1040100μA Weak pull-up -5.0-1.0-0.2μA

Weak pull-down 0.2 1.0 5.0μA I/O pad leakage current -10+1μA C I input capacitance 1.0- 5.0pF

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

3.5USB Terminals

(a)Internal USB pull-up disabled

3.6Power on Reset

3.7Auxilliary ADC

(a)ADC is accessed through the VM function. The sample rate given is achieved as part of this function

USB Terminals Min Typ Max Unit VDD_USB for correct USB operation 3.1 3.6V Input Threshold

V IL input logic level low --0.3VDD_USB V V IH input logic level high 0.7VDD_USB --V Input Leakage Current

VSS_PADS < VIN < VDD_USB (a) -115μA C I Input capacitance 2.5-10.0pF Output Voltage Levels to Correctly Terminated

USB Cable

V OL output logic level low 0.0-0.2V V OH output logic level high 2.8-VDD_USB V

Power-on Reset Min Typ Max Unit VDD_CORE falling threshold 1.40 1.50 1.60V VDD_CORE rising threshold 1.50 1.60 1.70V

Hysteresis 0.050.100.15V

Auxiliary ADC Min Typ Max Unit Resolution --8Bits Input voltage range

0-VDD_ANA V (LSB size = VDD_ANA/255)Accuracy INL -1-1LSB (Guaranteed monotonic)DNL 0-1LSB Offset -1-1LSB Gain Error -0.8-0.8%Input Bandwidth -100-kHz Conversion time - 2.5-μs Sample rate (a) --700Samples/s

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

3.8Auxilliary DAC

(a)Specified for an output voltage between 0.2V and VDD_PIO -0.2V. Output is high impedance when chip is in Deep Sleep

mode Auxiliary DAC Min Typ Max Unit Resolution --8Bits Average output step size (a) 12.514.517.0mV Output Voltage monotonic (a)

Voltage range (I O =0mA)VSS_PADS -VDD_PIO V Current range -10.0-0.1mA Minimum output voltage (I O =100μA)0.0-0.2V Maximum output voltage (I O =10mA)VDD_PIO-0.3-VDD_PIO V High Impedance leakage current -1-1μA Offset -220-120mV Integral non-linearity (a) -2-2LSB Settling time (50pF load)--10μs

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet

3.9Clocks

(a)Integer multiple of 250kHz (b)The difference between the internal capacitance at minimum and maximum settings of the internal digital trim.

(c)XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF.

(d)Clock input can be any frequency between 8MHz and 40MHz in steps of 250kHz plus CDMA/3G TCXO frequencies of

7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz.

(e)Clock input can be either sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA.

A DC blocking capacitor is required between the signal and XTAL_IN.

Notes:VDD_CORE, VDD_RADIO, VDD_LO and VDD_ANA are at 1.8V unless shown otherwise.

VDD_PADS, VDD_PIO and VDD_USB are at 3.15V unless shown otherwise.

The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT.

Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.Crystal Oscillator Min Typ Max Unit Crystal frequency (a) 8.0-40.0MHz Digital trim range (b) 5.0 6.28.0pF Trim step size (b) -0.1-pF Transconductance 2.0--mS Negative resistance (c) 87015002400?External Clock

Input frequency (d) 8.0-40.0MHz Clock input level (e) 0.4-VDD_ANA V pk-pk Allowable Jitter --15ps rms XTAL_IN input impedance -≥10-k ?XTAL_IN input capacitance - ≤ 4-pF

_?ìé`?êé?QJolj=r?íê~íüá?=ti`pm= Product Data Sheet 3.10Power Consumption

(a)Low power mode on the linear regulator is entered and exited automatically when the chip enters/leaves Deep Sleep

mode. For more information about the electrical characteristics of the linear regulator, see section 3.3 in this document.

Note:

Conditions: 20°C, VREG_IN 3.15V linear regulator supplying 1.8V

Operation Mode Connection Type UART Rate (kbps)Average Unit

Page scan, time

interval 1.28s -115.20.41mA

Inquiry and page scan -115.20.77mA

ACL No traffic Master 115.2 6.4mA

ACL With file transfer Master 115.211mA

ACL No traffic Slave 115.214mA

ACL With file transfer Slave 115.217mA

ACL 40ms sniff Master 38.4 1.5mA

ACL 1.28s sniff Master 38.40.19mA

SCO HV1Master 38.434mA

SCO HV3Master 38.417mA

SCO HV3 30ms sniff Master 38.417mA

ACL 40ms sniff Slave 38.4 1.5mA

ACL 1.28s sniff Slave 38.40.24mA

Parked 1.28s beacon Slave 38.40.18mA

SCO HV1Slave 38.434mA

SCO HV3Slave 38.421mA

SCO HV3 30ms sniff Slave 38.417mA

Standby Host

connection -38.40.03mA

(Deep Sleep)(a)

Reset (RESETB low)(a) --0.04mA