EDA实验代码

EDA实验代码实验一：

一位全加器：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY adder1 IS

PORT(A,B,C:IN STD_LOGIC;

COUT,SUM:OUT STD_LOGIC);

END ENTITY adder1;

ARCHITECTURE hl OF adder1 IS

SIGNAL ABC:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN

ABC<=A&B&C;

PROCESS(ABC)

BEGIN

CASE ABC IS

WHEN"000"=>COUT<='0';SUM<='0'; WHEN"001"=>COUT<='0';SUM<='1'; WHEN"010"=>COUT<='0';SUM<='1'; WHEN"011"=>COUT<='1';SUM<='0'; WHEN"100"=>COUT<='0';SUM<='1'; WHEN"101"=>COUT<='1';SUM<='0';

WHEN"110"=>COUT<='1';SUM<='0'; WHEN"111"=>COUT<='1';SUM<='1';

WHEN OTHERS=>NULL;

END CASE;

END PROCESS;

END ARCHITECTURE hl;

四位全加器（需要调用）

LIBRARY IEEE ;

USE IEEE.STD_LOGIC_1164.ALL ;

ENTITY adder4 IS

PORT (Ain, Bin: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ) ; END ENTITY adder4;

ARCHITECTURE hl4 OF adder4 IS

COMPONENT adder1

PORT (A, B, C: IN STD_LOGIC;

SUM,COUT: OUT STD_LOGIC ) ;

END COMPONENT;

SIGNAL net1,net2,net3:STD_LOGIC;

BEGIN

u1: adder1 PORT

MAP(A=>Ain(0),B=>Bin(0),C=>'0',SUM=>DOUT(0),COUT=>net1);

u2: adder1 PORT

MAP(A=>Ain(1),B=>Bin(1),C=>net1,SUM=>DOUT(1),COUT=>net2);

u3: adder1 PORT

MAP(A=>Ain(2),B=>Bin(2),C=>net2,SUM=>DOUT(2),COUT=>net3);

u4: adder1 PORT

MAP(A=>Ain(3),B=>Bin(3),C=>net3,SUM=>DOUT(3),COUT=>DOUT(4)); END ARCHITECTURE hl4;

实验二

LIBRARY IEEE ;

USE IEEE.STD_LOGIC_1164.ALL ;

USE IEEE.STD_LOGIC_UNSIGNED.ALL ;

USE IEEE.STD_LOGIC_ARITH.ALL ;

ENTITY LED IS

GENERIC ( T : INTEGER := 50000000);

PORT (CLK : IN STD_LOGIC ; Hz1 : OUT STD_LOGIC) ;

END ;

ARCHITECTURE bhv_HL OF LED IS

SIGNAL Q : INTEGER RANGE 0 TO T-1;

SIGNAL M : STD_LOGIC ;

BEGIN

PROCESS (CLK,Q) BEGIN

IF FALLING_EDGE(CLK) THEN

IF (Q=0) THEN Q<=T-1; ELSE Q<=Q-1; END IF;

IF (Q=0) THEN M<=NOT M; ELSIF (Q=T/2) THEN M<=NOT M;

END IF; E ND IF;

END PROCESS;

Hz1<=M;

END bhv_HL;

实验三

LIBRARY IEEE ;

USE IEEE.STD_LOGIC_1164.ALL ;

USE IEEE.STD_LOGIC_UNSIGNED.ALL ;

USE IEEE.STD_LOGIC_ARITH.ALL ;

ENTITY SEG7 IS

PORT ( CLK : IN STD_LOGIC ;

K_AND : OUT INTEGER RANGE 31 DOWNTO 0 ;

K1,K2 : OUT INTEGER RANGE 15 DOWNTO 0 ;

LED7S01,LED7S10:OUT STD_LOGIC_VECTOR(0 TO 6));

ARCHITECTURE bhv_HL OF SEG7 IS

SIGNAL Q1 : INTEGER RANGE 15 DOWNTO 0 ;

SIGNAL Q2 : INTEGER RANGE 15 DOWNTO 0 ;

SIGNAL Q3 : INTEGER RANGE 31 DOWNTO 0 ;

SIGNAL DEC10,DEC01 : INTEGER RANGE 0 TO 9; BEGIN

PROCESS(CLK)

BEGIN

IF RISING_EDGE(CLK) THEN Q1 <= Q1 + 1 ; END IF; END PROCESS ;

PROCESS(CLK) BEGIN

IF FALLING_EDGE(CLK) THEN Q2 <= Q2 + 1 ; END IF; END PROCESS ;

Q3 <= Q1+Q2 ;

PROCESS (Q3)

VARIABLE DD01 : INTEGER RANGE 0 TO 31; VARIABLE DD10 : INTEGER RANGE 31 DOWNTO 0;

CASE Q3 IS

WHEN 0 TO 9 => DEC10<= 0; DEC01<= Q3;

WHEN 10 TO 19 => DEC10<= 1; DEC01<= Q3 - 10;

WHEN 20 TO 29 => DEC10<= 2; DEC01<= Q3 - 20;

WHEN 30 TO 31 => DEC10<= 3; DEC01<= Q3 - 30; END CASE ;

END PROCESS;

PROCESS(DEC10,DEC01) BEGIN

CASE DEC01 IS

WHEN 0 => LED7S01 <="1000000";

WHEN 1 => LED7S01 <="1111001";

WHEN 2 => LED7S01 <="0100100";

WHEN 3 => LED7S01 <="0110000";

WHEN 4 => LED7S01 <="0011001";

WHEN 5 => LED7S01<="0010010";

WHEN 6 => LED7S01<="0000010";

WHEN 7 => LED7S01<="1111000";

WHEN 8 => LED7S01<="0000000";

WHEN 9 => LED7S01<="0010000";

WHEN OTHERS => NULL;

END CASE;

CASE DEC10 IS

WHEN 0 => LED7S10 <="1000000";

WHEN 1 => LED7S10 <="1111001";

WHEN 2 => LED7S10 <="0100100";

WHEN 3 => LED7S10<="0110000";

WHEN 4 => LED7S10<="0011001";

WHEN 5 => LED7S10<="0010010";

WHEN 6 => LED7S10<="0000010";

WHEN 7 => LED7S10<="1111000";

WHEN 8 => LED7S10<="0000000";

WHEN 9 => LED7S10<="0010000";

WHEN OTHERS => NULL;

END CASE;

END PROCESS;

END bhv_HL ;

实验四

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY text4 IS

GENERIC( nstep : INTEGER :=4);

PORT( CLK,LOAD:IN STD_LOGIC;

QB :OUT STD_LOGIC;

DIN :IN STD_LOGIC_VECTOR(7 DOWNTO 0);

DOUT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END text4;

ARCHITECTURE behav OF text4 IS

--SIGNAL REG8 :STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

PROCESS (CLK,LOAD)

VARIABLE FLAG :STD_LOGIC;

VARIABLE REG8 :STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

IF CLK'EVENT AND CLK = '1' THEN

IF LOAD = '1' THEN REG8 := DIN;

ELSE

FOR N IN 0 TO nstep LOOP

FLAG := REG8(0);

REG8(6 DOWNTO 0) :=REG8(7 DOWNTO 1);

REG8(7) :=FLAG;

END LOOP;

--IF LOAD = '1' THEN REG8 <= DIN;

-- ELSE REG8(6 DOWNTO 0) <=REG8(7 DOWNTO 1);

END IF;

END IF;

QB <=REG8(0);

DOUT <=REG8;

END PROCESS;

END behav;

实验五

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY text5 IS

PORT(

CLK: IN STD_LOGIC;

DOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END text5;

ARCHITECTURE BEHAV OF text5 IS

TYPE states IS(ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7,ST8,ST9);

SIGNAL PST : states;

BEGIN

REGCOM:PROCESS(PST,CLK)

BEGIN

IF RISING_EDGE(CLK) THEN

CASE PST IS

WHEN ST0=> PST<=ST1;

WHEN ST1=> PST<=ST2;

WHEN ST2=> PST<=ST3;

WHEN ST3=> PST<=ST4;

WHEN ST4=> PST<=ST5;

WHEN ST5=> PST<=ST6;

WHEN ST6=> PST<=ST7;

WHEN ST7=> PST<=ST8;

WHEN ST8=> PST<=ST9;

WHEN ST9=> PST<=ST0;

WHEN OTHERS => PST<=ST0;

END CASE;

END IF;

END PROCESS REGCOM;

COM: PROCESS(PST)

BEGIN

CASE PST IS

WHEN ST0=> DOUT<="0000";

WHEN ST1=> DOUT<="0001";

WHEN ST2=> DOUT<="0010";

WHEN ST3=> DOUT<="0011";

WHEN ST4=> DOUT<="0100";

WHEN ST5=> DOUT<="0101";

WHEN ST6=> DOUT<="0110";

WHEN ST7=> DOUT<="0111";

WHEN ST8=> DOUT<="1000";

WHEN ST9=> DOUT<="1001";

WHEN OTHERS => DOUT<="0000";

END CASE;

END PROCESS COM;

END;

实验六基于状态机实现交通灯设计

一、实验目的

1、掌握状态转移图的绘制；

2、掌握状态转移图到VHDL代码的设计实现方法；

二、实验参考资料

教材《VHDL与EDA实用技术（第五版）》潘松黄继业

PDF文件《使用QUARTUS_II做FPGA开发全流程_傻瓜式详细教程》PDF文件《Quartus 与ModelSim-Altera 的使用》

PDF文件《DE2中文用户手册》

引脚参考文件DE2_pin_assignments.csv

三、实验描述

1、步骤：

（a）依据示意图（左图）绘制状态机状态图（类似于右图）；

（b）配置状态转移条件以及状态输出；（c）依据状态图生成VHDL代码；

（d）配置引脚，下载至DE2，验证效果。

“01”

out_a <= “0101“1000”;

;

out_a <= “1101