STD1NK80Z中文资料

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January 2006

STQ1NK80ZR-AP - STN1NK80Z

STD1NK80Z - STD1NK80Z-1

N-CHANNEL 800V - 13 ? - 1 A TO-92 /SOT-223/DPAK/IPAK

Zener - Protected SuperMESH? MOSFET

Table 1: General Features

■TYPICAL R DS (on) = 13?

■EXTREMELY HIGH dv/dt CAPABILITY ■ESD IMPROVED CAPABILITY ■100% AVALANCHE TESTED

■NEW HIGH VOLTAGE BENCHMARK ■

GATE CHARGE MINIMIZED

DESCRIPTION

The SuperMESH? series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH? layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOS-FETs including revolutionary MDmesh? products.

APPLICATIONS

■AC ADAPTORS AND BATTERY CHARGERS ■SWITH MODE POWER SUPPLIES (SMPS)

Table 2: Order Codes

Figure 2: Internal Schematic Diagram

TYPE V DSS R DS(on)I D Pw STQ1NK80ZR-AP STN1NK80Z STD1NK80Z STD1NK80Z-1

800 V 800 V 800 V 800 V

< 16 ?< 16 ?< 16 ?< 16 ?

0.3 A 0.25A 1.0 A 1.0 A

3 W 2.5 W 45 W 45 W

TO-92 (Ammopack)

3DPAK

SALES TYPE MARKING PACKAGE PACKAGING STQ1NK80ZR-AP Q1NK80ZR TO-92AMMOPAK STN1NK80Z N1NK80Z SOT-223TAPE & REEL STD1NK80ZT4D1NK80Z DPAK TAPE & REEL

STD1NK80Z-1

D1NK80Z

IPAK

TUBE Rev. 3

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Table 3: Absolute Maximum ratings

( ) Pulse width limited by safe operating area (1) I SD ≤ 1 A, di/dt ≤ 200 A/μs, V DD ≤ 640

Table 4: Thermal Data

(#) When mounted on 1inch2 FR-4 BOARD, 2 oz Cu

Table 5: Avalanche Characteristics

Table 6: GATE-SOURCE ZENER DIODE

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.

Symbol Parameter

Value Unit

TO-92

SOT-223DPAK/IPAK

V DS Drain-source Voltage (V GS = 0)800V V DGR Drain-gate Voltage (R GS = 20 k ?)800V V GS Gate- source Voltage

± 30V I D Drain Current (continuous) at T C = 25°C 0.30.25 1.0A I D Drain Current (continuous) at T C = 100°C 0.19

0.160.63A I DM ( )Drain Current (pulsed)5A P TOT Total Dissipation at T C = 25°C 3 2.545W Derating Factor

0.0250.020.36W /°C V ESD(G-S)Gate source ESD (HBM-C= 100pF, R= 1.5K ?)1000V dv/dt (1)Peak Diode Recovery voltage slope 4.5V/ns T j T stg

Operating Junction Temperature Storage Temperature

-55 to 150

°C TO-92

SOT-223

DPAK/IPAK

Unit Rthj-case Thermal Resistance Junction-case Max ---- 2.78°C/W Rthj-amb(#)Thermal Resistance Junction-ambient Max 12050100°C/W Rthj-lead

Thermal Resistance Junction-lead Max 40----°C/W T l

Maximum Lead Temperature For Soldering Purpose

260

--300

°C

Symbol Parameter

Max Value

Unit I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max)

1A E AS

Single Pulse Avalanche Energy

(starting T j = 25 °C, I D = I AR , V DD = 50 V)

Symbol Parameter

Test Conditions

Min.Typ.

Max.

Unit BV GSO

Gate-Source Breakdown Voltage Igs=± 1mA (Open Drain)

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ELECTRICAL CHARACTERISTICS (T CASE =25°C UNLESS OTHERWISE SPECIFIED)Table 7: On/Off

Table 8: Dynamic

Table 9: Source Drain Diode

Note: 1.Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %.

2.Pulse width limited by safe operating area.

3.C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS

Symbol Parameter

Test Conditions

Min.Typ.

Max.

Unit V (BR)DSS Drain-source

Breakdown Voltage I D = 1 mA, V GS = 0

800

V I DSS Zero Gate Voltage

Drain Current (V GS = 0)V DS = Max Rating

V DS = Max Rating, T C = 125 °C 150μA μA I GSS Gate-body Leakage Current (V DS = 0)V GS = ± 20V

±10μA V GS(th)Gate Threshold Voltage V DS = V GS , I D = 50 μA 3

3.75

4.5V R DS(on)

Static Drain-source On Resistance

V GS = 10V, I D = 0.5 A

Symbol Parameter

Test Conditions

Min.

Typ.Max.

Unit g fs (1)Forward Transconductance V DS = 15 V , I D = 0.5 A

0.8S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V , f = 1 MHz, V GS = 0

160266.7pF pF pF C oss eq. (3)Equivalent Output Capacitance V GS = 0V, V DS = 0V to 640V 9.5pF t d(on)t r t d(off)t f Turn-on Delay Time Rise Time

Turn-off Delay Time Fall Time

V DD = 400 V, I D = 0.5 A R G = 4.7? V GS = 10 V (see Figure 21)8302255ns ns ns ns Q g Q gs Q gd

Total Gate Charge Gate-Source Charge Gate-Drain Charge

V DD = 640V, I D = 1.0 A,V GS = 10V

(see Figure 24)

7.71.44.5

nC nC nC

Symbol Parameter

Test Conditions

Min.

Typ.

Max.Unit I SD I SDM (2)Source-drain Current

Source-drain Current (pulsed) 1.05A A V SD (1)Forward On Voltage I SD = 1.0 A, V GS = 0 1.6

V t rr Q rr I RRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 1.0 A, di/dt = 100 A/μs V DD = 50 V, T j = 25°C (see Figure 22)

3658024.4ns nC A t rr Q rr I RRM

Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current

I SD = 1.0 A, di/dt = 100 A/μs V DD = 50 V, T j = 150°C (see Figure 22)

388802.74.6

ns nC A

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Figure 3: Safe Operating Area for SOT-223

Figure 6: Thermal Impedance for SOT-223

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Figure 9: Output Characteristics

Figure 12: Transfer Characteristics

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Figure 15: Normalized Gate Thereshold Volt-

Figure 18: Normalized On Resistance vs Tem-

STQ1NK80ZR-AP - STN1NK80Z - STD1NK80Z - STD1NK80Z-1

Figure 20: Unclamped Inductive Load Test Cir-cuit

Figure 21: Switching Times Test Circuit For Resistive Load Figure 22: Test Circuit For Inductive Load Switching and Diode Recovery Times

Figure 23: Unclamped Inductive Wafeform

Figure 24: Gate Charge Test Circuit

STQ1NK80ZR-AP - STN1NK80Z - STD1NK80Z - STD1NK80Z-1

In order to meet environmental requirements, ST offers these devices in ECOPACK? packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: https://www.360docs.net/doc/df3744564.html,

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TAPE AND REEL SHIPMENT

DPAK FOOTPRINT

DIM.mm inch MIN.

MAX.MIN.

MAX.A 330

12.992

B 1.50.059

C 12.813.20.5040.520

D 20.20.795G 16.418.40.6450.724N 50

1.968

22.40.881

BASE QTY BULK QTY 2500

2500REEL MECHANICAL DATA

DIM.mm inch MIN.MAX.MIN.

MAX.

A0 6.87

0.2670.275B010.410.60.4090.417

B112.10.476

D 1.5 1.60.0590.063D1 1.50.059

E 1.65 1.850.0650.073

F 7.47.60.2910.299K0 2.55 2.750.1000.108P0 3.9 4.10.1530.161P17.98.10.3110.319P2 1.9 2.1

0.0750.082R 40 1.574W

15.7

16.3

0.618

0.641

TAPE MECHANICAL DATA

All dimensions are in millimeters

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Table 10: Revision History

Date Revision Description of Changes 08-Jun-20051First Release

06-Sep-20052Inserted Ecopack indication

16-Jan-20063Corrected value on Table 3

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STQ1NK80ZR-AP - STN1NK80Z - STD1NK80Z - STD1NK80Z-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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