MSP430_OVERVIEW_CONFIGURAT

HeCh / 02-99/ 3-1

Ultra-low power design with

M S P 4 3 0 D E S I G N S E M I N A R

? Low-Power Concept ? MSP430 Features ? Overview Configurations ? Basic Architecture ? Modules

? Application Examples ? Communication Support ? Development Tools

? Documentation and Support

Agenda

HeCh / 02-99/ 3-2

Ultra-low power design with

M S P 4 3 0 D E S I G N S E M I N A R

Price

Complexity

x310

x320

x330

with LCD driver

without LCD

driver

x11x

More to come

CPU,

Timer/Port

CPU,

A/D converter Timer/Port

CPU,H/W MPY USART,Timer_A Timer/Port

MSP430 Roadmap

HeCh / 02-99/ 3-3

Ultra-low power design with

M S P 4 3 0 D E S I G N S E M I N A R

8kB 4kB ROM/EPROM

16kB C314x310

56 SSOP - DL x330

P337

x320

64 QFP - PM (0.5mm)64 QFP - PG (1.0mm)C323

P325

C325ADC 12+2bit

C = ROM , P = OTP

48 SSOP - DL

32kB 24kB 2kB

12kB 100 QFP - PJM H/W Multiplier 16bit Timer USART

C313C312

C311

P313

C337C336

P315

C315MSP430 Family Members: ‘3xx Configurations

HeCh / 02-99/ 3-4

M S P 4 3 0 D E S I G N S E M I N A R

MSP430C323IPG

MSP430P325IPM

MSP430C312IDL

64 QFP - PG

64 QFP - PM

56 SSOP - DL

MSP430C323IPG MSP430C325IPG MSP430P325IPG

MSP430C323IPM MSP430C325IPM MSP430P325IPM

MSP430C312IDL MSP430C313IDL MSP430C314IDL MSP430C315IDL MSP430P313IDL MSP430P315IDL

MSP430C337IPJM

100 QFP - PJM

MSP430C336IPJM MSP430C337IPJM MSP430P337IPJM

MSP430C311IDL

48 SSOP - DL

MSP430C311IDL MSP430P315SIDL

MSP430P325IFN

68 PLCC - FN

MSP430P325IFN

HeCh / 02-99/ 3-5

M S P 4 3 0 D E S I G N S E M I N A R

MSP430E325IFZ

68 CLCC - FZ

MSP430E325IFZ MSP430E313IFZ

MSP430E337IHFD

100 QFP - HFD

MSP430E337IHFD

HeCh / 02-99/ 3-6

Ultra-low power design with

M S P 4 3 0 D E S I G N S E M I N A R

2kB 0kB

ROM/EPROM

6kB x11020 SOP - DW

More to come

C = ROM , P = OTP

10kB 8kB 4kB C111

C112

P112

MSP430 Family Members: ‘1xx Configurations

HeCh / 02-99/ 3-7

Ultra-low power design with

M S P 4 3 0 D E S I G N S E M I N A R

20 SOP - DW

MSP430C111IDW MSP430C112IDW MSP430P112IDW

20 DIP - JL

PMS430E112IDW

MSP430C112IDW

Prototyping

Production

MSP430C112IDW

Available Packages ‘1xx

HeCh / 02-99/ 3-8

M S P 4 3 0 D E S I G N S E M I N A R

P1.0P1.7

VCC

VSS

RST/NMI

MAB, 16bit

MDB, 16bit

TEST/VPP

Test JTAG

incl. 16 reg.

CPU 2/4kB ROM 'C': ROM 128/256B SRAM MAB,4bit MDB,8bit MCB

Power RAM

Bus conv.

on Reset

I/O Port 1

Timer_A

3 CC Register:4kB OTP

'P': OTP

8 I/O's, all with interr. capability

XIN

XOut

Oscillator

System Clock

ACLK MCLK

SMCLK

Rosc

ACLK SMCLK

Watchdog 15 / 16 bit

Timer

ACLK

DCOR P2.5

P2.0I/O Port 2

6 I/O's, all with interr. capability

Outx CCI1B

Out0CCI0B TACLK SMCLK

TACLK or JTAG

CCIxB

CCIxA x = 0, 1, 2

CCR0/1/2INCLK INCLK Outx CCIxA

HeCh / 02-99/ 3-9

M S P 4 3 0 D E S I G N S E M I N A R

P0.0P0.7

VCC VSS RST/NMI MAB, 16bit MDB, 16bit

Com0..3

Seg 0..18,22,23,26Seg 27/CMPI

TMS TCK

TDI TDO

XIN XOut XBuf Oscillator System Clock

ACLK MCLK

Test JTAG

FLL

incl. 16 reg.

CPU TP.0 .. 5CIN

R13R23

4kB ROM 'C': Prom 'E': EProm

256B SRAM

WDT I/O Port

LCD

8b Timer/B. Timer MAB,4bit MDB,8bit

MCB

15bit

Counter

1, 2, 3, 4 Mux

Serial Protocol

Support

POR

RAM

92 Segmente f LCD

TXD

RXD

8kB ROM

A/D Conv.Timer, O/P

Timer/Port Applications:Bus conv.

8 I/O's, all with 3 Int. Vectors

interr. capability 'P': OTP CMPI

HeCh / 02-99/ 3-10

M S P 4 3 0 D E S I G N S E M I N A R

'C': Prom 'P': OTP SRAM

CPU incl. 16 reg.

Bus conv.

ADC WDT I/O Port

8b Timer/B. Timer MAB, 16bit MDB, 16bit

MAB,4bit MDB,8bit

Oscillator System Clock

ACLK MCLK

MCB

Test JTAG

12+2bit

5 Channels Current S.

FLL

15bit Counter

8 I/O's

Serial Protocol Support

3 Int. Vectors

POR

TMS TCK

TDI TDO

f LCD

TXD RXD

XIN XOut

P0.0P0.7

VCC

VSS

RST/NMI

SVCC

RI A0..5Timer/Port

TP.0TP.5CIN

R 03LCD

1, 2, 3, 4 Mux

84 Segmente Com0..3Seg 0..19Seg 20/CMPI

.....TP.4XBuf

R 23R 33

R 13'E': EProm

8kB ROM 256B RAM 16kB EPROM

512B RAM

16kB ROM 512B RAM CMPI

HeCh / 02-99/ 3-11

M S P 4 3 0 D E S I G N S E M I N A R

P3.0P3.7VCC2VSS1RST/NMI

MAB, 16bit

Com0..3S0..28/O2..28S29/O29/CMPI

TMS TCK

TDI TDO

XIN

XOut

XBuf Oscillator System Clock

ACLK MCLK

FLL

incl. 16 reg.

CPU URX 24kB ROM 1024B SRAM

Watchdog Timer I/O Port

LCD

Basic Timer1

MAB,4bit MDB,8bit

MCB

15bit

30 Segment

1,2,3,4 Mux

Power-on-Reset

RAM

Lines

f LCD R03R23

32kB EPROM

USART

Bus conv.

P4.7I/O Port

1x8 dig. I/O's

P2.x

P1.x I/O Port

2x8 I/O's all with interr. cap.R13R33

P0.0P0.7

I/O Port

8 I/O's, all with 3 Int. Vectors

interr. cap.8

TP.0 .. 5CIN

ADC Timer,O/P

Timer/Port

Appl.’s:UTX UCK

8bit Timer/Counter

RXD

TXD

UART TimerA 16bit PWM

TimerA TACLK TA0.0..5RXD, TXD

MPY MPYS MAC 16x16bit 8x8bit

MDB, 16bit

2 Int. Vectors

1x8 dig. I/O ’s

STE

SIMO

SOMI CMPI

UART or SPI

function

P4.0

VSS2VSS3VCC1Test JTAG

32kB ROM