SolidStateDriveTechnology

Solid State Solid-State Drive(SSD) and Memory System Innovation
Ken Takeuchi Dept. of Electrical Engineering and Information Systems University of Tokyo
Ken Takeuchi
Univ. of Tokyo - INRIA - Ecole des Mines Paris - INRETS Joint Symposium
1

Definition of SSD
SSD : Solid State Drive Mass storage to replace HDD of PC/automobile application. SSD consists of NAND Flash Memory and NAND controller(+RAM) t ll (+RAM)
J. Elliott, WinHEC 2007, SS-S499b_WH07.
All car manufactures are interested in SSD. SSD
Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 2

Reliability bottleneck for automobile application
Reliable Circuit
Reliable Device
Reliability
Reliable OS/Computer architecture Need collaboration with IT/SW community
Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 3

Key Challenge of SSD
Need to improve device reliability such as endurance, data retention, and disturb. R i d i f d t ll Require co-design of NAND and NAND controller circuits to best optimize both NAND and NAND controllers. OS/Computer architecture innovation essential.
K. Takeuchi Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 4

Outline
NAND Overview O e e SSD Overview Operating System for SSD Green IT with SSD Summary
Ken Takeuchi
Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium
5

Outline
NAND Overview O e e SSD Overview Operating System for SSD Green IT with SSD Summary
Ken Takeuchi
Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium
6

NAND Flash Memory
43nm 16Gb NAND
K. Kanda ISSCC 2008. K Kanda, ISSCC, 2008
NAND flash memory chip
Memory circuit
y Memory cell : Floating Gate-FET
Ken Takeuchi
Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium
7

Page & Block of NAND Flash Memory
Page : program/read unit Bitline Block : Erase unit
Bitline
Bitline
2S l t t Select-gate 32 Word-lines
Source-line
2S l t t Select-gate 32 Word-lines
Memory cells are sandwiched by select gates. Contactless structure : ideal 4F2 cell size
F.Masuoka, IEDM 1987, pp.552-555. Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium

Top View of NAND Flash Cell Array
Bitline (second metal) Source-line (first metal)
STI Active area SGD SGD Contact to bitline SGS SGS Contact to source-line
Word-lines
Simple structure : High scalability, High yield
K. Imamiya, ISSCC 1999, pp.112-113. Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium

MLC vs. SLC
SLC : Single-level cell or 1bit/cell MLC : Multi-level cell or >2bit/cell M lti l l ll >2bit/ ll
2bit/cell : Long production record since 2001 3bit/cell or 4bit/cell : Will be commercialized this year.
Existing SSD uses SLC but MLC based SSD will g be commercialized this year.
SLC (Single-level cell) Number of memory cells “1” “0” Vth
Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium
MLC (Multi-level cell) Number of memory cells “0” “1” “2” “3”
Vth

NAND Density Trend
100
M Memory dens [MB y sity B/mm]
2
10
55% growth / year
1
0.1
0.01 1994 1996 1998 2000 2002 2004 2006
Year
ISSCC paper MLC (Multi-level cell) NAND flash ( ) SLC (Single-level cell) NAND flash
K. Takeuchi, ISSCC 2006,pp.144-145. 11
Ken Takeuchi
Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium

NAND Program Speed Trend
12
Prog gram sp peed [M MB/sec]
10 8 6 4 2
ISSCC paper MLC (Multi-level cell) NAND flash SLC (Single-level cell) NAND flash
FTTH 5M-pixel 5photos/sec HDTV 60fps f
4M-pixel 3photos/sec
Motion JPEG VGA 30fps MPEG2 VGA 30fps
0 1994 1996 1998 2000 2002 2004 2006
Year
MLC performance is comparable with SLC. SLC
K. Takeuchi, ISSCC 2006,pp.144-145. Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 12

Chip Architecture
56nm 8Gbit NAND Flash Memory
K. Takeuchi, ISSCC 2006,pp.144-145. Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 13

NAND Operation Principle
Read
Bit line Bit-line (0.8V 0V) Vread (4.5V) Selected word-line (Read voltage : 0V) Vth Number of memory cells “1” 1 0 “0”
Read voltage
Vread (4.5V) Bit-line Bit line voltage “1” “0” Vread (4.5V) 0V Time
After precharging, bit-lines are discharged through the memory cell. Unselected cells are biased to the pass voltage, Vread. U l t d ll bi d t th lt V d Small cell read current (~1uA) Serial access : 30-50ns
Ken Takeuchi
Slow random access (~50us)
Fast read = 20-30MB/sec
14
Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium

NAND Operation Principle (Cont’)
Program : Electron injection
18V 0V 0V
Channel-FN tunneling
0V
High reliability Low current consumption
Erase : Electron ejection
0V 20V 20V
(~pA/cell) Page based parallel program Typical page size : 2-4kB
20V
S. Aritome, IEDM 1990, pp.111-114. Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 15

Outline
NAND Overview O e e SSD Overview Operating System for SSD Green IT with SSD Summary
Ken Takeuchi
Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium
16

SSD Market Projection
PC/automobile expected as the next killer application of NAND. NAND
Gartner Dataquest
I. Cohen, Flash Memory Summit 2007. Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 17

Cost Trend of NAND and HDD
Analyst expectation
O. Balaban, Flash Memory Summit 2007.
NAND will replace 2.5” HDD in 2010-2012 if the cost continues decreasing. decreasing Unclear scaling scenario e.g. double exposure vs. EUV, fl ti gate vs. MONOS and 2D vs. 3D cell. ll floating t MONOS, d
Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 18

SSD Reliability
SSD is robust. No mechanical parts parts. Need to be careful in PC/automobile application Portable consumer electronics application (Digital still cameras, MP3 players, Camcorders) ( g , p y , ) Effective data retention time << 10years Data D t quickly transferred to PC or DVD i kl t f dt through USB drive and memory cards. Most probably data backup in PC PC/automobile application Higher reliability required w.o. backup Need longer data retention time : 5-10 years
Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 19

SSD Reliability (Cont’)
Failure mechanism of NAND Program disturb During programming, electrons are injected to unselected memory cells. Read disturb During read, electrons are injected to unselected memory cells. ll Write/Erase endurance & Data retention As the Write/Erase cycles increase, damage of the tunnel oxide causes a leakage of stored charge.
Ken Takeuchi Univ. of Tokyo - INRIA - Ecole des Mines Paris - INRETS Joint Symposium 2008.7.7 20