bf533使用SCCB实现I2C总线

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Usage of the SCCB Software Interface for configuring I2C devices by the Blackfin? Processor family

Contributed by Thorsten Lorenzen

August 31, 2005

This application note describes the implementation of the Serial Camera Control Bus (SCCB) Interface based on software for Blackfin? Processors. Because of its architecture and video processing capabilities, Blackfin Processors will interface with video devices. All those devices acting in the video signal chain can be configured by the same interface with a two-wire bus. For those Blackfin derivatives that do not have an I2C compatible hardware interface (Known as Blackfin TWI) this software can be taken to simulate the function of I2C with the help of two processor programmable flag pins. The protocol supports slave devices only. Blackfin is keeping the master ship always. No multi maser bus network can be accessed.

Please be aware that slave devices need to be fully I2C compatible. For instance, the SCCB interface of Omnivision sensors is not fully compatible. This is due to the missing extra start condition at a read sequence. Additionally, those parts do not acknowledge any byte (don’t care).

Basics

The SCCB interface can be realized with the use of two programmable flags. In this example, PF0 is used to generate the clock line while PF1 is used for transmitting and receiving data. This functionality is most common in configuring

video devices. The software attached to this document implements the protocol required to initialize those types of devices. Most devices require some initialization which can be accomplished with a series of byte transfers. Once the device is setup, it is common to only have to send over a byte each video frame. A programmable timer is used to run the two-wire state machine. The timer generates an interrupt after its counter is expired. All activities of the SCCB interface are performed during the timer interrupt. The rate of the SCCB clock is determined by the interrupt interval of the timer. As an example, the time between these interrupts can be used to process video data as it is received.

Software Protocol

Common video devices are fitted with an interface that is dedicated to setup all the registers in the devices. For register setup purposes, it makes sense to use a protocol that provides the device address, device register address and the data to be stored in device registers. In order to save pins, it also makes sense to use as few as possible lines. As described previously, only two lines are required for this kind of network. Because an address scheme is used, multiple devices can be connected on the same lines. Figure 1 shows an example connection.

Figure 1 Device Connection

The protocol required to identify a specific device is explained below:

To generate a write to a register of a device, the data line must send the “Device Address” at first, followed by the register’s “Word Address”. At this point, the actual data can be transferred. Each bit must be aligned to a clock cycle generated by the second “clock line”. As long as the clock keeps going data words will be sent to the slave. The address will be incremented internally by the slave.

Note: After each 8th bit transferred an Acknowledge (9th -bit) will be invoked by the master (Blackfin). The SCCB interface will put the data line high and reconfigure PF1 as an input. If the slave (video device) does not pull down the data line the code will end in an error routine indicating failed access.

Figure 2 shows a write access. As it can be seen, the 8th bit of the Device Address indicates that

the following data will be written in the device.

Figure 2 I2C Write Access

The read access starts the same way by writing the “Device Address”, followed by the register’s “Word Address” to the device. After this is done,

an extra start condition must be inserted as it is shown in Figure 4. The Device Address will be written to the device again, but the 8th -bit is set to high indicating a read access follows. If those kinds of devices receive a second Device Address, as shown in figure 3, the device starts sending the contents that the internal address pointer points to. Continuously, multiple data words can be sent from the slave device to the processor.

Note: Similar to the write process, sending the device address, word address and devices address again ends in an acknowledge test as described before. But the stage of receiving data from the slave (device) the master (processor) has to pull down the line while the slave (device) observes whether it has been done. If the master (processor) does not pull down the data line the slave (device) will go in power down mode and keep the data line high. The transmission of the final data byte

will not end in an acknowledge.

Figure 3 I2C Read Access

Figure 4 shows the start condition, stop condition and the data and clock alignment. After the start condition, the data bit must be available before the raising edge of the clock. In addition, it must

not be released before the clocks falling edge.

Figure 4 I2C Start, Stop Condition

The SCCB software interface meets all these requirements. More details about the I2C timing can be found in dedicated literatures over the WWW.

Software structure

The SCCB Interface is located in the file (BF53xSCCB_Interface.asm or I2C_BF561_rev03.asm). Before calling this routine (SCCB_interface) some configurations must be done. To understand the use of the interface the following steps are provided:

An ASM/C file called xxx_Config.asm/c such as “BF533_EZ-KIT_ADV7171_Config.asm” attached to this document is used to set up the SCCB system. Go through the file and check the variables named below.

With the help of the variable “SCCB_Control”, transmitting or receiving can be chosen. “SCCB_Word_Count” holds the number of transfers that must be performed. Device Addresses and Word Address are included.

The data for transmission will be held in the variable “SCCB_DataIn”.

The data received at a read execution will be held in the variable “SCCB_DataOut”.

After these settings are made, the subroutine “SCCB_interface” stored in the file “eg. BF53x_SCCB_interface.ASM” must be called to start the transfer.

The subroutine (SCCB_Interface) stores and restores all registers used in the SCCB interface. It starts the timer0 and sets up there interrupt and PF0, PF1. Some variables required for the transfer are generated.

When the initialization process is finished, the core returns from subroutine to the user application code. A timer interrupt appears after a certain time. It was generated by the initialization process from before. Each timer interrupt will be taken to drive a signal change. From PF0 or PF1 “timer based program execution”.

During the SCCB transfer, all used flags and the selected timer must not be used for any other purposes. The registers and pointers can be used because they will be stored and restored before and after the end of each interrupt.

Do never start the SCCB interface a second time before the actual has been

finished. For multiple device setups,

make use of conditional loops or place

code between each call that guaranties

the delay required to finish the process.

The final timer interrupt will turn the timer off and disable all previous settings.

Software Implementation

In order to implement the SCCB Interface, add the file “BF533_SCCB_Interface.ASM” or “I2C_BF561_rev03.asm“ to your project. Place the setup instructions located in “xxx_Config.ASM” in your main file. Read the notes placed in the file “xxx_Config.ASM”.

Note: If you like to request source code to this document please visit:

https://www.360docs.net/doc/d818776704.html,/processors/proc

essors/blackfin/technicalLibrary/manual

s/codeExamples.html

SCCB Performance

The following example shows the performance measured. The processor load for a particular case is listed below:

The core clock (CCLK) runs at 432MHz

The peripheral clock (SCLK) runs at 108MHz The timer0 is set to run the SCCB at 70 KHz (see

Figure 5)

Figure 5 Write Access Timing

Figure 5 shows a register write. Three bytes are sent (Channel 1 as SDA) (Channel 2 as SCL). The first 8 bits include the device address. In this case it is “0xC0”. The 9th bit is held low by the slave (acknowledge). The following 8 bits hold the word address “0x13” within the identified device followed by the second acknowledge. Finally, the last 8 bits carries the registers content “0x21” followed by the third acknowledge. Let’s have a look at figure 5 again. The time between the signal changes of the data line and the clock line can be taken by the core to execute other instructions. Figure 6 zooms out the write transfer displayed in figure 5 and shows some additional pins. Channel 1 shows the timer0 pin (TMR0), channel 2 shows PF4 programmed to just toggle outside the timer interrupt. Channel 3 the SDA line and channel 4 the SCL line.

As it can be seen each positive edge of the timer0 pin (Channel 1) will trigger an interrupt. The interrupt will cause the PF4 pin to stop and to start toggling.

Figure 6 Performance Test Timing

As it can be seen in listing 1 the core is running in a loop outside of interrupt events. The loop executes the following instructions:

P0 = 0x02FF(Z);

LSETUP(Loop_Start,performance_test)LC0 =P0;

Loop_Start:

p0.h = hi(FIO_FLAG_C);

p0.l = lo(FIO_FLAG_C);

r0.l = 0x10;

w[p0] = r0;

p0.l = lo(FIO_FLAG_S);

r0.l = 0x10;

performance_test: w

[p0] = r0;

Listing 1 Performance Test Instructions

These instructions affect that the pin PF4 is toggling as shown in figure 6. PF4 does not toggle when the core is executing SCCB instructions during the timer interrupt. Each positive edge of the pin TMR0 causes the timer interrupt as mentioned before.

Figure 7 illustrates the processor load. At the beginning PF4 is toggling. The positive edge of TMR0 generates the timer interrupt. That causes PF4 to stop toggling. The first interrupt (figure 6) forces the clock line (SCL) to clear its pin. After

the interrupt is completed, PF4 toggles again until the next positive edge of the TMR0 pin appears. The next interrupt caused by TMR0 again forces the data line to clear.

Figure 7 Performance Test Timing

Figure 7 shows the clearance of SCL zooming out Figure 6.

Note: The frequency of PF4 (Channel 2) does not relate to the core frequency immediately. Each instruction in the loop (Listing 1) will be executed in one or two cycles but toggling the actual pin means to make use of the system bus which is linked to the pin. The system bus does run at 108MHz as mentioned before.

The frequency of PF4 is a combination of the core speed (CCLK) as well as the system speed (SCLK).

Conclusion

If the CCLK runs at 432MHz, the SCLK runs at 108MHz and the SCCB interface runs at 70KHz during the SCCB action, the entire transfer (shown in Figure 5) will take 404μs. After the transfer is completed the core processes data at 100% again. As it can be seen during the transfer, 5% of the Timer period is taken by the SCCB interrupt. 95% of the timer period can be taken to process data. Finally, the core performance can be increased by slowing down the timer. That results in a higher percentage of data processing performance but extends the SCCB transfer time. This example has been made to support the not existing I2C hardware interface for ADSP-BF53x Blackfin processors. The performance can still be enhanced by restructuring the code.

Note: Generally, the code was written to be implemented on the ADSP-BF533 EZ-KIT. Please be aware that it must be modified slightly to make use of the ADSP-BF561 as well as on hardware different to the ADSP-BF533 EZ-KIT.

It should be taken aware of that I2C support is limited due to Philips license restrictions. Additionally, the code this document is dedicated to is just given to customers that have agreed the terms of conditions

Note: If you like to request source code to this document please visit:

https://www.360docs.net/doc/d818776704.html,/processors/proc essors/blackfin/technicalLibrary/manual s/codeExamples.html

References

-ADSP-BF531/BF532/BF533 Datasheet, REV. PrA, 2003, Analog Devices Inc

-ADSP-BF533 Blackfin? Hardware Reference Manual, Revision 3.0, August 2004

-ADSP-BF561 Blackfin? Hardware Reference Manual, Preliminary Revision 0.3, November 2004 -ADV 7171 Datasheet, REV. A, 2001, Analog Devices Inc

-ADV 7183 Datasheet, REV. 0, 2002, Analog Devices Inc

-Blackfin? Processor Instruction Set Reference, Revision 2.0, May 2003, Analog Devices Inc

-VisualDSP++ 4.0

--IDDE Version 6.5.0.1

--ADSP-Blackfin Family Assembler 2.6.7.5

--ADI DSP Linker 3.5.2.2

https://www.360docs.net/doc/d818776704.html,

-Omnivision Serial Camera Control Bus (SCCB) Application Note “https://www.360docs.net/doc/d818776704.html,/pdfs/ds_note.pdf”https://www.360docs.net/doc/d818776704.html,

https://www.360docs.net/doc/d818776704.html,

Document History

Version Description

May 15, 2003 by Thorsten Lorenzen. Final draft release REV 1.0-

August 30, 2005 by Thorsten Lorenzen Update for next chip revisions and BF561 support.

August 30, 2005 by Thorsten Lorenzen Code update to avoid glitches on the bus.

BF533_EZ-KIT_ADV7171_Config.asm

File Name:

Date Modified: 8/30/05 TL Rev 2.0

Software: VisualDSP++4.0

Hardware: BF533 EZ-KIT Board

Purpose: To configure ADV video devices

**********************************************************************************/ #include

#include "startup.h"

/****************************************************************/

// Program Define Section

/****************************************************************/

#define rd_cmd 0x1 // sccb interface read command

#define wr_cmd 0x2 // sccb inteface write command

#define ADV7171_WR 0x54 // write address of video encoder

#define ADV7171_RD 0x55 // read address of video encoder

#define ADV7183_WR 0x88 // read address of video decoder

#define ADV7183_RD 0x89 // write address of video decoder

#define ADV7171_reg_cnt 0x1a // encoder register count (26 registers)

#define ADV7171_MR0 0x0 // mode reg 0 address of the encoder

#define ADV7171_MR1 0x1 // mode reg 1 address of the encoder

#define ADV7183_In_Control 0x0 // Input Control Register of decoder

#define ADV7171_ColorBar 0x80 //generate an internal color bar

#define ADV7183_AVIN4 0x3 //switch to AVIN4

.global Config_of_ADV7171;

.extern SCCB_Control;

.extern SCCB_Word_Count;

.extern SCCB_DataIn;

.extern SCCB_DataOut;

.extern SCCB_Interface;

.extern SCCB_Read_Count;

.extern SCCB_In_Progress;

/********************** SCCB Start Settings***********************************/

a /*Before Calling the SCCB_Interface the inputs to the SCCB_Taskmanager */

/*must be done. */

/* Write to the "SCCB_Control" a "1" for reading from the Device or */

/* a "2" for writing to the Device. */

/* */

/* Leave the number of bytes in total in "SCCB_Wordcount". Device Addresses */

/* and Word Addresses included. */

/* */

/* Write all data to the "SCCB_DataIn". */

/* e.g.Writing to the device: */

/* */

/* SCCB_DataIn Device Address (LSB must be Zero) */

/* Word Address */

/* Data 1 */

/* Data 2 */

/* . */

/*****************************************************************************/

/* (e.g.Reading from the device: */

/* SCCB_DataIn Device Address (LSB must be zero) */

/* Word Address */

/* Device Address (LSB must be one) */

/* SCCB_DataOut Holds the data received! */

/*****************************************************************************/

/* See below !!!!!! */

/*****************************************************************************/

.section L1_code;

/*****************************************************************************/

//write regs to the ADV7171 encoder

Config_of_ADV7171:

p0.l = SCCB_DataIn;

p0.h = SCCB_DataIn;

r0 = ADV7171_WR (z); //Device select

[p0++] = r0;

r0 = ADV7171_MR1 (z); //Device Subregister select

[p0++] = r0;

r0 = ADV7171_ColorBar (z); //Data to transfer in the register

[p0++] = r0;

p0.l = SCCB_Word_Count;

p0.h = SCCB_Word_Count;

r0 = 3 (z); //Number of transfers in total

[p0] = r0;

p0.l = SCCB_Control;

p0.h = SCCB_Control;

r0 = wr_cmd (z); //controls whether to read or to write

[p0] = r0;

p0.h = SCCB_In_Progress; //takes care that the next transfer will not

p0.l = SCCB_In_Progress; // start before the last one ends

r0 = 1;

[p0] = r0;

Config_of_ADV7171.END:

RTS;