东南大学 计算结构 课程设计 POC设计报告

Computer Organization and

Architecture

Course Design

The Report of the parallel output controller (POC) Array School of Information Science and Engineering Southeast University

2014

COA-POC

1. Purpose

The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus II

EDA tool is recommended and provided for simulation.

2. Introduction and requirements

●Basic introduction

POC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral (such as a printer or other output devices).

●Architectural Model Array Figure 1 Printer Connection

Figure 1 shows the connecting of a printer to the system bus through the POC. The communication between POC and the printer is controlled by a “handshake” protocol

illustrated in Figure 2.

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COA-POC

Figure 2 The handshake-timing diagram between POC and the printer

The handshaking process is described as follows : When the printer is ready to receive a character, it holds RDY =1.The POC must then hold a character at PD (parallel data)port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the character at PD and hold the RDY at 0 until the character has been printed (e.g. 5 or 10ms), then set RDY =1 again when it is ready to receive the next character. (Suppose the printer has only a one character “buffer” register, so that each character must be printed before the next character is sent).

3. Design of Top Schematic

Figure 3 The Top Schematic of the simulated printer and POC

There are three modules in the figure: the CPU,the Printer and the POC. According to the hints in the direction, we know that in order to simulate the POC by computer, a simulated printer is been written.

4. Design of Each Module

4.1 CPU

Figure 4 The Schematic Symbol of CPU

4.2 POC

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COA-POC

4.3 Printer

Figure 6 The Schematic Symbol of Printer

5. Simulation Results

5.0 Introduction

Following is the Simulation Waveforms. 0xF0 is set to be POC SR address and 0xF1 is set to be POC BR address.

5.1 Query mode

Figure 7-1 : CPU Sets ADDR to be 0xF0 to get POC Status(SR).

Figure 7-2 : POC is idle, CPU sends new data to POC Buffer Register(BR, address 0xF1).

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Figure 7-3 : CPU refresh POC-SR.

Figure 7-4 : POC puts data on PD, starting handshake with printer.

Figure 7-5 : TR is set high, the printer gets the data, then starting printing.

Figure 7-6 : Printing process finished, RDY turn high to inform POC that printer is idle.

Figure 7-7 : When POC and printer is busy, CPU query will be denied, so that CPU will not send new data to POC.

5.2 Interrupt Mode

Figure 8-1 : IRQ valid, CPU Turn into Interrupt Program.

Figure 8-2 : Without access to POC-SR, CPU writes data to BR(0xF1) directly.

Figure 8-3 : CPU refresh POC-SR(0xF0).

Figure 8-4 : Handshake between POC and the printer. The printer starts printing.

Figure 8-5 : Printing process finished, RDY turn high to inform POC that printer is idle.

Figure 8-6 : POC set IRQ valid to inform CPU that the printer is available.

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COA-POC

Southeast University

COA-POC

Southeast University