IDT64ALVCH16823PA中文资料

INDUSTRIAL T EMPERATURE R ANGE

IDT74ALVCH16823

3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

?0.5 MICRON CMOS Technology

?Typical t SK(o) (Output Skew) < 250ps

?ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)?V CC = 3.3V ± 0.3V, Normal Range ?V CC = 2.7V to 3.6V, Extended Range ?V CC = 2.5V ± 0.2V

?CMOS power levels (0.4μ W typ. static)

?Rail-to-Rail output swing for increased noise margin ?Available in TSSOP package

FUNCTIONAL BLOCK DIAGRAM

DRIVE FEATURES:

?High Output Drivers: ±24mA ?Suitable for heavy loads

APPLICATIONS:

? 3.3V high speed systems

? 3.3V and lower voltage computing systems

IDT74ALVCH16823

3.3V CMOS 18-BIT

BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUT-PUTS AND BUS-HOLD

DESCRIPTION:

This 18-bit bus-interface flip-flop is built using advanced dual metal CMOS technology. The ALVCH16823 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing wider buffer registers, I/O ports, bidirec-tional bus drivers with parity, and working registers.

The ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop.With the clock-enable (CLKEN ) input low, the D-type flip-flops enter data on the low-to-high t ransitions o f t he c lock. T aking CLKEN h igh d isables t he c lock b uffer,thus l atching t he o utputs. T aking t he c lear (CLR ) i nput l ow c auses t he Q o utputs to go low independently of the clock.

A buffered output-enable (OE ) input can be used to place the nine outputs in e ither a n ormal l ogic s tate (high o r l ow l ogic l evels) o r a h igh-impedance s tate.In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability t o d rive b us l ines w ithout n eed f or i nterface o r p ullup c omponents. T he OE input does not affect the internal operation of the flip-flops. Old data can be retained o r n ew d ata c an b e e ntered w hile t he o utputs a re i n t he h igh-impedance state.

The ALVCH16823 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

The ALVCH16823 has “bus-hold” which retains the inputs’ last state whenever t he i nput g oes t o a h igh i mpedance. T his p revents f loating i nputs a nd eliminates the need for pull-up/down resistor.

INDUSTRIAL T EMPERATURE R ANGE

IDT74ALVCH16823

3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

(1)

2.Output level before the indicated steady-state input conditions were established.

NOTE:

1.These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

INDUSTRIAL T EMPERATURE R ANGE

IDT74ALVCH16823

3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

Symbol Parameter Test Conditions Min.Typ.(1)Max.Unit V IH Input HIGH Voltage Level V CC = 2.3V to 2.7V 1.7——V

V CC = 2.7V to 3.6V 2——V IL Input LOW Voltage Level V CC = 2.3V to 2.7V ——0.7V V CC = 2.7V to 3.6V ——0.8I IH Input HIGH Current V CC = 3.6V V I = V CC ——±5μA I IL Input LOW Current

V CC = 3.6V V I = GND ——±5μA I OZH High Impedance Output Current V CC = 3.6V

V O = V CC ——±10μA I OZL (3-State Output pins)V O = GND

——±10V IK Clamp Diode Voltage

V CC = 2.3V, I IN = –18mA —–0.7–1.2V V H Input Hysteresis

V CC = 3.3V —100—mV I CCL Quiescent Power Supply Current

V CC = 3.6V

—

0.1

μA I CCH V IN = GND or V CC

I CCZ ?I CC

Quiescent Power Supply Current One input at V CC - 0.6V, other inputs at V CC or GND ——750μA

Variation

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:Operating Condition: T A = –40°C to +85°C

NOTE:

1.Typical values are at V CC = 3.3V, +25°C ambient.

BUS-HOLD CHARACTERISTICS

Symbol Parameter (1)

Test Conditions

Min.Typ.(2)Max.Unit I BHH Bus-Hold Input Sustain Current V CC = 3V V I = 2V – 75——μA I BHL V I = 0.8V 75——I BHH Bus-Hold Input Sustain Current V CC = 2.3V V I = 1.7V – 45——μA I BHL V I = 0.7V 45——I BHHO Bus-Hold Input Overdrive Current

V CC = 3.6V

V I = 0 to 3.6V

—

±500

μA

I BHLO

NOTES:

1.Pins with Bus-Hold are identified in the pin description.

2.Typical values are at V CC =

3.3V, +25°C ambient.

INDUSTRIAL T EMPERATURE R ANGE

IDT74ALVCH16823

3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

OPERATING CHARACTERISTICS, T A = 25°C

NOTE:

1.V IH and V IL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V CC range.

T A = – 40°C to + 85°C.

INDUSTRIAL T EMPERATURE R ANGE

IDT74ALVCH16823

3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SWITCHING CHARACTERISTICS (1)

V CC = 2.5V ± 0.2V

V CC = 2.7V V CC = 3.3V ± 0.3V Symbol Parameter

Min.Max.Min.Max.Min.Max.Unit f MAX 150—150—150—MHz t PLH Propagation Delay 1

5.8

—

5.2

4.5

t PHL xCLK to xQx t PLH Propagation Delay 1

5.4

—

5.2

1.2

4.6

t PHL xCLR to xQx t PZH Output E nable T ime 1

—

5.7

4.8

t PZL xOE to xQx t PHZ Output Disable Time 1.1

5.4

—

4.7

1.3

4.5

t PLZ xOE to xQx

t W Pulse Duration, xCLR LOW 3.3— 3.3— 3.3—ns t W Pulse Duration, xCLK HIGH or LOW 3.3— 3.3— 3.3—ns t SU Set-up Time, xCLR inactive 0.7—0.7—0.8—ns t SU Set-up Time, data LOW before xCLK ↑ 1.4— 1.6— 1.3—ns t SU Set-up Time, data HIGH before xCLK ↑ 1.1— 1.1—1—ns t SU Set-up Time, xCLKEN LOW before xCLK ↑ 1.8— 1.9— 1.5—ns t H Hold Time, data LOW after xCLK ↑0.4—0.5—0.5—ns t H Hold Time, data HIGH after xCLK ↑0.7—0.1—0.8—ns t H Hold Time, xCLKEN LOW after CLK ↑0.2—0.3—0.4—ns t SK(O)

Output Skew (2)

—

500

NOTES:

1.See TEST CIRCUITS AND WAVEFORMS. T A = – 40°C to + 85°C.

2Skew between any two outputs of the same package and switching in the same direction.

INDUSTRIAL T EMPERATURE R ANGE

IDT74ALVCH16823

3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

INDUSTRIAL T EMPERATURE R ANGE

IDT74ALVCH16823

3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

ORDERING INFORMATION

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IDT XX

ALVC XXX

XX Package

Device Type Temp. Range

PA 1674

Thin Shrink Small Outline Package

18-Bit Bus-Interface Flip-Flop with 3-State Outputs –40°C to +85°C

X XXX

Family

Bus-Hold 823Bus-Hold H Double-Density, ±24mA