BC41B143A05-IRK-E4中文资料
Device Features
_?ìé`?êé?QJolj Single Chip Bluetooth ? v2.0 System with EDR Production Data Sheet for
BC41B143A
! Fully Qualified Bluetooth v2.0 system
! Enhanced Data Rate (EDR) compliant with
v2.0.E.2 of specification for both 2Mbps and
3Mbps modulation modes ! Full Speed Bluetooth Operation with Full Piconet Support ! Scatternet Support ! 1.8V core, 1.7 to 3.6V I/O split rails
! Low Power 1.8V Operation
! Small footprint 6 x 6mm 84-ball VFBGA
Package
! Minimal External Components Required ! Integrated 1.8V regulator
! USB and Dual UART Ports to 3MBaud
! Support for 802.11 Coexistence
! RoHS Compliant
July 2005 General Description
Applications _?ìé`?êéQJolj is a single chip radio and
baseband IC for Bluetooth 2.4GHz systems
including enhanced data rates (EDR) to 3Mbps.
With the on-chip CSR Bluetooth software stack it
provides a fully compliant Bluetooth system to v2.0
of the specification for data and voice
communications. ! Cellular Handsets ! Personal Digital Assistants ! Digital cameras and other high volume consumer products
BlueCore4-ROM System Architecture
BlueCore4-ROM has been designed to reduce the number of external components required which ensures that production costs are minimised. The device incorporates auto-calibration and built-in self-test (BIST) routines to simplify development, type approval and production test. All hardware and device firmware is fully compliant with the Bluetooth v2.0 Specification (all mandatory and optional features). To improve the performance of both Bluetooth and 802.11b/g co-located systems a wide range of co-existence features are available including a variety of
hardware signalling: basic activity signalling and Intel
WCS activity and channel signalling.
_?ìé`?êé?QJolj Product Data Sheet
Contents
Status Information (7)
1 Key Features (8)
2 6 x 6mm VFBGA Package Information (9)
2.1 BlueCore4-ROM Pinout Diagram (9)
2.2 Device Terminal Functions (10)
3 Electrical Characteristics (13)
3.1 Power Consumption (18)
4 Radio Characteristics – Basic Data Rate (19)
4.1 Temperature +20°C (19)
4.1.1 Transmitter (19)
4.1.2 Receiver (21)
4.2 Temperature -40°C (23)
4.2.1 Transmitter (23)
4.2.2 Receiver (23)
4.3 Temperature -25°C (24)
4.3.1 Transmitter (24)
4.3.2 Receiver (24)
4.4 Temperature +85°C (25)
4.4.1 Transmitter (25)
4.4.2 Receiver (25)
4.5 Temperature +105°C (26)
4.5.1 Transmitter (26)
4.5.2 Receiver (26)
5 Radio Characteristics – Enhanced Data Rate (27)
5.1 Temperature +20°C (27)
5.1.1 Transmitter (27)
5.1.2 Receiver (28)
5.2 Temperature -40°C (29)
5.2.1 Transmitter (29)
5.2.2 Receiver (30)
5.3 Temperature -25°C (31)
5.3.1 Transmitter (31)
5.3.2 Receiver (32)
5.4 Temperature +85°C (33)
5.4.1 Transmitter (33)
5.4.2 Receiver (34)
5.5 Temperature +105°C (35)
5.5.1 Transmitter (35)
5.5.2 Receiver (36)
6 Device Diagram (37)
7 Description of Functional Blocks (38)
7.1 RF Receiver (38)
7.1.1 Low Noise Amplifier (38)
7.1.2 Analogue to Digital Converter (38)
7.2 RF Transmitter (38)
7.2.1 IQ Modulator (38)
7.2.2 Power Amplifier (38)
7.2.3 Auxiliary DAC (38)
7.3 RF Synthesiser (38)
7.4 Power Control and Regulation (38)
7.5 Clock Input and Generation (39)
7.6 Baseband and Logic (39)
_?ìé`?êé?QJolj Product Data Sheet
7.6.1 Memory Management Unit (39)
7.6.2 Burst Mode Controller (39)
7.6.3 Physical Layer Hardware Engine DSP (39)
7.6.4 RAM (39)
7.6.5 ROM (39)
7.6.6 USB (40)
7.6.7 Synchronous Serial Interface (40)
7.6.8 UART (40)
7.6.9 Audio PCM Interface (40)
7.7 Microcontroller (40)
7.7.1 Programmable I/O (40)
7.7.2 802.11 Coexistence Interface (40)
8 CSR Bluetooth Software Stacks (41)
8.1 BlueCore HCI Stack (41)
8.1.1 Key Features of the HCI Stack – Standard Bluetooth Functionality (42)
8.1.2 Key Features of the HCI Stack – Extra Functionality (43)
8.2 BlueCore RFCOMM Stack (44)
8.2.1 Key Features of the BlueCore4-ROM RFCOMM Stack (45)
8.3 BlueCore Virtual Machine Stack (46)
8.4 BCHS Software (47)
8.5 Additional Software for Other Embedded Applications (47)
8.6 CSR Development Systems (47)
9 Enhanced Data Rate (48)
9.1 Enhanced Data Rate Baseband (48)
9.2 Enhanced Data Rate π/4 DQPSK (48)
9.3 Enhanced Data Rate 8DPSK (49)
10 Device Terminal Descriptions (51)
10.1 RF Ports (51)
10.1.1 TX_A and TX_B (51)
10.1.2 Single-Ended Input (RF_IN) (52)
10.1.3 Transmit RF Power Control for Class 1 Applications (TX_PWR) (52)
10.1.4
Control of External RF Components (53)
10.2 External Reference Clock Input (XTAL_IN) (54)
10.2.1 External Mode (54)
10.2.2 XTAL_IN Impedance in External Mode (54)
10.2.3 Clock Timing Accuracy (54)
10.2.4 Clock Start-Up Delay (55)
10.2.5 Input Frequencies and PS Key Settings (56)
10.3 Crystal Oscillator (XTAL_IN, XTAL_OUT) (57)
10.3.1 XTAL Mode (57)
10.3.2 Load Capacitance (58)
10.3.3 Frequency Trim (58)
10.3.4 Transconductance Driver Model (59)
10.3.5 Negative Resistance Model (59)
10.3.6 Crystal PS Key Settings (59)
10.3.7 Crystal Oscillator Characteristics (60)
10.4 UART Interface (63)
10.4.1 UART Bypass (65)
10.4.2 UART Configuration While RESET is Active (65)
10.4.3 UART Bypass Mode (65)
10.4.4 Current Consumption in UART Bypass Mode (65)
10.5 USB Interface (66)
10.5.1 USB Data Connections (66)
10.5.2 USB Pull-Up Resistor (66)
10.5.3 Power Supply (66)
10.5.4 Self Powered Mode (67)
10.5.5 Bus Powered Mode (68)
10.5.6 Suspend Current (69)
_?ìé`?êé?QJolj Product Data Sheet
10.5.7 Detach and Wake-Up Signalling (69)
10.5.8 USB Driver (69)
10.5.9 USB 1.1 Compliance (70)
10.5.10 USB 2.0 Compatibility (70)
10.6 Serial Peripheral Interface (70)
10.6.1 Instruction Cycle (70)
10.6.2 Writing to BlueCore4-ROM (71)
10.6.3 Reading from BlueCore4-ROM (71)
10.6.4 Multi Slave Operation (71)
10.7 Audio PCM Interface (72)
10.7.1 PCM Interface Master/Slave (73)
10.7.2 Long Frame Sync (74)
10.7.3 Short Frame Sync (74)
10.7.4 Multi Slot Operation (75)
10.7.5 GCI Interface (75)
10.7.6 Slots and Sample Formats (76)
10.7.7 Additional Features (76)
10.7.8 PCM Timing Information (77)
10.7.9 PCM Slave Timing (79)
10.7.10 PCM_CLK and PCM_SYNC Generation (81)
10.7.11 PCM Configuration (82)
10.8 I/O Parallel Ports (83)
10.8.1
PIO Defaults for BTv2.0 + EDR HCI Level Bluetooth Stack (83)
10.9 I 2C Interface (84)
10.10 TCXO Enable OR Function (84)
10.11 RESET and RESETB (85)
10.11.1 Pin States on Reset (86)
10.11.2 Status after Reset (86)
10.12 Power Supplies (87)
10.12.1 Supply Domains and Sequencing (87)
10.12.2 External Voltage Source (87)
10.12.3 Linear Regulator (87)
10.12.4 VREG_EN Pin (87)
11 Application Schematic (88)
12 Package Dimensions (89)
12.1 6 x 6mm VFBGA 84-Ball Package (89)
13 Solder Profiles (90)
13.1 Solder Re-Flow Profile for Devices with Lead-Free Solder Balls (90)
14 Ordering Information (92)
14.1 BlueCore4-ROM (92)
15 Tape and Reel Information (93)
15.1 Tape Orientation and Dimensions (93)
15.2 Reel Information (95)
15.3 Dry Pack Information (96)
15.4 Baking Conditions (97)
15.5 Product Information (97)
16 Contact Information (98)
17 Document References (99)
Terms and Definitions (100)
Document History (102)
_?ìé`?êé?QJolj Product Data Sheet
List of Figures
Figure 2.1: BlueCore4-ROM Device Pinout (9)
Figure 6.1: BlueCore4-ROM Device Diagram (37)
Figure 8.1: BlueCore HCI Stack (41)
Figure 8.2: BlueCore RFCOMM Stack (44)
Figure 8.3: Virtual Machine (46)
Figure 9.1: Basic Data Rate and Enhanced Data Rate Packet Structure (48)
Figure 9.2: π/4 DQPSK Constellation Pattern (49)
Figure 9.3: 8DPSK Constellation Pattern (50)
Figure 10.1: Circuit TX/RX_A and TX/RX_B (51)
Figure 10.2: Circuit RF_IN (52)
Figure 10.3: Internal Power Ramping (53)
Figure 10.4: TCXO Clock Accuracy (54)
Figure 10.5: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting (55)
Figure 10.6: Crystal Driver Circuit (57)
Figure 10.7: Crystal Equivalent Circuit (57)
Figure 10.8: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency (60)
Figure 10.9: Crystal Driver Transconductance vs. Driver Level Register Setting (61)
Figure 10.10: Crystal Driver Negative Resistance as a Function of Drive Level Setting (62)
Figure 10.11: Universal Asynchronous Receiver (63)
Figure 10.12: Break Signal (64)
Figure 10.13: UART Bypass Architecture (65)
Figure 10.14: USB Connections for Self Powered Mode (67)
Figure 10.15: USB Connections for Bus Powered Mode (68)
Figure 10.16: USB_DETACH and USB_WAKE_UP Signal (69)
Figure 10.17: Write Operation (71)
Figure 10.18: Read Operation (71)
Figure 10.19: BlueCore4-ROM as PCM Interface Master (73)
Figure 10.20: BlueCore4-ROM as PCM Interface Slave (73)
Figure 10.21: Long Frame Sync (Shown with 8-bit Companded Sample) (74)
Figure 10.22: Short Frame Sync (Shown with 16-bit Sample) (74)
Figure 10.23: Multi Slot Operation with Two Slots and 8-bit Companded Samples (75)
Figure 10.24: GCI Interface (75)
Figure 10.25: 16-Bit Slot Length and Sample Formats (76)
Figure 10.26: PCM Master Timing Long Frame Sync (78)
Figure 10.27: PCM Master Timing Short Frame Sync (78)
Figure 10.28: PCM Slave Timing Long Frame Sync (80)
Figure 10.29: PCM Slave Timing Short Frame Sync (80)
Figure 10.30: Example EEPROM Connection (84)
Figure 10.31: Example TXCO Enable OR Function (84)
Figure 13.1: Application Circuit for Radio Characteristics Specification with 6 x 6mm VFBGA Package (88)
Figure 14.1: BlueCore4-ROM 84-Ball VFBGA Package Dimensions (89)
Figure 15.1: Typical Lead-Free Re-flow Solder Profile (90)
Figure 17.1: Tape and Reel Orientation (93)
Figure 17.2: Tape Dimensions (94)
_?ìé`?êé?QJolj Product Data Sheet
Figure 17.3: Reel Dimensions (95)
Figure 17.4: Tape and Reel Packaging (96)
Figure 17.5: Product Information Labels (97)
List of Tables
Table 9.1: Data Rate Schemes (48)
Table 9.2: 2-Bits Determine Phase Shift Between Consecutive Symbols (49)
Table 9.3: 3-Bits Determine Phase Shift Between Consecutive Symbols (50)
Table 10.1: TXRX_PIO_CONTROL Values (53)
Table 10.2: External Clock Specifications (54)
Table 10.3: PS Key Values for CDMA/3G Phone TCXO Frequencies (56)
Table 10.4: Oscillator Negative Resistance (59)
Table 10.5: Possible UART Settings (63)
Table 10.6: Standard Baud Rates (1) (64)
Table 10.7: USB Interface Component Values (67)
Table 10.8: Instruction Cycle for an SPI Transaction (70)
Table 10.9: PCM Master Timing (77)
Table 10.10: PCM Slave Timing (79)
Table 10.11: PSKEY_PCM_CONFIG32 Description (82)
Table 10.12: PSKEY_PCM_LOW_JITTER_CONFIG Description (83)
Table 10.13: Pin States of BlueCore4-ROM on Reset (86)
Table 15.1: Soldering Profile Zones (90)
Table 17.1: Reel Dimensions (95)
Table 17.2: Diameter Dependent Dimensions (95)
List of Equations
Equation 10.1: Output Voltage with Load Current ≤ 10mA (52)
Equation 10.2: Output Voltage with No Load Current (52)
Equation 10.3: Load Capacitance (58)
Equation 10.4: Trim Capacitance (58)
Equation 10.5: Frequency Trim (58)
Equation 10.6: Pullability (58)
Equation 10.7: Transconductance Required for Oscillation (59)
Equation 10.8: Equivalent Negative Resistance (59)
Equation 10.9: Baud Rate (64)
Equation 10.10: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock (81)
Equation 10.11: PCM_SYNC Frequency Relative to PCM_CLK (81)
_?ìé`?êé?QJolj Product Data Sheet
Status Information
The status of this Data Sheet is Production Information.
CSR Product Data Sheets progress according to the following format:
Advance Information
Information for designers concerning CSR product in development. All values specified are the target values of
the design. Minimum and maximum values specified are only given as guidance to the final specification limits
and must not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-production Information
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not
be considered as the final values.
All electrical specifications may be changed by CSR without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
RoHS Compliance
BlueCore4-ROM devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the
Council on the Restriction of Hazardous Substance (RoHS).
Trademarks, Patents and Licenses
Unless otherwise stated, words and logos marked with ? or ? are trademarks registered or owned by
Cambridge Silicon Radio Limited or its affiliates. Bluetooth? and the Bluetooth logos are trademarks owned by
Bluetooth SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have
been trademarked by their respective owners.
Windows?, Windows 98?, Windows 2000?, Windows XP? and Windows NT? are registered trademarks of
the Microsoft Corporation.
OMAP? is a trademark of Texas Instruments Inc.
The publication of this information does not imply that any license is granted under any patent or other rights
owned by Cambridge Silicon Radio Limited.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
CSR’s products are not authorised for use in life-support or safety-critical applications
_?ìé`?êé?QJolj Product Data Sheet
1 Key Features
Radio ! Common TX/RX terminal simplifies external matching; eliminates external antenna switch ! BIST minimises production test time. No external trimming is required in production ! Full RF reference designs available ! Bluetooth v2.0 Specification compliant ! EDR v2.0.E.2 compliant Transmitter ! +6dBm RF transmit power with level control from
on-chip 6-bit DAC over a dynamic range >30dB ! Class 2 and Class 3 support without the need for an external power amplifier or TX/RX switch ! Class1 support using external power amplifier, with RF power controlled by an internal 8-bit DAC ! Supports DQPSK (2Mbps) and 8DPSK (3Mbps) modulation Receiver ! Integrated channel filters
! Digital demodulator for improved sensitivity and co-channel rejection
! Real time digitised RSSI available on HCI interface ! Fast AGC for enhanced dynamic range ! Supports DQPSK and 8DPSK modulation ! Channel classification Synthesiser ! Fully integrated synthesiser requires no external
VCO, varactor diode, resonator or loop filter ! Compatible with an external crystal or with an
external clock using sinusoidal or logic-level signals ! Accepts frequencies between 8 and 32MHz (in multiples of 250kHz); additionally accepts 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8
and 38.4MHz frequencies typically used in GSM and CDMA devices Auxiliary Features ! Crystal oscillator with built-in digital trimming ! Power management includes digital shut down, wake up commands with an integrated low power
oscillator for ultra-low power Park/Sniff/Hold mode ! ‘Clock request’ output to control an external clock Auxiliary Features (continued)
! On-chip linear regulator; 1.8V output from a 2.2 -
4.2V input
! Clock for low power mode can be either supplied
from an external 32kHz clock signal or an internal
oscillator
! Auto baud rate setting for different TCXO
frequencies
! Power-on-reset cell detects low supply voltage
! Arbitrary power supply sequencing permitted
! 8-bit ADC and DAC available to applications
Baseband and Software
! Internal 48Kbyte RAM, allows full speed data
transfer, mixed voice and data, and full piconet
operation, including all medium rate preset types
! Logic for forward error correction, header error
control, access code correlation, CRC,
demodulation, encryption bit stream generation,
whitening and transmit pulse shaping. Supports all
Bluetooth v2.0 features including eSCO and AFH
! Transcoders for A-law, μ-law and linear voice from
host and A-law, μ-law and CVSD voice over air Physical Interfaces
! Synchronous serial interface up to 4Mbaud for
system debugging
! UART interface with programmable baud rate up to
3Mbits/s with an optional bypass mode
! Full speed USB v2.0 interface supports OHCI and
UHCI host interfaces
! Synchronous bi-directional serial programmable
audio interface
! Optional I 2C? compatible interfaces
! Audio PCM interface
! Optional co-existence interfaces Bluetooth Stack
CSR’s Bluetooth Protocol Stack runs on the on-chip
MCU in a variety of configurations:
! Standard HCI (UART or USB)
! Fully embedded RFCOMM
! Customised builds with embedded application code
Package Options
! 84-ball VFBGA, 6 x 6mm x 1mm, 0.5mm pitch
_?ìé`?êé?QJolj Product Data Sheet
2 6 x 6mm VFBGA Package Information
2.1 BlueCore4-ROM Pinout Diagram
Orientation from top of device
A B C D E F G H J K 12345678910
A1A2A3A4A5A6A7A8A9A10
B1B2B3B4B5B6B7B8B9B10
C1C2C3C4C5C6C7C8C9C10
D1D2D3D8D9D10
E1E2E3E8E9E10
F1F2F3F8F9F10
G1G2G3G8G9G10
H1H2H3H4H5H6H7H8H9H10
J1J2J3J4J5J6J7J8J9J10
K1K2K3K4K5K6K7K8K9K10
Figure 2.1: BlueCore4-ROM Device Pinout
_?ìé`?êé?QJolj Product Data Sheet
2.2 Device Terminal Functions Radio Ball Pad Type Description
RF_IN D1 Analogue Single-ended receiver input
PIO[0]/RXEN B1 Bi-directional with
programmable strength internal pull-up/down Control output for external TX/RX switch (if
fitted)
PIO[1]/TXEN B2 Bi-directional with
programmable strength internal pull-up/down Control output for external PA (if fitted)
TX_A F1 Analogue Transmitter output/switched receiver input
TX_B E1 Analogue Complement of TX_A
AUX_DAC D3 Analogue Voltage DAC output
Synthesiser and
Oscillator Ball Pad Type Description
XTAL_IN K3 Analogue For crystal or external clock input
XTAL_OUT J3 Analogue Drive for crystal
USB and UART Ball Pad Type Description
UART_TX J10 CMOS output, tri-state with
weak internal pull-up UART data output active high
UART_RX H9 CMOS input with weak
internal pull-down UART data input active high
UART_RTS H7 CMOS output, tri-state with
weak internal pull-up UART request to send active low
UART_CTS H8 CMOS input with weak
internal pull-down UART clear to send active low
USB_DP J8 Bi-directional USB data plus with selectable internal
1.5k Ω p ull-up resistor
USB_DN K8 Bi-directional USB data minus
PCM Interface Ball Pad Type Description
PCM_OUT G8 CMOS output, tri-state with
weak internal pull-down Synchronous data output
PCM_IN G9 CMOS input, with weak
internal pull-down Synchronous data input
PCM_SYNC G10 Bi-directional with weak
internal pull-down Synchronous data sync
PCM_CLK H10 Bi-directional with weak
internal pull-down Synchronous data clock
_?ìé`?êé?QJolj Product Data Sheet
Test and Debug Ball Pad Type Description
RESET C7 CMOS input with weak internal pull-down Reset if high. Input debounced, so must be
high for >5ms to cause a reset
RESETB D8 CMOS input with weak internal pull-up Reset if low. Input debounced, so must be
low for >5ms to cause a reset
SPI_CSB C9 CMOS input with weak internal pull-up Chip select for Serial Peripheral Interface,
active low
SPI_CLK C10 CMOS input with weak
internal-pull-down Serial Peripheral Interface clock
SPI_MOSI C8 CMOS input with weak
internal pull-down Serial Peripheral Interface data input
SPI_MISO B9 CMOS output, tri-state with
weak internal pull-down Serial Peripheral Interface data output
TEST_EN C6 CMOS input with strong
internal pull-down For test purposes only (leave unconnected)
PIO Port Ball Pad Type Description
PIO[2] B3 Bi-directional with
programmable strength internal pull-up/down
Programmable input/output line
PIO[3] B4 Bi-directional with
programmable strength internal pull-up/down
Programmable input/output line
PIO[4] E8 Bi-directional with programmable strength internal pull-up/down Programmable input/output line or optionally
BT_Priority/Ch_Clk output for co-existence
signalling
PIO[5] F8 Bi-directional with programmable strength internal pull-up/down
Programmable input/output line or optionally
BT_Active output for co-existence signalling
PIO[6] F10 Bi-directional with programmable strength internal pull-up/down Programmable input/output line or optionally
WLAN_Active/Ch_Data input for
co-existence signalling
PIO[7] F9 Bi-directional with
programmable strength internal pull-up/down
Programmable input/output line
PIO[8] C5 Bi-directional with
programmable strength internal pull-up/down
Programmable input/output line
PIO[9] C3 Bi-directional with
programmable strength internal pull-up/down
Programmable input/output line
PIO[10] C4 Bi-directional with
programmable strength internal pull-up/down
Programmable input/output line
PIO[11] E3 Bi-directional with
programmable strength internal pull-up/down
Programmable input/output line
AIO[0] H4 Bi-directional Programmable input/output line
AIO[1] H5 Bi-directional Programmable input/output line
AIO[2] J5 Bi-directional Programmable input/output line
_?ìé`?êé?QJolj Product Data Sheet
Power Supplies and
Control Ball Pad Type Description
VREG_IN K6 Linear regulator input Linear regulator voltage input (1)
VREG_EN K5 Input High or not connected to enable active
regulator. VSS to disable regulator (1)
VDD_USB K9 VDD Positive supply for UART/USB and AIO ports
VDD_PIO A3 VDD Positive supply for PIO and AUX DAC (2)
VDD_PADS D10 VDD Positive supply for all other digital
input/output ports (3)
VDD_CORE E10 VDD Positive supply for internal digital circuitry
VDD_RADIO C1, C2 VDD Positive supply for RF circuitry
VDD_VCO H1 VDD Positive supply for VCO and synthesiser
circuitry
VDD_ANA K4 VDD/Linear regulator output Positive supply for analogue circuitry and
1.8V regulated output
VSS_PADS A1, A2,
D9, J9, K10
VSS Ground connections for input/output
VSS_CORE E9 VSS Ground connection for internal digital
circuitry
VSS_RADIO D2, E2, F2 VSS Ground connections for RF circuitry
VSS_VCO G1, G2 VSS Ground connections for VCO and
synthesiser
VSS_ANA J2, J4, K2 VSS Ground connections for analogue circuitry
VSS F3 VSS Ground connection for internal package
shield
Ball Description
Unconnected
Terminals A4, A5, A6, A7, A8, A9, A10, B5, B6,
B7, B8, B10, G3, H2, H3, H6, J1, J6, J7, K1, K7
Leave unconnected
Notes:
(1) To enable the regulator the VREG_EN pin needs to be either pulled high or left unconnected. This
keeps compatibility with BlueCore2-ROM as the corresponding pin on BlueCore2-ROM was designated
as a not connect pin. In this situation the BlueCore4-ROM regulator is permanently on replicating the
BlueCore2-ROM that has no regulator enable pin.
(2) Positive supply for PIO[3:0] and PIO[11:8]
(3) Positive supply for SPI/PCM ports and PIO[7:4]
_?ìé`?êé?QJolj Product Data Sheet
3 Electrical Characteristics Absolute Maximum Ratings
Rating Min Max Storage Temperature -40°C +150°C
Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA
and VDD_CORE -0.4V 2.2V
Supply Voltage: VDD_PADS, VDD_PIO and VDD_USB -0.4V 3.7V
Supply Voltage: VREG_IN -0.4V 5.6V
Other Terminal Voltages VSS-0.4V VDD+0.4V
Recommended Operating Conditions
Operating Condition Min Max
Operating Temperature Range -40°C +105°C
Guaranteed RF performance range (1) -40°C +105°C
Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA
and VDD_CORE 1.7V 1.9V
Supply Voltage: VDD_PADS, VDD_PIO and VDD_USB 1.7V 3.6V
Supply Voltage: VREG_IN 2.2V 4.2V (2)
Note:
(1) Typical figures are given for RF performance between -40°C and +105°C
(2) The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is
not guaranteed above 4.2V
_?ìé`?êé?QJolj Product Data Sheet
Input/Output Terminal Characteristics
Linear Regulator
Min Typ Max Unit Normal Operation
Output Voltage (Iload = 70 mA)
1.70 1.78 1.85 V Temperature Coefficient -250 - +250 ppm/C
Output Noise (1)(2) - - 1 mV rms Load Regulation (Iload < 100 mA) - - 50 mV/A
Settling Time (1)(3) - - 50 μs
Maximum Output Current 70 - - mA
Minimum Load Current 5 - - μA
Input Voltage - - 4.2(6) V
Dropout Voltage (Iload = 70 mA) - - 350 mV
Quiescent Current (excluding Ioad, Iload < 1mA) 25 35 50 μA
Low Power Mode (4)
Quiescent Current (excluding Ioad, Iload < 100μA) 4 7 10 μA
Disabled Mode (5)
Quiescent Current 1.5 2.5 3.5 μA
Notes:
For optimum performance the VDD_ANA ball adjacent to VREG_IN should be used for regulator output.
(1) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors.
(2) Frequency range 100Hz to 100kHz
(3) 1mA to 70mA pulsed load
(4) Low power mode is entered and exited automatically when the chip enters/leaves Deep Sleep mode.
(5) Regulator is disabled when VREG_EN is pulled low. It is also disabled when VREG_IN is either open
circuit or driven to the same voltage as VDD_ANA.
(6) Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to
damage the rest of BlueCore4, but output regulation and other specifications are no longer guaranteed
at input voltages in excess of 4.2V.
Electrical Characteristics
_?ìé`?êé?QJolj Product Data Sheet
Input/Output Terminal Characteristics (Continued)
Digital Terminals Min Typ Max Unit
Input Voltage Levels
V IL input logic level low 2.7V ≤ VDD ≤ 3.0V -0.4 - +0.8 V
1.7V ≤ VDD ≤ 1.9V -0.4 - +0.4 V
V IH input logic level high 0.7VDD - VDD+0.4 V
Output Voltage Levels
V OL output logic level low,
(l o = 4.0mA), 2.7V ≤ VDD ≤ 3.0V
- - 0.2 V
V OL output logic level low,
(l o = 4.0mA), 1.7V ≤ VDD ≤ 1.9V
- - 0.4 V
V OH output logic level high,
(l o = -4.0mA), 2.7V ≤ VDD ≤ 3.0V VDD-0.2 - - V
V OH output logic level high,
(l o = -4.0mA), 1.7V ≤ VDD ≤ 1.9V
VDD-0.4 - - V
Input and Tri-state Current with:
Strong pull-up -100 -40 -10 μA
Strong pull-down +10 +40 +100 μA
Weak pull-up -5.0 -1.0 -0.2 μA
Weak pull-down +0.2 +1.0 +5.0 μA
I/O pad leakage current -1 0 +1 μA
C I Input Capacitance 1.0 - 5.0 pF
Input/Output Terminal Characteristics (Continued)
USB Terminals Min Typ Max Unit
VDD_USB for correct USB operation 3.1 3.6 V
Input threshold
V IL input logic level low - - 0.3VDD_USB V
V IH input logic level high 0.7VDD_USB - - V
Input leakage current
VSS_PADS < V IN < VDD_USB (1) -1 1 5 μA
C I Input capacitance 2.5 - 10.0 pF
Output Voltage levels to correctly terminated USB Cable
V OL output logic level low 0.0 - 0.2 V
V OH output logic level high 2.8 - VDD_USB V
_?ìé`?êé?QJolj Product Data Sheet Input/Output Terminal Characteristics (Continued)
Power-on reset
Min Typ Max Unit VDD_CORE falling threshold
1.40 1.50 1.60 V VDD_CORE rising threshold 1.50 1.60 1.70 V
Hysteresis 0.05 0.10 0.15 V
Input/Output Terminal Characteristics (Continued)
Auxiliary ADC Min Typ Max Unit
Resolution - - 8 Bits Input voltage range
(LSB size = VDD_ANA/255) 0 - VDD_ANA V
Accuracy INL -1 - 1 LSB
(Guaranteed monotonic) DNL 0 - 1 LSB
Offset -1 - 1 LSB Gain Error -0.8 - 0.8 %
Input Bandwidth - 100 - kHz
Conversion time - 2.5 - s
Sample rate (2) - - 700 Samples/s
Input/Output Terminal Characteristics (Continued)
Auxiliary DAC Min Typ Max Unit
Resolution - - 8 Bits
Average output step size (3) 12.5 14.5 17.0 mV
Output Voltage monotonic (2)
Voltage range (I O =
0mA) VSS_PADS - VDD_PIO V
Current range -10.0 - +0.1 mA
Minimum output voltage (I O =100μA) 0.0 - 0.2 V
Maximum output voltage (I O =10mA) VDD_PIO-0.3 - VDD_PIO V
High Impedance leakage current -1 - +1 μA
Offset -220 - +120 mV Integral non-linearity (3) -2 - +2 LSB
Settling time (50pF load) - - 10 μs
_?ìé`?êé?QJolj Product Data Sheet
Input/Output Terminal Characteristics (Continued)
Crystal Oscillator Min Typ Max Unit
Crystal frequency (4) 8.0 - 32.0 MHz Digital trim range (5) 5.0 6.2 8.0 pF Trim step size (5) - 0.1 - pF Transconductance 2.0 - - mS Negative resistance (6) 870 1500 2400 Ω
External Clock
Input frequency (7) 7.5 - 40.0 MHz Clock input level (8) 0.2 - VDD_ANA V pk-pk Allowable Jitter - - 15 ps rms
XTAL_IN input impedance - - - k Ω
XTAL_IN input capacitance - 7 - pF
Notes:
VDD_CORE, VDD_RADIO, VDD_LO and VDD_ANA are at 1.8V unless shown otherwise.
VDD_PADS, VDD_PIO and VDD_USB are at 3.0V unless shown otherwise.
The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT.
Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.
(1) Internal USB pull-up disabled
(2) Access of ADC is through VM function and therefore sample rate given is achieved as part of this
function
(3) Specified for an output voltage between 0.2V and VDD_PIO -0.2V
(4) Integer multiple of 250kHz
(5) The difference between the internal capacitance at minimum and maximum settings of the internal
digital trim
(6) XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF
(7) Clock input can be any frequency between 8 and 40MHz in steps of 250kHz and also covers the
CDMA/3G TCXO frequencies of 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz
(8) Clock input can either be sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or
above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN
_?ìé`?êé?QJolj Product Data Sheet
3.1 Power Consumption Operation Mode Connection Type UART Rate
(kbps) Average Unit
Page scan - 115.2 0.43 mA
Inquiry & page scan - 115.2 0.75 mA
ACL data transfer No traffic Master 115.2 3.71 mA
ACL data transfer With file transfer Master 115.2 8.44 mA
ACL data transfer No traffic Slave 115.2 15.1 mA
ACL data transfer With file transfer Slave 115.2 17.7 mA
ACL data transfer 40ms sniff Master 115.2 1.58 mA
ACL data transfer 1.28s sniff Master 115.2 0.14 mA eSCO EV3 – Setting S1 Master 38.4 24.0 mA
SCO connection HV1 Master 38.4 36.3 mA
SCO connection HV3 Master 38.4 17.8 mA
SCO connection HV3 30ms sniff Master 38.4 17.5 mA
ACL data transfer 40ms sniff Slave 38.4 1.39 mA
ACL data transfer 1.28s sniff Slave 38.4 0.26 mA
eSCO EV3 – Setting S1 Slave 38.4 22.7 mA
SCO connection HV1 Slave 38.4 35.7 mA
SCO connection HV3 Slave 38.4 22.7 mA
SCO connection HV3 30ms sniff Slave 38.4 16.8 mA
Parked 1.28s beacon Slave 38.4 0.19 mA
Standby Host connection (1) - 38.4 36 μA Reset (RESETB low)(1) - - 49 μA Note:
Conditions: 20°C, 3.15V supply into linear regulator
(1) Low power mode on the linear regulator is entered and exited automatically when the chip enters/leaves
Deep Sleep mode. For more information about the electrical characteristics of the linear regulator, see
section 3 in this document.
Radio Characteristics – Basic Data Rate
_?ìé`?êé?QJolj Product Data Sheet
4 Radio Characteristics – Basic Data Rate
BlueCore4-ROM meets the Bluetooth specification v2.0 + EDR when used in a suitable application circuit
between -40°C and +105°C.
TX output is guaranteed to be unconditionally stable over the guaranteed temperature range.
4.1 Temperature +20°C
4.1.1 Transmitter Radio Characteristics VDD = 1.8V Temperature = +20°C
Min Typ Max Bluetooth
Specification Unit
Maximum RF transmit power (1)(2) - 4.5 - -6 to +4(3) dBm Variation in RF power over temperature range with
compensation enabled (±)(4) - 1.5 - - dB
Variation in RF power over temperature range with
compensation disabled (±)(4) - 2.5 - - dB
RF power control range - 35 - ≥16 dB
RF power range control resolution (5) - 0.5 - - dB 20dB bandwidth for modulated carrier - 780 - ≤1000 kHz
Adjacent channel transmit power F=F 0 ± 2MHz (6)(7) - -35 - ≤-20 dBm
Adjacent channel transmit power F=F 0 ± 3MHz (6)(7) - -45 - ≤-40 dBm
Adjacent channel transmit power F=F 0 >± 3MHz (6)(7) - <-50 - ≤-40 dBm
Δf1avg “Maximum Modulation” - 165 - 140 Δf2max “Minimum Modulation” - 152 - 115 kHz Δf1avg/Δf2avg - 0.98 - ≥0.80 - Initial carrier frequency tolerance - 8 - ±75 kHz Drift Rate - 7 - ≤20 kHz/ 50μs Drift (single slot packet) - 8 - ≤25 kHz Drift (five slot packet) - 9 - ≤40 kHz 2nd Harmonic Content - -45 - ≤30 dBm 3rd Harmonic Content - -50 - ≤30 dBm Notes: (1) BlueCore4-ROM firmware maintains the transmit power to be within the Bluetooth specification v2.0 + EDR limits. (2) Measurement made using a PSKEY_LC_MAX_TX_POWER setting corresponds to a PSKEY_LC_POWER_TABLE power table entry of 63. (3) Class 2 RF transmit power range, Bluetooth specification v2.0 + EDR. (4) To some extent these parameters are dependent on the matching circuit used, and its behaviour over temperature. Therefore these parameters may be beyond CSR’s direct control. (5) Resolution guaranteed over the range -5dB to -25dB relative to maximum power for TX Level >20. (6) Measured at F 0 = 2441MHz. (7) Up to three exceptions are allowed in v2.0 + EDR of the Bluetooth specification. BlueCore4-ROM is guaranteed to meet the ACP performance as specified by the Bluetooth specification v2.0 + EDR. Radio Characteristics – Basic Data Rate _?ìé`?êé?QJolj Product Data Sheet Radio Characteristics VDD = 1.8V Temperature = +20°C (Continued) Frequency (GHz) Min Typ Max Cellular Band Unit 0.869 – 0.894(1) - -125 - GSM 850 0.869 – 0.894(2) - -129 - CDMA 850 0.925 – 0.960(1) - -129 - GSM 900 1.570 – 1.580(3) - -135 - GPS 1.805 – 1.880(1) - -133 - GSM 1800 / DCS 1800 1.930 – 1.990(4) - -135 - PCS 1900 1.930 – 1.990(1) - -133 - GSM 1900 1.930 – 1.990(2) - -135 - CDMA 1900 2.110 – 2.170(2) - -131 - W-CDMA 2000 Emitted power in cellular bands measured at the unbalanced port of the balun. Output power = 4dBm 2.110 – 2.170(5) - -131 - W-CDMA 2000 dBm /Hz Notes: (1) Integrated in 200kHz bandwidth and then normalised to a 1Hz bandwidth. (2) Integrated in 1.2MHz bandwidth and then normalised to a 1Hz bandwidth. (3) Integrated in 1MHz bandwidth and then normalised to a 1Hz bandwidth. (4) Integrated in 30kHz bandwidth and then normalised to a 1Hz bandwidth. (5) Integrated in 5MHz bandwidth and then normalised to a 1Hz bandwidth.