THGBMDG5D1KBAIT A19nm 4GB e-MMC Ver5 0_E_rev0 1_131121
金士顿e MMC 5.1嵌入式多媒体卡（e
Embedded Multi-Media Card(e•MMC™ 5.1)EMMC16G-IB29-PE90EMMC32G-IB29-PE90EMMC64G-IB29-PE90v1.0Product Features•Packaged managed NAND flash memory with e•MMC™ 5.1 interface•Backward compatible with all prior e•MMC™ specification revisions•153-ball JEDEC FBGA RoHS Compliant package•Operating voltage range:o VCCQ = 1.8 V/3.3 Vo VCC = 3.3 V•Operating Temperature (T case) - 40C to +85C•Storage Temperature -55C to +85C•Compliant with e•MMC™ 5.1 JEDEC Standard Number JESD84-B51•Factory configured with pseudo Single Level Cell (pSLC) mode for enhanced reliability and performance•Factory configured with reliable writee•MMC™ Specific Feature Support•High-speed e•MMC™ protocol•Variable clock frequencies of 0-200MHz•Ten-wire bus interface (clock, 1 bit command, 8 bit data bus) with an optional hardware reset •Supports three different data bus widths: 1 bit(default), 4 bits, 8 bits•Bus Modes:o Single data transfer rate: up to 52MB/s (using 8 parallel data lines at 52MHz)o Dual data rate mode (DDR-104) : up to 104MB/s @ 52MHzo High speed, single data rate mode (HS-200) : up to 200MB/s @ 200MHzo High speed, dual data rate mode (HS-400) : up to 400MB/s @ 200MHz•Supports alternate boot operation mode to provide a simple boot sequence methodo Supports SLEEP/AWAKE (CMD5)o Host initiated explicit sleep mode for power saving•Enhanced write protection with permanent and partial protection options•Multiple user data partition with enhanced attribute for increased reliability•Error free memory accesso Cyclic Redundancy Code (CRC) for reliable command and data communicationo Internal error correction code (ECC) for improved data storage integrityo Internal enhanced data management algorithmo Data protection for sudden power failure during program operations•Securityo Secure bad block erase commandso Enhanced write protection with permanent and partial protection options•Power off notification for sleep•Field firmware update (FFU)•Production state awareness•Device health report•Command queuing•Enhanced strobe•Cache flushing report•Cache barrier•Background operation control & High Priority Interrupt (HPI)•RPMB throughput improvement•Secure write protection•Pre EOL information•Optimal sizeProduct DescriptionKingston’s e•MMC™ products conform to the JEDEC e•MMC™ 5.1standard. These devices are an ideal universal storage solution for many commercial and industrial applications. In a single integrated packaged device, e•MMC™ combines triple-level cell (TLC) NAND flash memory with an onboard e•MMC™ controller, providing an industry standard interface to the host system. The integrated e•MMC™ controller directly manages NAND flash media which relieves the host processor of these tasks, including flash media error control, wear-leveling, NAND flash management and performance optimization. Future revision to the JEDEC e•MMC™ standard will always maintain backward compatibility. The industry standard interface to the host processor ensures compatibility across future NAND flash generations as well, easing product sustainment throughout the product life cycle. ConfigurationsKingston’s e•MMC™ products support a variety of configurations that allow the e•MMC™ device to be tailored to your specific application needs. The most popular configurations described below are each offered under standard part numbers.Standard TLC – By default the e•MMC™ device is configured with the NAND flash in a standard TLC mode. This configuration provides reasonable performance and reliability for many applications. Pseudo Single Level Cell (pSLC) – The TLC NAND flash in the Kingston e•MMC™ device can be configured to further improve device endurance, data retention, reliability and performance over the standard TLC configuration. This is done by converting the NAND TLC cells to a pseudo single level cell (SLC) configuration. In this configuration, along with the performance and reliability gains, the device capacity is reduced by 2/3 of the capacity. This one-time configuration is achieved by setting the e•MMC™ enhanced attribute for the hardware partition.Kingston e•MMC™ can be ordered preconfigured with the option of reliable write or pSLC at no additional cost. Standard TLC devices can also be one-time configured in-field by following the procedures outlined in the JEDEC e•MMC™ specification. The JEDEC e•MMC™ specification allows for many additional configurations such as up to 4 additional general purpose (GPn) hardware partitions each with the option to support pSLC and reliable write. Additionally, Kingston provides a content loading service that can streamline your product assembly while reducing production costs. For more information, contact your Kingston representative.Kingston e•MMC™ devices are fully compliant with the JEDEC Standard Specification No. JESD84-B51. This datasheet provides technical specifications for Kingston’s family of e•MMC™ devices. Refer to the JEDEC e•MMC™ standard for specific information related to e•MMC™ device function and operation. See: /sites/default/files/docs/JESD84-B51.pdfe•MMC™ Mode and ControllerTLC mode using PS8229 - Leading edge 3D NAND flash technology in TLC mode rated to 3,000 endurance cycles.- Strong data protection with LDPC Error control- Improved data integrity with end-to-end data protection.pSLC mode using PS8229 - Leading edge 3D NAND flash technology in pSLC mode.- Strong data protection with LDPC Error control- Improved data integrity with end-to-end data protection.Part NumberingFigure 1 – Part Number FormatEMMC 16G - xxxx - PE90A B C DPart Number FieldsA: Product Family : EMMCB: Device Capacity : Available capacities of 16GB – 64GBC: Hardware Revision and ConfigurationD: Device Firmware Revision and ConfigurationTable 1 - Device SummaryDevice PerformanceTable 2 below provides sequential read and write speeds for all capacities. Performance numbers can vary under different operating conditions. Values are given at HS400 bus mode. Contact your Kingston Representative for performance numbers using other bus modes.Power ConsumptionDevice current consumption for various device configurations is defined in the power class fields of the EXT_CSD register. Power consumption values are summarized in Table 3 below.Device and Partition CapacityThe device NAND flash capacity is divided across two boot partitions (2048 KB each), a Replay Protected Memory Block (RPMB) partition (512 KB), and the main user storage area. Four additional general purpose storage partitions can be created from the user partition. These partitions can be factory preconfigured or configured in-field by following the procedure outlined in section 6.2 of the JEDEC e•MMC™ specification JESD84-B51. A small portion of the NAND storage capacity is used for the storage of the onboard controller firmware and mapping tables. Additionally, several NAND blocks are held in reserve to boost performance and extend the life of the e•MMC™ device. Table 4 identifies the specific capacity of each partition. This information is reported in the device EXT_CSD register. The contents of this register are also listed in the Appendix.e•MMC™ Bus ModesKingston e•MMC™ devices support all bus modes defined in the JEDEC e•MMC™ 5.1 specification. These modes are summarized in Table 6 below.Signal DescriptionTable 7 - e•MMC™ Signals Name Type DescriptionCLK I Clock: Each cycle of this signal directs a one bit transfer on the command and either a one bit (1x) or a two bits transfer (2x) on all the data lines. The frequency may vary between zero and the maximum clock frequency.DAT[7:0] I/O/PP Data: These are bidirectional data channels. The DAT signals operate in push-pull mode. These bidirectional signals are driven by either the e•MMC™ device or the host controller. By default, after power up or reset, only DAT0 is used for data transfer. A wider data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-DAT7, by the e•MMC™ host controller. The e•MMC™ device includes internal pull-ups for data lines DAT1-DAT7. Immediately after entering the 4-bit mode, the device disconnects the internal pull ups of lines DAT1, DAT2, and DAT3. Correspondingly, immediately after entering to the 8-bit mode, the device disconnects the internal pull-ups of lines DAT1–DAT7.CMD I/O/PP/OD Command: This signal is a bidirectional command channel used for device initialization and transfer of commands. The CMD signal has two operation modes: open-drain for initialization mode, and push-pull for fast command transfer. Commands are sent from the e•MMC™ host controller to the e•MMC™ device and responses are sent from the device to the host.DS O This signal is generated by the device and used for output in HS400 mode. The frequency of this signal follows the frequency of CLK. For data output each cycle of this signal directs two bits transfer(2x) on the data - one bit for positive edge and the other bit for negative edge. For CRC status response output and CMD response output (enabled only HS400 enhanced strobe mode), the CRC status and CMD Response are latched on the positive edge only, and don't care on the negative edge.RST_n I Hardware Reset: By default, hardware reset is disabled and must be enabled in the EXT_CSD register if used. Otherwise, it can be left un-connected.RFU - Reserved for future use: These pins are not internally connected. Leave floatingNC - Not Connected: These pins are not internally connected. Signals can be routed through these balls to ease printed circuit board design. See Kingston’s Design Guidelines for further details.VSF - Vendor Specific Function: These pins are not internally connectedVddi - Internal Voltage Node: Note that this is not a power supply input. This pin provides access to the output of an internal voltage regulator to allow for the connection of an external Creg capacitor. See Kingston’s Design Guidelines for further details.Vcc S Supply voltage for core Vccq S Supply voltage for I/ODesign GuidelinesDesign guidelines are outlined in a separate document. Contact your Kingston Representative for more information.Package DimensionsFigure 2 – Package DimensionsFigure 3 – Ball Pattern DimensionsBall Assignment (153 ball)Table 8 – Ball Assignment, Top View (HS400)1 2 3 4 5 6 7 8 9 10 11 12 13 14A NC NC DAT0 DAT1 DAT2 Vss RFU NC NC NC NC NC NC NC AB NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC BC NC Vddi NC Vssq NC Vccq NC NC NC NC NC NC NC NC CD NC NC NC NC NC NC NC DE NC NC NC RFU Vcc Vss VSF VSF VSF NC NC NC EF NC NC NC Vcc VSF NC NC NC FG NC NC RFU Vss VSF NC NC NC GH NC NC NC DS Vss NC NC NC H J NC NC NC Vss Vcc NC NC NC J K NC NC NC RST_n RFU RFU Vss Vcc VSF NC NC NC K L NC NC NC NC NC NC L M NC NC NC Vccq CMD CLK NC NC NC NC NC NC NC NC M N NC Vssq NC Vccq Vssq NC NC NC NC NC NC NC NC NC N P NC NC Vccq Vssq Vccq Vssq RFU NC NC RFU NC NC NC NC P1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note: VSF, RFU and NC balls are not electrically connected. RFU balls may be defined with functionality by the Joint Electron Device Engineering Council (JEDEC) in future revisions of the e•MMC™ standard. Please refer to Kingston’s design guidelines for more info.Device MarkingFigure 4 - EMMC Package Marking240xxxx-xxx.xxxxYYWW PPPPPPPPxxxxxxx-xxxx2xxxxxxTAIWANKingston Logo240xxxx-xxx.xxxx：Internal control numberYYWW：Date code (YY– Last 2 digits ofyear, WW- Work week)PPPPPPPP： Internal control numberxxxxxxx-xxxx Sales P/N2xxxxxx : Internal control numberCountry：TAIWANCard Identification Register (CID)The Card Identification (CID) register is a 128-bit register that contains device identification information used during the e•MMC™ protocol device identification phase. Refer to JEDEC Standard Specification No.JESD84-B51 for details.Field Byte ValueMID [127:120] 0x70reserved [119:114] 0x00CBX [113:112] 0x01OID [111:104] 0x00PNM [103:56 ] IB2916(16G) IB2932(32G) IB2964(64G)PRV [ 55:48 ] 0x90PSN [ 47:16 ] RandomMDT [ 15:8 ] month, yearCRC [ 7:1 ] Follows JEDEC Standard reserved [ 0:0 ] 0x01Card Specific Data Register [CSD]The Card-Specific Data (CSD) register provides information on how to access the contents stored in e•MMC™. The CSD registers are used to define the error correction type, maximum data access time, data transfer speed, data format…etc. For details, refer to section 7.3 of the JEDEC Standard Specification No.JESD84-B51.Field Byte ValueCSD_Structure [127:126] 0x03 (V2.0)SPEC_VER [125:122] 0x04 (V4.0~4.2)reserved [121:120] 0x00TAAC [119:112] 0x4F (40ms)NSAC [111:104] 0x01TRAN_SPEED [103:96 ] 0x32 (26Mbit/s)CCC [ 95:84 ] 0x0F5READ_BL_LEN [ 83:80 ] 0x09 (512 Bytes)READ_BL_PARTIAL [ 79:79 ] 0x00WRITE_BLK_MISALIGN [ 78:78 ] 0x00READ_BLK_MISALIGN [ 77:77 ] 0x00DSR_IMP [ 76:76 ] 0x00reserved [ 75:74 ] 0x00C_SIZE [ 73:62 ] 0xFFFVDD_R_CURR_MIN [ 61:59 ] 0x07 (100mA)VDD_R_CURR_MAX [ 58:56 ] 0x07 (200mA)VDD_W_CURR_MIN [ 55:53 ] 0x07 (100mA)VDD_W_CURR_MAX [ 52:50 ] 0x07 (200mA)C_SIZE_MULT [ 49:47 ] 0x07 (512 Bytes)ERASE_GRP_SIZE [ 46:42 ] 0x1FERASE_GRP_MULT [ 41:37 ] 0x1FWP_GRP_SIZE [ 36:32 ] 0x0FWP_GRP_ENABLE [ 31:31 ] 0x01DEFAULT_ECC [ 30:29 ] 0x00R2W_FACTOR [ 28:26 ] 0x02WRITE_BL_LEN [ 25:22 ] 0x09 (512 Bytes)WRITE_BL_PARTIAL [ 21:21 ] 0x00reserved [ 20:17 ] 0x00CONTENT_PROT_APP [ 16:16 ] 0x00FILE_FORMAT_GRP [ 15:15 ] 0x00COPY [ 14:14 ] 0x00PERM_WRITE_PROTECT [ 13:13 ] 0x00TMP_WRITE_PROTECT [ 12:12 ] 0x00FILE_FORMAT [ 11:10 ] 0x00Field Byte ValueECC [ 9:8 ] 0x00CRC [ 7:1 ] Follow JEDEC Standard reserved [ 0:0 ] 0x01Extended Card Specific Data Register [EXT_CSD]The Extended CSD register defines the Device properties and selected modes. It is 512 bytes long. The most significant 320 bytes are the Properties segment, which defines the Device capabilities and cannot be modified by the host. The lower 192 bytes are the Modes segment, which defines the configuration the Device is working in. These modes can be changed by the host by means of the SWITCH command. For details, refer to section 7.4 of the JEDEC Standard Specification No.JESD84-B51.Field Byte ValueReserved [511:506] 0EXT_SECURITY_ERR [505:505] 0x00S_CMD_SET [504:504] 0x01HPI_FEATURES [503:503] 0x01BKOPS_SUPPORT [502:502] 0x01MAX_PACKED_READS [501:501] 0x3CMAX_PACKED_WRITES [500:500] 0x20DATA_TAG_SUPPORT [499:499] 0x01TAG_UNIT_SIZE [498:498] 0x03TAG_RES_SIZE [497:497] 0x00CONTEXT_CAPABILITIES [496:496] 0x05LARGE_UNIT_SIZE_M1 [495:495] 0x17(16G) 0x2F(32G) 0x5F(64G)EXT_SUPPORT [494:494] 0x03 SUPPORTED_MODES [493:493] 0x01FFU_FEATURES [492:492] 0x00 OPERATION_CODE_TIMEOUT [491:491] 0x00FFU_ARG [490:487] 65535 BARRIER_SUPPORT [486:486] 0x01Reserved [485:309] 0CMDQ_SUPPORT [308:308] 0x01CMDQ_DEPTH [307:307] 0x0FReserved [306:306] 0x00 NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED [305:302] 0 VENDOR_PROPRIETARY_HEALTH_REPORT [301:270] 0 DEVICE_LIFE_TIME_EST_TYP_B [269:269] 0x01DEVICE_LIFE_TIME_EST_TYP_A [268:268] 0x01PRE_EOL_INFO [267:267] 0x01 OPTIMAL_READ_SIZE [266:266] 0x01OPTIMAL_WRITE_SIZE [265:265] 0x08Field Byte Value OPTIMAL_TRIM_UNIT_SIZE [264:264] 0x01 DEVICE_VERSION [263:262] 0FIRMWARE_VERSION [261:254] 0x90 PWR_CL_DDR_200_360 [253:253] 0x00 CACHE_SIZE [252:249] 1024 GENERIC_CMD6_TIME [248:248] 0x32 POWER_OFF_LONG_TIME [247:247] 0xFF BKOPS_STATUS [246:246] 0x00 CORRECTLY_PRG_SECTORS_NUM [245:242] 0 INI_TIMEOUT_AP [241:241] 0x64 CACHE_FLUSH_POLICY [240:240] 0x01 PWR_CL_DDR_52_360 [239:239] 0x00 PWR_CL_DDR_52_195 [238:238] 0x00PWR_CL_200_195 [237:237] 0x00PWR_CL_200_130 [236:236] 0x00 MIN_PERF_DDR_W_8_52 [235:235] 0x00 MIN_PERF_DDR_R_8_52 [234:234] 0x00 Reserved [233:233] 0x00TRIM_MULT [232:232] 0x11(16G) 0x11(32G) 0x22(64G)SEC_FEATURE_SUPPORT [231:231] 0x55 SEC_ERASE_MULT [230:230] 0xF7 SEC_TRIM_MULT [229:229] 0xF7 BOOT_INFO [228:228] 0x07Reserved [227:227] 0x00 BOOT_SIZE_MULT [226:226] 0x20ACC_SIZE [225:225] 0x07(16G) 0x08(32G) 0x09(64G)HC_ERASE_GRP_SIZE [224:224] 0x01ERASE_TIMEOUT_MULT [223:223] 0x11(16G) 0x11(32G) 0x22(64G)REL_WR_SEC_C [222:222] 0x01HC_WP_GRP_SIZE [221:221] 0x10 S_C_VCC [220:220] 0x08S_C_VCCQ [219:219] 0x08 PRODUCTION_STATE_AWARENESS_TIMEOUT [218:218] 0x14 S_A_TIMEOUT [217:217] 0x15 SLEEP_NOTIFICATION_TIME [216:216] 0x0FField Byte ValueSEC_COUNT [215:212] 10207232 (16G) 20414464 (32G) 40828928 (64G)SECURE_WP_INFO [211:211] 0x01 MIN_PERF_W_8_52 [210:210] 0x08 MIN_PERF_R_8_52 [209:209] 0x08 MIN_PERF_W_8_26_4_52 [208:208] 0x08 MIN_PERF_R_8_26_4_52 [207:207] 0x08 MIN_PERF_W_4_26 [206:206] 0x08 MIN_PERF_R_4_26 [205:205] 0x08 Reserved [204:204] 0x00 PWR_CL_26_360 [203:203] 0x00 PWR_CL_52_360 [202:202] 0x00 PWR_CL_26_195 [201:201] 0x00 PWR_CL_52_195 [200:200] 0x00 PARTITION_SWITCH_TIME [199:199] 0xFF OUT_OF_INTERRUPT_TIME [198:198] 0xFF DRIVER_STRENGTH [197:197] 0x1F DEVICE_TYPE [196:196] 0x57 Reserved [195:195] 0x00 CSD_STRUCTURE [194:194] 0x02 Reserved [193:193] 0x00 EXT_CSD_REV [192:192] 0x08 CMD_SET [191:191] 0x00Reserved [190:190] 0x00 CMD_SET_REV [189:189] 0x00 Reserved [188:188] 0x00 POWER_CLASS [187:187] 0x00 Reserved [186:186] 0x00HS_TIMING [185:185] 0x01 STROBE_SUPPORT [184:184] 0x01 BUS_WIDTH [183:183] 0x02Reserved [182:182] 0x00 ERASED_MEM_CONT [181:181] 0x00 Reserved [180:180] 0x00 PARTITION_CONFIG [179:179] 0x00 BOOT_CONFIG_PROT [178:178] 0x00 BOOT_BUS_CONDITIONS [177:177] 0x00 Reserved [176:176] 0x00 ERASE_GROUP_DEF [175:175] 0x00 BOOT_WP_STATUS [174:174] 0x00C - 4Field Byte Value BOOT_WP [173:173] 0x00 Reserved [172:172] 0x00 USER_WP [171:171] 0x00 Reserved [170:170] 0x00 FW_CONFIG [169:169] 0x00 RPMB_SIZE_MULT [168:168] 0x20 WR_REL_SET [167:167] 0x00 WR_REL_PARAM [166:166] 0x15 SANITIZE_START [165:165] 0x00 BKOPS_START [164:164] 0x00 BKOPS_EN [163:163] 0x00 RST_n_FUNCTION[162:162] 0x00 HPI_MGMT[161:161] 0x00 PARTITIONING_SUPPORT [160:160] 0x07 MAX_ENH_SIZE_MULT [159:157] 623(16G) 1246(32G) 2492(64G) PARTITIONS_ATTRIBUTE[156:156] 0x01 PARTITION_SETTING_COMPLETED[155:155] 0x01 GP_SIZE_MULT_4 [154:152] 0 GP_SIZE_MULT_3 [151:149] 0 GP_SIZE_MULT_2 [148:146] 0 GP_SIZE_MULT_1[145:143] 0 ENH_SIZE_MULT[142:140] 623(16G) 1246(32G) 2492(64G)ENH_START_ADDR[139:136] 0 Reserved[135:135] 0x00 SEC_BAD_BLK_MGMNT[134:134] 0x00 PRODUCTION_STATE_AWARENESS[133:133] 0x00 TCASE_SUPPORT [132:132] 0x00 PERIODIC_WAKEUP[131:131] 0x00 PROGRAM _CID_CSD_DDR_SUPPORT[130:130] 0x01 Reserved[129:128] 0 VENDOR_SPECIFIC_FIELD[127:67 ] 538968064ERROR_CODE [ 66:65 ] 0 ERROR_TYPE[ 64:64 ] 0x00 NATIVE_SECTOR_SIZE [ 63:63 ] 0x00 USE_NATIVE_SECTOR [ 62:62 ] 0x00 DATA_SECTOR_SIZE [ 61:61 ] 0x00 INI_TIMEOUT_EMU[ 60:60 ] 0x00C - 5FieldByte Value CLASS_6_CTRL [ 59:59 ] 0x00 DYNCAP_NEEDED[ 58:58 ] 0x00 EXCEPTION_EVENTS_CTRL [ 57:56 ] 0 EXCEPTION_EVENTS_STATUS [ 55:54 ] 0 EXT_PARTITIONS_ATTRIBUTE[ 53:52 ] 0 CONTEXT_CONF[ 51:37 ] 0 PACKED_COMMAND_STATUS [ 36:36 ] 0x00 PACKED_FAILURE_INDEX [ 35:35 ] 0x00 POWER_OFF_NOTIFICATION[ 34:34 ] 0x00 CACHE_CTRL [ 33:33 ] 0x00 FLUSH_CACHE [ 32:32 ] 0x00 BARRIER_CTRL [ 31:31 ] 0x00 MODE_CONFIG[ 30:30 ] 0x00 MODE_OPERATION_CODES[ 29:29 ] 0x00 Reserved [ 28:27 ] 0 FFU_STATUS[ 26:26 ] 0x00 PRE_LOADING_DATA_SIZE [ 25:22 ] 0MAX_PRE_LOADING_DATA_SIZE[ 21:18 ] 3304106(16G) 6608213(32G) 13216426(64G)PRODUCT_STATE_AWARENESS_ENABLEMENT[ 17:17 ] 0x01 SECURE_REMOVAL_TYPE[ 16:16 ] 0x01 CMDQ_MODE_EN[ 15:15 ] 0x00 Reserved[ 14:0 ]。
莫贾UC-8580系列双核ARM Cortex-A7高速训练到地面计算机说明书
UC-8580SeriesArm Cortex-A7dual-core1GHz train-to-ground computers with4Mini PCIe expansion slots for wireless modulesFeatures and Benefits•Complies with all EN50155mandatory test items1•Supports up to3WWAN connections and2SIM card slots per cellularmodule•Supports1WLAN(IEEE802.11a/b/g/n/ac)connection•Single-panel I/O design for reduced installation space and easiermaintenance•Front-side access panel for easy maintenance•Isolated24to110VDC power input with power-ignition function suitable forvehicle applications•EN50155Tx(-40to70°C)operating temperature for harsh environments•5-year warrantyCertificationsIntroductionMoxa’s UC-8580is an innovative computing platform designed specifically for transportation applications.The UC-8580is available with one of two different types of antenna connectors.The SMA model supports all SMA type connectors.The QMA model supports TNC connectors for GPS and QMA connectors for Wi-Fi/cellular modules,and has four slots for installing wireless modules.2Three slots support4G LTE modules,and one slot supports a Wi-Fi module.Each4G LTE module has two SIM card slots,which can be used to enable redundant cellular network communications or geo-fencing SIM card selection by leveraging the built-in Wireless Manager,a Moxa software utility for cellular and Wi-Fi management.The UC-8580uses an open platform based on Debian8with Linux kernel4.1,allowing solution providers to manage software packages via Debian’s APT(Advanced Packaging Tools),or develop software applications with Moxa’s API Library and GNU C Library.The UC-8580’s single-sided I/O design is ideal for vehicle applications,which typically do not have a lot of room for installing communications devices.The UC-8580also has an access panel on the front side,allowing users to install or change wireless modules,SIM cards,or mSATA cards without removing the entire unit from the wall after being mounted.The UC-8580can be used as a communication-centric computing platform for the following applications:•Vehicle-to-ground communication gateway•TCMS T2G(train-to-ground)gateway•Mobile condition monitoring unit•Ethernet Consist Network T2G gateway•Onboard wireless automated fare collection unit1.This product is suitable for rolling stock railway applications,as defined by the EN50155standard.For a more detailed statement,click here:/doc/specs/EN_50155_Compliance.pdf2.Wireless modules are sold separately.Please contact a Moxa sales representative for details.AppearanceSMA ModelQMA ModelSpecificationsComputerCPU Armv7Cortex-A7dual-core1GHz System Memory Pre-installed1GB DDR3LSupported OS Linux Debian8(Linux kernel v4.1)Storage Slot mSATA slots x1,internal mini-PCIe socketStorage Pre-installed8GB eMMCComputer InterfaceEthernet Ports Auto-sensing10/100/1000Mbps ports(M12X-coded)x2 Serial Ports RS-232/422/485ports x2,software-selectable(terminal block) USB3.0USB3.0hosts x1,type-A connectorsDigital Input DIs x3Digital Output DOs x3Expansion Slots mPCIe slots x4Wi-Fi Antenna Connector UC-8580-LX/8580-T-LX/8580-T-CT-LX:RP-SMA x3UC-8580-Q-LX/8580-T-Q-LX/8580-T-CT-Q-LX:QMA x3 Cellular Antenna Connector UC-8580-LX/8580-T-LX/8580-T-CT-LX:SMA x6UC-8580-Q-LX/8580-T-Q-LX/8580-T-CT-Q-LX:QMA x6 Number of SIMs6SIM Format MiniGPS Antenna Connector UC-8580-LX/8580-T-LX/8580-T-CT-LX:SMA x1UC-8580-Q-LX/8580-T-Q-LX/8580-T-CT-Q-LX:TNC x1 Console Port RS-232(TxD,RxD,GND),4-pin header output(115200,n,8,1) Input/Output InterfaceButtons Reset buttonDigital InputsChannel-to-Channel Isolation3K VDCConnector Screw-fastened Euroblock terminalCounter Frequency25HzDry Contact On:short to GNDOff:openI/O Mode DIPoints per COM3x channelSensor Type Wet contact(NPN or PNP)Wet Contact(DI to COM)On:10to30VDCOff:0to3VDCDigital OutputsConnector Screw-fastened Euroblock terminalCurrent Rating200mA per channelI/O Type SinkVoltage0to30VDCLED IndicatorsSystem Power x1System Ready x1Programmable x1Wireless Signal Strength Cellular/Wi-Fi x12LAN2per port(10/100/1000Mbps)Serial2per port(Tx,Rx)Serial SignalsRS-232TxD,RxD,RTS,CTS,DTR,DSR,DCD,GNDRS-422Tx+,Tx-,Rx+,Rx-,GNDRS-485-2w Data+,Data-,GNDRS-485-4w Tx+,Tx-,Rx+,Rx-,GNDGPS InterfaceHeading Accuracy0.3degreesIndustrial Protocols NMEA0183,version4.0(V2.3or V4.1configurable),UBX,RTCM Receiver Types72-channel u-blox M8engineTime Pulse0.25Hz to10MHzVelocity Accuracy0.05msPower ParametersInput Current 1.66A@24VDC,0.36A@110VDCInput Voltage24to110VDCPower Connector M12A-coded4-pin male connectorPower Consumption40W(max.)Physical CharacteristicsHousing MetalIP Rating IP40Dimensions(with ears)270x134x88mm(10.63x5.28x3.46in)Dimensions(without ears)220x134x88mm(8.66x5.28x3.46in)Weight Product only:2,200g(4.85lb)Installation Wall mountingProtection-CT models:PCB conformal coatingEnvironmental LimitsOperating Temperature Standard Models:-25to55°C(-13to131°F)Wide Temp.Models:-40to70°C(-40to158°F)Storage Temperature(package included)-40to85°C(-40to185°F)Ambient Relative Humidity5to95%(non-condensing)Standards and CertificationsEMC EN55032/24EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:6kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:20V/mIEC61000-4-4EFT:Power:2kV;Signal:2kVIEC61000-4-5Surge:Power:2kV;Signal:2kVIEC61000-4-6CS:10VIEC61000-4-8PFMFRailway EN50121-4EN50155Railway Fire Protection EN45545-2Safety EN60950-1UL60950-1Shock IEC60068-2-27,IEC61373,EN50155:2017 Vibration IEC60068-2-64,IEC61373,EN50155:2017 DeclarationGreen Product RoHS,CRoHS,WEEEWarrantyWarranty Period5yearsDetails See /warrantyPackage ContentsDevice1x UC-8580Series computerCable1x4-pin header to DB9console cable Documentation1x quick installation guide1x warranty cardDimensionsOrdering InformationModel Name CPU Antenna Connector Type Operating Temp.Conformal CoatingUC-8580-LX Armv7Cortex-A7dual-core1GHzSMA-25to55°C–UC-8580-T-LX Armv7Cortex-A7dual-core1GHzSMA-40to70°C–UC-8580-T-CT-LX Armv7Cortex-A7dual-core1GHzSMA-40to70°C✓UC-8580-Q-LX Armv7Cortex-A7dual-core1GHzQMA-25to55°C–UC-8580-T-Q-LX Armv7Cortex-A7dual-core1GHzQMA-40to70°C–UC-8580-T-CT-Q-LX Armv7Cortex-A7dual-core1GHzQMA-40to70°C✓Accessories(sold separately)Wi-Fi Wireless ModulesUC-8580-WLAN33-AC3transmitter3receiver Wi-Fi card module,3SMA connectors with cablesUC-8500-WLAN33-Q-AC3transmitter3receiver Wi-Fi card module,3QMA connectors with cablesCellular Wireless ModulesUC-8500-4GCat6-Q-APAC LTE Cat.6module for North America and Europe,2QMA connectors with cables,-40to60°Coperating temperatureUC-8500-4GCat6-Q-NAMEU LTE Cat.6module for North America and Europe,2QMA connectors with cables,-40to60°Coperating temperatureUC-8580-4GCat6-NAMEU LTE Cat.6module for North America and Europe,2SMA connectors with cables,-40to60°Coperating temperaturePower AdaptersPWR-24250-DT-S1Power adapter,90to264VAC,24VDC,2.5A DC loadPower CordsPWC-C13US-3B-183Power cord with United States(US)plug,1.83mPWC-C13CN-3B-183Power cord with three-prong China(CN)plug,1.83mPWC-C13AU-3B-183Power cord with Australian(AU)plug,1.83mPWC-C13EU-3B-183Power cord with Continental Europe(EU)plug,1.83mPWC-C13JP-3B-183Power cord with Japan(JP)plug,7A/125V,1.83mPWC-C13UK-3B-183Power cord with United Kingdom(UK)plug,1.83m©Moxa Inc.All rights reserved.Updated Nov23,2022.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。
HTC G19Raider 4GX710e突袭者刷机图文教程
HTC G19/Raider 4G/X710e/突袭者刷机图文教程当你入手HTC G19/Raider 4G/X710e/突袭者后，经过一段时间的把玩，一定会有这些疑问。
HTC G19/Raider 4G/X710e/突袭者如何解锁？HTC G19/Raider4G/X710e/突袭者如何刷机？HTC G19/Raider 4G/X710e/突袭者又该如何获取ROOT权限？而且苦于找不到相关的教程。
不用担心，通过此篇《HTCG19/Raider 4G/X710e/突袭者解锁、刷机、Root详细图文教程》，你会轻松掌握这些技巧。
一、HTC G19/Raider 4G/X710e/突袭者解锁教程自Sensation XE以后，HTC旗下搭载Android系统的智能手机都已经支持官方解锁，也就是解除Bootloader限制，这里我们就使用官方的解锁来给大家提供本次的教程。
第一步.注册ID绑定接受解锁文件邮箱首先点击打开/register，注册一个属于你自己的邮箱账号，解锁文件会发送到你的邮箱。
注册好之后登陆，网页不关闭，继续下一步。
第二步.电脑驱动的安装（已经在电脑中安装过驱动的，可以跳过这一步）1、首先插上手机数据线连接电脑，打开USB调试模式（设置-应用程序-开发-USB调试勾选）2、打开电脑的设备管理器（一般都是在桌面上右键我的电脑-管理-设备管理器）3、下载USB驱动解压到电脑，然后在设备管理器安装Android驱动，根据自己电脑情况选择版本。
4、驱动安装完毕之后如下图显示：5.接下来下载解锁.zip,并解压到电脑桌面6.点击开始-运行-输入CMD-回车，见下图7.接下来在CMD窗口输入cd 注意是cd+(空格),cd后面有个空格,然后把桌面上的解锁文件夹拖放到cmd对话框,回车8.接着键入以下命令：adb reboot-bootloader此时手机会重启到bootloader模式.手机上有一行红字fastboot usb字样表示手机与电脑连接正常.如果未出现.表示驱动安装未完成，此时应重新安装驱动。
MEMORY存储芯片THGBMHG8C4LBAU7中文规格书
FEATURES4GB– 128GBNAND FLASH MEMORYSPECIFICATIONS e •MMCCost Effective Mass Storage APPLICATIONS•Industrial•Consumer Electronics •Multimedia•Smart Metering & Intelligent LightingADVANTAGESHigh Interface speed (HS400BENEFITSEasy -to -integrate storage e•MMC TM is a family of advanced, highly efficient NAND flash memory with an integrated controller and enhanced memory management. Based on an interface standardized by JEDEC, Toshiba’s e•MMC offers a suitable solution for applications in which higher data volumes need to be stored in a cost-efficient way. It is fully compliant with the Multimedia Card Association (MMCA) high-speed memory interface standard.e•MMC – PRODUCT LISTe •MMC – SPECIALIZED VERSIONSe •MMC – DESIGN GUIDELINE & DESIGN CHECK SHEETTo support your e ·MMC design, Toshiba offers a design guideline and a design check sheet . The designguideline highlights some of the key topics to be considered when selecting and utilizing a Toshiba e ·MMC. The design check sheet can be used to give more detailed information about the individual usage scenario for the e ·MMC. Both files are available at your local Toshiba representative or a qualified distributor.e •MMC – ENHANCED USER DATA AREAToshiba 's e ·MMC products support the JEDEC compliant “Enhanced User Data Area ," also called “pseudo-SLC .” F or applications requiring the memory to perform with higher write/erase cycles than MLC NAND can offer, the e ·MMC provides the option to build a partition which offers “pseudo-SLC“ performance.INNOVATION IS OUR TRADITION: FLASH MEMORY AND MOREIn 1984, Toshiba developed a new type of semiconductor memory called flash memory, leading the industry into the next generation ahead of its competitors. Some time later in 1987, NAND flash memory was developed, and this has since been used in a variety of memory cards and electronic equipment. The NAND flash market has grown rapidly, with flash memory becoming an internationally standardized memory device. As the inventor of flash memory, Toshiba has carved out a path to a new era in which we are all able to carry videos, music and data with us wherever we go.Does your application require faster data throughput? T oshiba offers enhanced versions of its 16GB and 32GB e -MMC on demand. Please contact your Toshiba representative or qualified distributor for more information.Mouser ElectronicsAuthorized DistributorClick to View Pricing, Inventory, Delivery & Lifecycle Information:。
XGK-CPU 用户手册
如果在安装的环境中有大量的震动出现，请不要让PLC直 接的承受震动，否则，将会引起触电，火灾或者导致系统 不正常的运行.
不要让任何外部的金属碎末进入到产品的内部，这将会引 起触电，火灾或者不正常的运行.
第三章 综合规格 .......................................................................................................................................................................................................................... 3-1
注意
应当在符合PLC手册或者在标准的环境下使用PLC系统， 否则的话，这将会引起的触电，火灾，不正常的运行或者 引起电弧 .
在安装模块之前，请确保PLC的供应电源已经关闭，否则, 这将会引起触电或者导致产品的损坏。
请确保PLC系统中的每一个模块都是正确的安装，如果模 块的安装出现松动或者不正确的现象，这将会引起不正常 的运行，错误或者模块掉下.
在安装接线的时候请确保终端块上的所有螺丝都已经拧紧， 如果终端块上的螺丝有松动，这将会引起触电，火灾或者 导致系统的不正常运行.
* 请确保FG接线端子上使用3级接地方式，这是使用PLC的 基本要求，如果端子上的接地不正确，这将会导致系统的 不正常运行.
在接线的过程中不要让任何外部的金属碎末和线头进入到 产品的内部，否则这将会引起火灾，产品的损坏或者系统 的不正常运行.
MEMORY存储芯片THGBMNG5D1LBAIL中文规格书
[492]
FFU features
FFU_FEATURES
1
[491]
Operation codes timeout
OPERATION_CODES_TIMEOUT
1
[490:487] FFU Argument
FFU_ARG
4
[486]
Barrier support
BARRIER_SUPPORT
1
[485:309] Reserved
4
ORRECTLY_PROGRAMMED
[301:270] Vendor proprietary health report
VENDOR_PROPRIETARY 32
_HEALTH_REPORT
[269]
Device life time estimation type B
DEVICE_LIFE_TIME_EST_TYP_B
THGBMNG5D1LBAIL
Width Cell Type
2
R
4
R
2
R
8
R
8
R
8
R
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4
R
1
R
1
R
1
R
1
R
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R/W
1
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1
ICDPPCNEXUS MPC55xx MPC56xx In-Circuit Debugger
ICDPPCNEXUSMPC55xx / MPC56xx In-Circuit DebuggerQuick Start GuideCopyright 2009, P&E Microcomputer Systems, Inc. All rights reserved.Visit us on the web at Document Version HistoryVersion Date Notes1.0 21 Sep 2009 Initial versionCONTENTS1 Introduction (4)1.1 P&E Compatible Hardware (4)2 Getting Started (5)2.1 Connecting to your Target (5)2.2 Reset Script (6)2.3 Loading Data and Debug Information (7)2.4 CPU and Memory Windows (8)3 Debugging (10)3.1 GOTIL command (10)3.1 Stepping through C instructions (11)3.3 Setting and Reaching Breakpoints (12)3.4 Using Code Window Popup Debug Evaluation Hints (13)3.5 Using the Variables Window (15)3.6 Modifying a Variable (16)3.7 Using the Register Interpreter (17)3.8 Adding Register Field Descriptions to the Variables Window (20)1 IntroductionThis document is a step-by-step guide to using the P&E ICDPPCNEXUS in-circuit debugger software, which is compatible with Freescale MPC55xx / MPC56xx processors. This guide covers the most commonly used features of the debugger: loading binary & debug information, accessing CPU registers & memory, stepping code, setting breakpoints, and monitoring variables.1.1 P&E Compatible HardwareThe following lists the P&E hardware compatible with the ICDPPCNEXUS debugger software.P&E Part Number Interface to host PCCABPPCNEXUS Parallel (LPT) portUSB-ML-PPCNEXUS USB 2.0 (Backwards compatible with USB 1.1 ports) Cyclone MAX Serial (RS232) portUSB 1.1 (Upwards compatible with USB 2.0 ports)Ethernet2 Getting Started2.1 Connecting to your TargetUpon starting the debugger, the connection assistant dialog appears:•Use the “Interface” and “Port” drop-down menus to choose the P&E hardware interface connected between the PC and your target board.•The “Target CPU” setting can safely be left at the “Autodetect” setting for most users. If you experience problems connecting, you can try specifying the exact Freescale device that you are connecting to.• A BDM_SPEED parameter between 2 to 4 can typically be used.Processors running at slower clock speeds will require higher values.Click the Connect button, and ICDPPCNEXUS will attempt to contact the processor. Using the default debugger settings, ICDPPCNEXUS will establish communications and reset the processor.After establishing communications, the main debugger screen will appear, and a debugger reset script macro should automatically execute and complete.2.2 Reset ScriptThis section explains the initialization that the debugger, using a reset script macro file, performs on the processor. The user can view and modify all of the macro file's initialization tasks.The processor Boot Assist Module (BAM) would normally initialize the memory of the processor. However, when running the target application from the debugger, the BAM functionality is disabled. To account for this, the debugger must run a script file on reset. The script initializes the memory of the processor similar to the way in which the BAM would initialize the processor.If ICDPPCNEXUS is launched from the Freescale CodeWarrior IDE, the correct reset script file is automatically selected.If ICDPPCNEXUS is launched stand-alone, the reset script file may need to be configured. Several reset script macros are included with the ICDPPCNEXUS debugger and have a .mac extension. For detailed information, you can view each macro file using a simple text editor such as Notepad. The macro contents will contain useful comments, such as which devices are supported by that particular macro.To configure the debugger reset script macro, select the debugger Configuration menu, Automated Script Options dialog, shown here:2.3 Loading Data and Debug InformationIf ICDPPCNEXUS is launched from the Freescale CodeWarrior IDE, your code will automatically be downloaded to the processor.•RAM projects are loaded into the processor’s internal SRAM.•FLASH projects will invoke the CPROGPPCNEXUS Flash programming software to burn the code into the processor’s internal FLASH.The debug information is also automatically loaded from CodeWarrior, which will allow you to debug using your high level source code and variables.If ICDPPCNEXUS is launched stand-alone, you will need to manually download the code and debug information. Launch the Load Dialog by clicking on the High Level Load button on the debugger tool bar:This dialog allows you to specify the binary/debug file and whether to load into RAM or FLASH. Once you are satisfied with your settings, press the “Process Load Command” button to begin the download process. This step will also load the debug information.2.4 CPU and Memory WindowsThe CPU Window displays all CPU core registers, including the Program Counter (PC) and all general purpose registers.•To modify CPU register contents, double-click the register value. You will be prompted for a new value.The Memory Window displays data at any given memory address. It can be used to view RAM contents, FLASH contents, and values of peripheral registers.•To change the memory address, right-click inside the Memory Window and select “Set Base Address”. You will be prompted for a new address to begin displaying data.•To change the contents in memory, double-click the value in memory that you would like to change. You will be prompted for a new value.3 DebuggingThis section outlines the different debugging capabilities available in the ICDPPCNEXUS debugger once the debug information has been loaded.3.1 GOTIL commandAt this point, your source window will show the assembly language startup code generated by the compiler:If you do not need to debug this section and would like to run the processor until the beginning of your “main” function, you can use the “GOTIL” command.•Type “GOTIL main” in the Status window to tell the debugger to run code until it reaches the “main” function of your code.The “GOTIL” command works with any function in your code.3.1 Stepping through C instructionsStep through the initialization code, or any source code, using the high-level language source step command. Use this feature by typing “HSTEP” in the Status window or by clicking the high-level step button on the debugger tool bar:Each time the HSTEP command executes, the debugger will rapidly single step assembly instructions until it encounters the next source instruction, at which point target execution will cease. When the debugger reaches the next source instruction, all visible windows will be updated with data from the board. After reaching the main function, step through several C language instructions. Notice that some instructions will take longer to step through than others because each C instruction may consist of a greater or fewer number of underlying assembly instructions.3.3 Setting and Reaching BreakpointsIn the source code window, there will be a small red dot and a small blue arrow next to each source instruction that has underlying object code. If a large blue arrow appears on a source line, this indicates that the program counter (PC) currently points to this instruction. If a large red stop sign appears on the source line, this indicates that a breakpoint exists on this line.•Set a breakpoint at an instruction by double-clicking the tiny red dot.•To remove a breakpoint, double-click the large red stop sign.Execution will begin in real-time when you issue the HGO command or click the high-level language GO button on the debugger tool bar:If the debugger encounters a breakpoint, execution will stop on this source line. If it does not encounter a breakpoint, target execution will continue until you press a key or use the stop button on the debugger tool bar:•By double clicking the small blue arrow, you will be issuing a GOTIL command to the address of this source line.A GOTIL command will set a single breakpoint at the desired address, and the processor will begin executing code in real-time from the current program counter (PC). When the debugger encounters the GOTIL address, execution stops. If the debugger does not encounter this location, execution continues until you press akey or use the stop button on the debugger tool bar. Note that all user breakpoints are ignored when the GOTIL command is used.You may also double-click the red and blue symbols in the disassembly window. The disassembly window may display an additional symbol, a small, blue "S" enclosed in a box. This indicates that that a source code instruction begins on this disassembly instruction.3.4 Using Code Window Popup Debug Evaluation HintsWhen debugging source code, it is convenient to view the contents of a variable while viewing your source code. The in-circuit debugger has a feature, debug hints, which displays the value of a variable while the mouse cursor is held over the variable name. The hint may be displayed in any of three locations, as shown below.The three locations for the debug hints are the code window title bar, the status window caption bar, and a popup hint that appears over the variable in source code. You can configure the hints to display in any combination.•Set the locations of debug hints in the configuration menu of the debuggerThe information in the popup hint box is similar to the information displayed in the variables window.The information includes the variable name (i), value ($1), and type (signed long).3.5 Using the Variables WindowThe variables window displays the current value of application variables. The following window shows a display of variables from the example application.Variables that are pointer or reference types are displayed in red. Normal variables are displayed in black.•Add a variable by typing the VAR command, by right clicking the variables window and choosing “Add a variable”, or by hitting the "Add Variable"button in the variables window.When adding a variable using the pop-up menu, the debugger displays the following screen.In the variable field, type the address or name of the variable. Typically, set the type of the variable to “Default”, which means that the variable will be displayed as it is defined in the debugging information. When adding a variable, you may specify the numeric display base of the variable.3.6 Modifying a Variable•To modify the current value of a variable, right-click the variable name in the variables window and select “Modify Variable” to display a dialog.Check the “Modify value” checkbox, and type the variable’s new value. After you click the OK button, the debugger updates the variable value on the target, and the debugger refreshes the variable window to display the new value. Note that the debugger will not edit certain user-defined types, such as enumerated types.•You may also modify a variable’s display properties, such as the type or numeric display base using this dialog.3.7 Using the Register InterpreterThe register interpreter provides a descriptive display of bit fields within the processor’s peripheral registers. The register interpreter allows you easily to change the value of these registers. You may quickly check the current state of a peripheral and examine the configuration of the target device.When you use the register interpreter within the debugger, it reads the current value of the peripheral register, decodes it, and displays it.To launch the register interpreter in the debugger, either use the “R” command or click the view/edit register button on the tool bar:A window will appear that allows you to select a peripheral block to examine.Double clicking the module of choice will launch the register selection window.Double clicking a specific register will launch the edit/display window for that register.The window lists the keystrokes and mouse actions, allowing you to modify the values of each of the fields. After right clicking on a specific field, the register interpreter will display all options for that field.When you quit the register view/edit window by hitting the ESC key, you will be given the opportunity to write the new value into the register, as shown in the following window.3.8 Adding Register Field Descriptions to the Variables WindowAdd register bit fields to the variables window by using the “_TR” command in the debugger or by clicking the "Add Register" button in the variables window. After selecting the register field, the field appears in the debugger variables window, and the debugger will continually update its value.。
无限Wifi网络破解——BACK TRACK支持的网卡芯片
BACK TRACK支持的网卡芯片以下数据全部来自BackTrack 3 官方论坛，这份数据可以让你清楚知道你的无线网卡或者你准备购买的无线网卡是否支持BT3，因为使用BT3破解无线网络的密码必须要无线网卡支持监听和注入，所以这个很重要！2.1 PCI2.1.1 Asus WL-138g v22.1.2 Belkin F5D80012.1.3 CNet CWP-8542.1.4 Dlink DWL-AG5302.1.5 Dlink DWL-G5202.1.6 Dlink DWL-G5502.1.7 Dlink DWL-G5102.1.8 Foxconn WLL-33502.1.9 MSI PC60G2.1.10 Netgear WG311T2.1.11 Netgear WPN3112.1.12 SMC SMCWPCI-G2.2 Mini PCI (Built in)2.2.1 Broadcom BCM4306 802.11b/g (rev 3)2.2.2 Broadcom BCM4318 802.11b/g2.2.3 IBM AR5212 802.11abg NIC (rev 01)2.2.4 IPW21002.2.5 IPW22002.2.6 WN360G2.3 Mini PCIe (Built in)2.3.1 Broadcom BCM4311 802.11b/g2.3.2 IPW39452.3.3 IPWRAW (IPW3945 Monitor + Inject)2.3.4 IPW4965/IWL4965 agn2.4 PCMCIA Cards2.4.1 3COM 3CRWE154G72 v12.4.2 3COM 3CRPAG175B with XJACK Antenna2.4.3 Agere Systems ORiNOCO GOLD PC Card Classic2.4.4 AirLink101 AWLC41302.4.5 ASUS WL100G2.4.6 Belkin F5D6020 v32.4.7 Belkin F5D7010 V10002.4.8 Belkin F5D7010 V3000UK2.4.9 Belkin F5D7010 V50002.4.10 Belkin F5D7010 V60002.4.11 Belkin F5D70112.4.12 Buffalo WLI-CB-G54HP2.4.13 Cisco AIR-LMC3502.4.14 Cisco AIR-PCM350-T2.4.15 Cisco Aironet AIR-CB21AG-A-K92.4.16 Dlink DW A-6452.4.17 Dlink DWL-650+2.4.18 Dlink DWL-G6502.4.19 Dlink DWL-G630, 650+/-2.4.20 Dlink DWL-G650M2.4.21 Dlink DWL-G650+2.4.22 D-Link WNA-13302.4.23 Enterasys Roamabout 802.11 DS High Rate2.4.24 Gigabyte GN-WM01GT AirCruiserG Mach G2.4.25 Lucent Technologies Orinoco Silver2.4.26 Linksys WPC11v42.4.27 Linksys WPC11v42.4.28 Linksys WPC54G v32.4.29 Motorola WN825G v22.4.30 NetGear MA4012.4.31 NetGear WPN5112.4.32 NetGear WPN511 – Range Max2.4.33 NetGear WG511T2.4.34 NetGear W AG511v22.4.35 NetGear WG511 v12.4.36 NetGear WG511v22.4.37 Netgear WG511U2.4.38 NetGear WPN511GR2.4.39 Netgear WPNT5112.4.40 PROXIM ORiNOCO 802.11b/g Gold (Model: 8470-WD)2.4.41 Senao NL-2511CD PLUS EXT22.4.42 Senao Sl-2511CD Plus EXT22.4.43 Senao SL-2511 CD PLUS (the one w/o external connectors)2.4.44 Sitecom WL-100b2.4.45 SMC 2532W-B2.4.46 SMC SMC2536W-AG2.4.47 SMC WCB-G2.4.48 SWEEX LW051 ver:1.02.4.49 TP-link SuperG&eXtended Range 108M Wireless Cardbus Adapter(TL-WN610G) 2.4.50 TP-link eXtended Range 54M Wireless Cardbus Adapter (TL-WN510G)2.4.51 Ubiquiti SRC2.4.52 Wistron WLAN 802.11a/b/g Cardbus CB9-GP2.4.53 X-Micro WLAN 11g PCMCIA Card (XWL-11GPAG)2.4.54 ZCom XI-325HP+2.4.55 Zyxel ZyAIR G-100 PCMCIA Card (FCC ID:N89-WE601l)2.5 USB Dongles2.5.1 Airlink101 AWLL30262.5.2 ALFA Networks AWUS036H2.5.3 ASUS WL-167G2.5.4 A VM Fritz!Wlan USB V1.12.5.5 Belkin F5D7050 V12.5.6 Belkin F5D7050 (4000 series)2.5.7 Belkin F5D7050B2.5.8 Belkin F5D70512.5.9 Buffalo Airstation G54 WLI-U2-KG54-AI (2A)2.5.10 Chiefmax2.5.11 D-Link DWL 122 (USB) F/W3.2.1 H/W A12.5.12 D-Link DWL G122 (USB) F/W 2.03 B12.5.13 D-Link WUA-13402.5.14 Edimax EW-7317UG2.5.15 Edimax EW-7318USG2.5.16 Linksys WUSB54g v42.5.17 Linksys WUSB54GC2.5.18 MicroEdge MEG55A Wireless-G USB Dongle2.5.19 NetGear WG111v22.5.20 NetGear WG111T2.5.21 Netopia ter/gusb-e2.5.22 OvisLink Evo-w54usb2.5.23 SafeCom SWMULZ-54002.5.24 ZyDAS 12112.5.25 SMCWUSB-G EU2.5.26 MSI US54SE2.5.27 Hawking HWUG1为了您的安全，请只打开来源可靠的网址打开网站取消来自: /zsh%5Fmars/blog/item/c5524029148e59f599250ab0.html。
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Register Informations
OCR Register
OCR bit [6:0] [7] [14:8] [23:15] [28:24] [30:29] [31] VDD Voltage window Reserved 1.70-1.95 2.0-2.6 2.7-3.6 Reserved Access Mode Value 000 0000b 1b 000 0000b 1 1111 1111b 0 0000b 10b
Performance
X8 mode/ Sequential access (4MByte access size)
Interleave Operation Frequency /Mode Typ. Performance [MB/sec] VccQ Read 1.8V 52MHz/SDR 3.3V THGBMDG5D1KBAIT 4GB 1 x 32Gb A19nm Non Interleave 1.8V 52MHz/DDR 3.3V HS200 HS400 1.8V 1.8V TBD TBD TBD TBD TBD TBD Write TBD TBD TBD TBD TBD TBD
NC NC NC
NC NC NC
NC NC NC NC
VccQ
VSF VSF RFU Vss
VSF RFU
Vcc RFU Vcc Vss
RFU
NC NC NC NC
CLK
NC NC NC NC
NC
NC NC
RFU
VssQ
Top View
Vss
Vcc
RFU Vcc
RFU NC
Vss
DAT2
DAT7
RFU
4GB
Part Number
THGBMDG5D1KBAIT
Interleave Operation
Non Interleave
User Area Density [Bytes]
3,959,422,976
SEC_COUNT in Extended CSD
0x760000
1) User area density shall be reduced if enhanced user data area is defined.
Name VccQ VssQ VccQ VssQ VccQ VssQ
NC: No Connect, shall be connected to ground or left floating. RFU: Reserved for Future Use, shall be left floating for future use. VSF: Vendor Specific Function, shall be left floating.
14 13 12 11 10 9 8 7 6 5 4 3 2 1
NC
NC NC NC
NC
NC NC NC
NC
NC NC NC
NC
NC NC
NC
NC NC
NC
NC NC
NC
NC NC
NC
NC NC
NC
NC NC
NC
NC NC
NC
NC NC
NC
NC NC NC
NC
NC NC NC
NC
NC NC NC
RFU
Except HS400 HS400
* Toshiba recommends that the value should be usually applied as the value of CREG. CREG shall be compliant with X5R/X7R of EIA standard or B of JIS standard.
Figure 1
THGBMDG5D1KBAIT Block Diagram
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Nov. 21st, 2013
Preliminary
THGBMDG5D1KBAIT
PRODUCT SPECIFICATIONS
Package Dimensions
P-WFBGA153-1110-0.50-001 (11 x 10mm, H0.8mm max. package) Unit: mm
Max Operating Current [mA] Iccq 1.8V 52MHz/SDR 3.3V THGBMDG5D1KBAIT 4GB 1 x 32Gb A19nm Non Interleave 1.8V 52MHz/DDR 3.3V HS200 HS400 1.8V 1.8V TBD TBD TBD TBD TBD TBD Icc TBD TBD TBD TBD TBD TBD
3
Nov. 21st, 2013
Preliminary
THGBMDG5D1KBAIT
Product Architecture
The diagram in Figure 1 illustrates the main functional blocks of the THGBMDG5D1KBAIT. Specification of the CREG and recommended values of the CVCC, and CVCCQ in the Figure 1 are as follows. Parameter Symbol Unit μF VDDi capacitor value VCC capacitor value VCCQ capacitor value CREG CVCC CVCCQ μF μF μF Min. 0.10 1.00 Typ. 2.2 + 0.1 2.2 + 0.1 Max. 2.2* 2.2* Remark
Package
Vcc(3.3V) VccQ(1.8V/3.3V) VDDi CVCC CVCCQ
MMC I/O BLOCK
REGULATOR
NAND Control signal
NAND I/O BLOCK
CREG
x11
I/O BLOCK
CORE LOGIC
NAND
NAND I/O
MMC I/F(1.8V/3.3V)
NC
VssQ
VccQ
Байду номын сангаас
NC NC A
DAT3 VDDi
NC NC G
NC NC H
NC NC P
NC B
NC C
NC N
Pin Number A3 A4 A5 A6 B2 B3 B4 B5 B6
Name DAT0 DAT1 DAT2 Vss DAT3 DAT4 DAT5 DAT6 DAT7
Pin Number C2 C4 C6 E6 E7 F5 G5 H5 H10
TOSHIBA Part Number
Density
NAND Flash Type
Interleave Operation
Frequency /Mode
VccQ
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Nov. 21st, 2013
Preliminary
THGBMDG5D1KBAIT
Sleep Mode Current
Iccqs [μA] Typ. *1 TBD Max. *2 TBD Iccqs+Iccs [μA] Typ. *1 TBD Max. *2 TBD
TOSHIBA Part Number
Density
NAND Flash Type
Interleave Operation Non Interleave
THGBMDG5D1KBAIT
4GB
1 x 32Gb A19nm
*1: The conditions of typical values are 25°C and VccQ = 3.3V or 1.8V. *2: The conditions of maximum values are 85°C and VccQ = 3.6V or 1.95V.
TOSHIBA Part Number
Density
NAND Flash Type
Power Supply
Vcc = VccQ = 2.7V to 3.6V 1.7V to 1.95V / 2.7V to 3.6V
Operating Current (RMS)
The measurement for max RMS current is done as average RMS current consumption over a period of 100ms
Preliminary
THGBMDG5D1KBAIT
TOSHIBA e-MMC Module
4GB THGBMDG5D1KBAIT INTRODUCTION
THGBMDG5D1KBAIT is 4GB density of e-MMC Module product housed in 153ball BGA package. This unit is utilized advanced TOSHIBA NAND flash device(s) and controller chip assembled as Multi Chip Module. THGBMDG5D1KBAIT has an industry standard MMC protocol for easy use.
Remark: Data A, B and S are defined by the least square method of all solder balls
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Nov. 21st, 2013
Preliminary
THGBMDG5D1KBAIT