L6229DP中文资料
NI_PXI-6229

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NI PXI-6229
16位, 250 kS/s, 32路模拟输入
• 4路16位模拟输出 (833 kS/s) • 高达48路数字I/O; 32位计数器; 数字触发 • NIST校准认证书以及70多个信号调理选项 • 关联(Correlated)DIO (32条时钟线, 1 MHz) • 另有5倍采样速率的高速M系列和4倍分辨率的高精度M系列可供选择. • NI-DAQmx驱动软件和NI LabVIEW SignalExpress交互式数据记录软件
RMB 820.00
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CR6229

Min Typ Max Unit
Supply Voltage (VDD)
VDD=14.1V, Measure
Istartup
VDD Start up Current
Leakage current into VDD
3
20
uA
I_VDD (Operation)
Operation Current
VFB=3V
260℃
Note: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the
device. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
-0.3V to 7V
Sense Input Voltage Min/Max Operating junction Temperature TJ
-0.3V to 7V -20℃ to 150℃
Min/Max Storage Temperature Tstg
-55℃ to 160℃
Lead Temperature (Soldering, 10secs)
Voltage Lockout with Hysteresis (UVLO) ¾ Line Input Compensated Cycle-by-Cycle Over-current Threshold Setting For Constant Output Power Limiting Over Universal Input Voltage Range ¾ Overload Protection (OLP) ¾ Over Voltage Protection (OVP)
BA6229资料

411
元器件交易网 Motor driver ICs
FMeasurement circuit FApplication example
BAacteristics (unless otherwise noted, Ta = 25_C and VCC1 = 12V)
412
元器件交易网 Motor driver ICs
FOperation notes (1) The quality of these products have been carefully checked; however, use of the products with applied voltages, operating temperatures, or other parameters that exceed the absolute maximum rating given may result in the damage of the IC and the product it is used in. If the IC is damaged, the short mode and open modes cannot be specified, so if the IC is to be used in applications where parameters may exceed the absolute maximum ratings, then be sure to incorporate fuses, or other physical safety measures. (2) Input pins Voltage should never be applied to the input pins when the VCC voltage is not applied to the IC. Similarly, when VCC is applied, the voltage on each input pin should be less than VCC and within the guaranteed range for the electrical characteristics. (3) Back-rush voltage Depending on the ambient conditions, environment, or motor characteristics, the back-rush voltage may fluctuate. Be sure to confirm that the back-rush voltage will not adversely affect the operation of the IC. (4) Large current line Large currents are carried by the motor power supply and motor ground for these ICs. Therefore, the layout of the pattern of the PC board and the constants of certain parameters for external components, such as the capacitor between the power supply and ground, may cause this large output current to flow back to the input pins, resulting in output oscillation or other malfunctions. To prevent this, make sure that the PC board layout and external circuit constants cause no problems with the characteristics of these ICs. FExternal dimensions (Units: mm)
TPS62291资料

• High Efficiency Step Down Converter • Output Current up to 1000 mA • VIN Range From 2.3 V to 6 V • 2.25 MHz Fixed Frequency Operation • Power Save Mode at Light Load Currents • Output Voltage Accuracy in PWM mode ±1.5% • Fixed Output Voltage Options • Typ. 15-µA Quiescent Current • 100% Duty Cycle for Lowest Dropout • Voltage Positioning at Light Loads • Available in a 2 × 2 × 0,8 mm SON Package
VALUE –0.3 to 7 –0.3 to VIN +0.3, ≤ 7 –0.3 to 7 Internally limited
2 1 200 –40 to 125 –65 to 150
UNIT
V
A kV V °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
L6599D中文资料

L6599D中⽂资料May 2006 Rev 11/36L6599High-voltage resonant controllerFeatures■50% duty cycle, variable frequency control of resonant half-bridge ■High-accuracy oscillator■Up to 500kHz operating frequency■Two-level OCP: frequency-shift and latched shutdown■Interface with PFC controller ■Latched disable input■Burst-mode operation at light load ■Input for power-ON/OFF sequencing or brownout protection■Non-linear soft-start for monotonic output voltage rise■600V-rail compatible high-side gate driver with integrated bootstrap diode and high dV/dt immunity■-300/800mA high-side and low-side gate drivers with UVLO pull-down ■DIP-16, SO-16N packagesApplications■LCD & PDP TV■Desktop PC, entry-level server ■Telecom SMPS■AC-DC adapter, open frame SMPSOrder codePart number Package Packaging L6599D SO-16N T ube L6599TR SO-16N Tape and reelL6599NDIP-16T ube/doc/128b95b11a37f111f1855bea.htmlContents L6599Contents1Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3Typical system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.1Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157.1Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.2Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.3Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.4Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.5Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277.6Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277.7Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297.8Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352/36L6599Device description3/361 Device descriptionThe L6599 is a double-ended controller specific for the resonant half-bridge topology. Itprovides 50% complementary duty cycle: the high-side switch and the low-side switch are driven ON 180° out-of-phase for exactly the same time.Output voltage regulation is obtained by modulating the operating frequency. A fixed dead-time inserted between the turn-OFF of one switch and the turn-ON of the other one guarantees soft-switching and enables high-frequency operation.To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage floating structure able to withstand more than 600V with a synchronous-driven high-voltage DMOS that replaces the external fast-recovery bootstrap diode.The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator.At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non linear to minimize output voltage overshoots; its duration is programmable as well.The IC can be forced to enter a controlled burst-mode operation at light load, so as to keep converter's input consumption to a minimum.IC's functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart.A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP .An interface with the PFC controller is provided that enables to switch off the pre-regulator during fault conditions, such as OCP shutdown and DIS high, or during burst-mode operation.Pin Settings L65994/362 Pin Settings2.1 Connection2.2 FunctionsTable 1.Pin functionsN.NameFunction1C SSSoft start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4)that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor every time the chip turns OFF (V CC < UVLO, LINE < 1.25V or > 6V , DIS > 1.85V , ISEN > 1.5V , DELAY > 3.5V) to make sure it will be soft-started next, and when the voltage on the current sense pin (ISEN) exceeds 0.8V , as long as it stays above 0.75V .2DELAYDelayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin to GND to set both the maximum duration of an overcurrent condition before the IC stops switching and the delay after which the IC restarts switching. Every time the voltage on the ISEN pin exceeds 0.8V the capacitor is charged by an internal 150µA current generator and is slowly discharged by the external resistor. If the voltage on the pin reaches 2V , the soft start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150µA is kept always on. As the voltage on the pin exceeds 3.5V the IC stops switching and the internal generator is turned OFF , so that the voltage on the pin will decay because of the external resistor. The IC will be soft-restarted as the voltage drops below 0.3V . In this way, under short circuit conditions, the converter will work intermittently with very low input average power.3CFTiming capacitor. A capacitor connected from this pin to GND is charged and discharged by internal current generators programmed by the external network connected to pin 4 (RFmin) and determines the switching frequency of the converter.L6599Pin Settings5/364RFminMinimum oscillator frequency setting. This pin provides a precise 2V reference and a resistor connected from this pin to GND defines a current that is used to set the minimum oscillator frequency. T o close the feedback loop that regulates the converter output voltage bymodulating the oscillator frequency, the phototransistor of an optocoupler will be connected to this pin through a resistor. The value of this resistor will set the maximum operatingfrequency. An R-C series connected from this pin to GND sets frequency shift at start-up to prevent excessive energy inrush (soft-start).5STBYBurst-mode operation threshold. The pin senses some voltage related to the feedbackcontrol, which is compared to an internal reference (1.25V). If the voltage on the pin is lower than the reference, the IC entersan idle state and its quiescent current is reduced. The chip restarts switching as the voltage exceeds the reference by 50mV . Soft-start is not invoked. This function realizes burst-mode operation when the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if burst-mode is not used.6ISENCurrent sense input. The pin senses the primary current though a sense resistor or acapacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control; hence the voltage signal must be filtered to get average current information. As the voltage exceeds a 0.8V threshold (with 50mV hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases hence limiting the power throughput. Under output short circuit, this normally results in a nearly constant peak primary current. This condition is allowed for a maximum time set at pin 2. If the current keeps on building up despite this frequency increase, a second comparator referenced at 1.5V latches the device off and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.7LINELine sensing input. The pin is to be connected to the high-voltage input bus with a resistor divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage below 1.25V shuts down (not latched) the IC, lowers its consumption and discharges the soft-start capacitor. IC’s operation is re-enabled (soft-started) as the voltage exceeds 1.25V . The comparator is provided with current hysteresis: an internal 15µA current generator is ON as long as the voltage applied at the pin is below 1.25V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is top-limited by an internal zener. Activating the zener causes the IC to shut down (not latched). Bias the pin between 1.25 and 6V if the function is not used.8DISLatched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 1.85V , shuts the IC down and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the V CC pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.9PFC_STOPOpen-drain ON/OFF control of PFC controller. This pin, normally open, is intended forstopping the PFC controller, for protection purpose or during burst-mode operation. It goes low when the IC is shut down by DIS > 1.85V , ISEN > 1.5V , LINE > 6V and STBY < 1.25V .The pin is pulled low also when the voltage on pin DELAY exceeds 2V and goes back open as the voltage falls below 0.3V . During UVLO, it is open. Leave the pin unconnected if not used.10GNDChip ground. Current return for both the low-side gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.Table 1.Pin functionsTypical system block diagram L65996/363 Typical system block diagramTypical system block diagram11LVGLow-side gate-drive output. The driver is capable of 0.3A min. source and 0.8A min. sink peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively pulled to GND during UVLO.12V CC Supply Voltage of both the signal part of the IC and the low-side gate driver. Sometimes a small bypass capacitor (0.1µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC.13N.C.High-voltage spacer. The pin is not internally connected to isolate the high-voltage pin and ease compliance with safety regulations (creepage distance) on the PCB.14OUTHigh-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground.15HVGHigh-side floating gate-drive output. The driver is capable of 0.3A min. source and 0.8A min. sink peak current to drive the upper MOSFET of the half-bridge leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.16VBOOTHigh-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate-drive. This patented structure replaces the normally used external diode.Table 1.Pin functionsL6599Electrical data7/364 Electrical data4.1 Maximum ratingsNote:ESD immunity for pins 14, 15 and 16 is guaranteed up to 900V4.2 Thermal dataTable 2.Absolute maximum ratingsSymbol Pin ParameterValue Unit V BOOT 16 Floating supply voltage -1 to 618 V V OUT 14 Floating ground voltage -3 to V BOOT -18V dV OUT /dt 14 Floating ground max. slew rate 50V/nsV CC 12 IC Supply voltage (I CC ≤ 25 mA) Self-limited V V PFC_STOP 9 Maximum voltage (pin open) -0.3 to V CC V I PFC_STOP 9 Maximum sink current (pin low)AV LINEmax 7Maximum pin voltage (Ipin ≤ 1mA) Self-limited VI RFmin4 Maximum source current 2 mA 1 to 6, 8 Analog inputs & outputs-0.3 to 5VTable 3.Thermal dataSymbol DescriptionValue Unit R thJA Max. thermal resistance junction to ambient (DIP16)80°C/W Max. thermal resistance junction to ambient (SO16)120T STG Storage temperature range-55 to 150°C T J Junction operating temperature range-40 to 150°C P TOTRecommended max. power dissipation @T A = 70°C (DIP16) 1 WRecommended max. power dissipation @T A = 50°C (SO16)0.835 ElectricalcharacteristicsT J = 0 to 105°C, V CC = 15V, V BOOT = 15V, C HVG = C LVG = 1nF; C F = 470pF;R RFmin = 12k?; unless otherwise specified.Table 4.Electrical characteristicsSymbol Parameter TestconditionMin Typ Max Unit IC supply voltageV CC Operating range After device turn-on8.85 16 VV CC(ON)Turn-ON threshold Voltage rising10 10.7 11.4 VV CC(OFF)Turn-OFF threshold Voltagefalling 7.45 8.15 8.85 V Hys Hysteresis 2.55 VV Z V CC clamp voltage Iclamp = 10mA 16 17 17.9 V Supply currentI start-up Start-up current Before device turn-ONV CC = V CC(ON) - 0.2V200 250 µAI q Quiescent current Device ON, V STBY = 1V 1.5 2 mAI op Operating current Device ON,V STBY = V RFmin 3.5 5 mAI q Residual consumption V DIS> 1.85V or V DELAY> 3.5V or V LINE < 1.25 Vor V LINE = V clamp300 400 µAHigh-side floating gate-drive supplyI LKBOOT V BOOT pin leakagecurrentV BOOT= 580V 5 µAI LKOUT OUT pin leakage current VOUT= 562V 5 µAr DS(on)Synchronous bootstrapdiode ON-resistanceV LVG= High 150 ?Overcurrent comparatorI ISEN Input bias current V ISEN = 0 to V ISENdis-1 µAt LEB Leading edge blanking After V HVG and V LVGlow-to-high transition250 nsV ISENx Frequency shiftthreshold Voltage rising(1)0.76 0.8 0.84 VHysteresis Voltagefalling 50 mV V ISENdis Latch OFF threshold Voltage rising (1) 1.44 1.5 1.56 V td(H-L)Delay to output 300400 ns8/369/36Symbol Parameter Test condition Min Typ Max UnitLine sensing V th Threshold voltage Voltage rising or falling(1)1.2 1.25 1.3 V I Hyst Current hysteresis V CC > 5V , V LINE = 0.3V 12 15 18 µA V clamp Clamp levelI LINE = 1mA6 8 VDIS functionI DIS Input bias current V DIS = 0 to V th -1 µAV th Disable thresholdVoltage rising (1)1.77 1.85 1.93 VOscillatorDOutput duty cycleBoth HVG and LVG4850 52 %f oscOscillation frequency58.2 60 61.8kHzR RFmin = 2.7 k ?240 250 260Maximumrecommended500kHz T D Dead-time Between HVG and LVG0.20.3 0.4µs V CFp Peak value 3.9 V V CFv Valley value 0.9 VV REF Voltage reference at pin 4(1)1.92 22.08 VK M Current mirroring ratio 1A/A RF MINTiming resistor range1100k ?PFC_STOP functionI leak High level leakage currentV PFC_STOP = V CC ,V DIS = 0V 1 µAV LLow saturation levelI PFC_STOP =1mA,V DIS = 2V0.2 VSoft-start functionI leakOpen-state currentV(Css) = 2V0.5µA R Discharge resistance V ISEN > V ISENx 120Standby functionI DIS Input Bias Current V DIS = 0 to V th -1 µAV thDisable thresholdVoltage falling (1) 1.2 1.25 1.3 VHys HysteresisVoltage rising50mVTable 4.Electrical characteristics10/36Symbol Parameter Test condition Min TypMax UnitDelayed shutdown functionI leak Open-state current V(DELAY) = 0 0.5 µAI CHARGE Charge current V DELAY = 1V , V ISEN = 0.85V 100 150 200 µA Vth 1 Threshold for forcedoperation at max. frequencyVoltage rising (1)1.92 22.08 VVth 2Shutdown threshold Voltage rising (1) 3.3 3.5 3.7 V Vth 3Restart thresholdVoltage falling (1)0.25 0.3 0.35 VLow - side gate driver (voltages referred to GND)V LVGL Output low voltage I sink = 200mA 1.5 VV LVGH Output high voltage I source = 5mA12.8 13.3 V I sourcepk Peak source current -0.3 A I sinkpk Peak sink current 0.8A t f Fall time 30 ns t rRise time 60nsUVLO saturationV CC = 0 to V CC(ON),I sink = 2mA 1.1 VHigh-side gate driver (voltages referred to OUT)V HVGL Output low voltage I sink = 200 mA 1.5 V V HVGH Output high voltage I source = 5 mA12.8 13.3 V I sourcepk Peak source current -0.3 A I sinkpk Peak sink current 0.8A t f Fall time 30 ns t rRise time60 ns HVG-OUT pull-down25k ?1.Values traking each otherTable 4.Electrical characteristics11/366 Typical electrical performanceFigure 3.Device consumption vssupply voltageFigure 4.IC consumption vs junction temperatureV CC clamp voltage vs junction temperatureFigure 6.UVLO thresholds vs junction temperature12/36Figure 7.Oscillator frequency vsjunction temperature Figure 8.Dead-time vsjunction temperatureFigure 9.Oscillator frequency vstiming components Figure 10.Oscillator ramp vs junction temperature13/36Figure 11.Reference voltage vsjunction temperatureFigure 12.Current mirroring ratio vsjunction temperatureFigure 13.OCP delay source current vsjunction temperature Figure 14.OCP delay thresholds vs junction temperatureFigure 15.Standby thresholds vsjunction temperatureFigure 16.Current sense thresholds vsjunction temperatureFigure 17.Line thresholds vsjunction temperatureFigure 18.Line source current vsjunction temperatureFigure /doc/128b95b11a37f111f1855bea.html tched disable threshold vs junction temperature7 ApplicationinformationThe L6599 is an advanced double-ended controller specific for resonant half-bridge topology. In these converters the switches (MOSFETs) of the half-bridge leg are alternately switched on and OFF (180° out-of-phase) for exactly the same time. This is commonly referred to as operation at "50% duty cycle", although the real duty cycle, that is the ratio of the ON-time of either switch to the switching period, is actually less than 50%. The reason is that there is an internally fixed dead-time T D, inserted between the turn-OFF of either MOSFET and the turn-ON of the other one, where both MOSFETs are OFF. This dead- time is essential in order for the converter to work correctly: it will ensure soft-switching and enable high-frequency operation with high efficiency and low EMI emissions.To perform converter's output voltage regulation the device is able to operate in different modes (Figure20), depending on the load conditions:1.Variable frequency at heavy and medium/light load. A relaxation oscillator (see "Oscillator" section for more details) generates a symmetrical triangular waveform,which MOSFETs' switching is locked to. The frequency of this waveform is related to a current that will be modulated by the feedback circuitry. As a result, the tank circuitdriven by the half-bridge will be stimulated at a frequency dictated by the feedback loopto keep the output voltage regulated, thus exploiting its frequency-dependent transfer characteristics.2. Burst-mode control with no or very light load. When the load falls below a value, the converter will enter a controlled intermittent operation, where a series of a fewswitching cycles at a nearly fixed frequency are spaced out by long idle periods whereboth MOSFETs are in OFF-state. A further load decrease will be translated into longeridle periods and then in a reduction of the average switching frequency. When theconverter is completely unloaded, the average switching frequency can go down evento few hundred Hz, thus minimizing magnetizing current losses as well as all frequency-related losses and making it easier to comply with energy saving recommendations.Figure 20.Multi-mode operation15/3616/367.1 OscillatorThe oscillator is programmed externally by means of a capacitor (CF), connected from pin 3 (CF) to ground, that will be alternately charged and discharged by the current defined with the network connected to pin 4 (RF min ). The pin provides an accurate 2V reference with about 2mA source capability and the higher the current sourced by the pin is, the higher the oscillator frequency will be. The block diagram of Figure 21 shows a simplified internal circuit that explains the operation. The network that loads the RFmin pin generally comprises three branches:1. A resistor RF min connected between the pin and ground that determines the minimum operating frequency;2.A resistor RF max connected between the pin and the collector of the (emitter-grounded) phototransistor that transfers the feedback signal from the secondary side back to the primary side; while in operation, the phototransistor will modulate the current through this branch - hence modulating the oscillator frequency - to perform output voltage regulation; the value of RF max determines the maximum frequency the half-bridge will be operated at when the phototransistor is fully saturated;3.An R-C series circuit (C SS + R SS ) connected between the pin and ground that enables to set up a frequency shift at start-up (see Chapter 7.3: Soft-start ). Note that the contribution of this branch is zero during steady-state operation.The following approximate relationships hold for the minimum and the maximum oscillatorfrequency respectively:f min 13CF RF min------------------------------------------=f max 13CF RF min RF max ||()--------------------------------------------------------------------------=17/36After fixing CF in the hundred pF or in the nF (consistently with the maximum sourcecapability of the RF min pin and trading this off against the total consumption of the device), the value of RF min and RF max will be selected so that the oscillator frequency is able to cover the entire range needed for regulation, from the minimum value f min (at minimum input voltage and maximum load) to the maximum value f max (at maximum input voltage and minimum load):A different selection criterion will be given for RF max in case burst-mode operation at no-load will be used (see "Operation at no load or very light load" section).In Figure 22 the timing relationship between the oscillator waveform and the gate-drive signals, as well as the swinging node of the half-bridge leg (HB) is shown. Note that the low-side gate-drive is turned on while the oscillator's triangle is ramping upand the high-side gate-drive is turned on while the triangle is ramping down. In this way, at start-up, or as the IC resumes switching during burst-mode operation, the low-side MOSFET will be switched on first to charge the bootstrap capacitor. As a result, the bootstrap capacitor will always be charged and ready to supply the high-side floating driver.RF min 13CF f min-----------------------------------=RF max RF minf maxf min----------1–--------------------=7.2 Operation at no load or very light loadWhen the resonant half-bridge is lightly loaded or unloaded at all, its switching frequency willbe at its maximum value. T o keep the output voltage under control in these conditions and toavoid losing soft-switching, there must be some significant residual current flowing throughthe transformer's magnetizing inductance. This current, however, produces someassociated losses that prevent converter's no-load consumption from achieving very lowvalues.To overcome this issue, the L6599 enables the designer to make the converter operateintermittently (burst-mode operation), with a series of a few switching cycles spaced out bylong idle periods where both MOSFETs are in OFF-state, so that the average switchingfrequency can be substantially reduced. As a result, the average value of the residualmagnetizing current and the associated losses will be considerably cut down, thusfacilitating the converter to comply with energy saving recommendations.The device can be operated in burst-mode by using pin 5 (STBY): if the voltage applied tothis pin falls below 1.25V the IC will enter an idle state where both gate-drive outputs arelow, the oscillator is stopped, the soft-start capacitor C SS keeps its charge and only the 2Vreference at RF min pin stays alive to minimize IC's consumption and V CC capacitor'sdischarge. The IC will resume normal operation as the voltage on the pin exceeds 1.25V by50mV.To implement burst-mode operation the voltage applied to the STBY pin needs to be relatedto the feedback loop. Figure23 shows the simplest implementation, suitable with a narrowinput voltage range (e.g. when there is a PFC front-end).18/3619/36Essentially, RF max will define the switching frequency f max above which the L6599 will enter burst-mode operation. Once fixed f max , RF max will be found from the relationship:Note that, unlike the f max considered in the previous section ("Chapter 7.1: Oscillator "), here f max is associated to some load Pout B greater than the minimum one. Pout B will be such that the transformer's peak currents are low enough not to cause audible noise.Resonant converter's switching frequency, however, depends also on the input voltage; hence, in case there is quite a large input voltage range with the circuit of Figure 23 the value of Pout B would change considerably. In this case it is recommended to use thearrangement shown in Figure 24 where the information on the converter's input voltage is added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship between switching frequency and input voltage, it is more practical to find empirically the right amount of correction R A / (R A + R B ) needed to minimize the change of Pout B . Just be careful in choosing the total value R A + R B much greater than R C to minimize the effect on the LINE pin voltage (see Chapter 7.6: Line sensing function ).Whichever circuit is in use, its operation can be described as follows. As the load falls below the value Pout B the frequency will try to exceed the maximum programmed value f max and the voltage on the STBY pin (V STBY ) will go below 1.25V . The IC will then stop with both gate-drive outputs low, so that both MOSFETs of the half-bridge leg are in OFF-state. The voltage V STBY will now increase as a result of the feedback reaction to the energy delivery stop and, as it exceeds 1.3V, the IC will restart switching. After a while, V STBY will go down again in response to the energy burst and stop the IC. In this way the converter will work in a burst-mode fashion with a nearly constant switching frequency. A further load decrease will then cause a frequency reduction, which can go down even to few hundred hertz. The timing diagram of Figure 25 illustrates this kind of operation, showing the most significant signals. A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close to the IC as possible to reduce switching noise pick-up, will help get clean operation. To help the designer meet energy saving requirements even in power-factor-correctedsystems, where a PFC pre-regulator precedes the DC-DC converter, the device allows that the PFC pre-regulator can be turned off during burst-mode operation, hence eliminating the no-load consumption of this stage (0.5 ÷ 1W). There is no compliance issue in that because EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is envisaged when the converter operates with light or no load.To do so, the device provides pin 9 (PFC_STOP): it is an open collector output, normally open, that is asserted low when the IC is idle during burst-mode operation. This signal will be externally used for switching off the PFC controller and the pre-regulator as shown in Figure 26 When the L6599 is in UVLO the pin is kept open, to let the PFC controller start first.RF max 38--RF min f maxf min----------1–--------------------?=。
L6599中文资料

ST公司针对日益广泛使用的LCD-TV电源推出了新一代的HB-LLC控制IC-L6599,它从L6598改进而来,从而性能更优秀,使用更便捷。
下面介绍IC特色及主要应用。
L6599是一个双端输出的控制器。
它专为谐振半桥拓朴设计,提供两个50%的互补的占空比。
高边开关和低边开关输出相位差180°,输出电压的调节用调制工作频率来得到。
两个开关的开启关断之间有一个固定的死区时间,以确保软开关及高频下可靠工作。
为使高边驱动采用高压电平位移的结构具有600V耐压,用高压MOSFET取代了外部快速二极管,IC设置的工作频率范围由外部元件调节。
起动时为防止失控的冲击电流,开关频率从设置的最大值开始逐渐衰减直到由控制环路给出的稳定状态,这个频率的移动不是线性的,用来减小输出电压的过冲,做到更好的调节。
在轻载时,IC可以强制进入到控制为猝发模式工作,用以保持空载时的最低功耗。
IC的功能包括非锁定低边禁止输入以实现OCP,具有频率移动及延迟关断,然后再自动重新起动。
更高水平的OCP在第一保护电平不足时可锁住IC以控制初级电流。
它结合了完整的应对过载及短路的保护,此外锁住禁止输入(DIS)可以很容易地改善OTP及OVP。
与PFC的接口处提供了PFC预调整器在故障时的使能端子,这些故障包括OCP,在猝发模式时令DIS为高电平。
L6599的内部方框电路如图1所示。
图1 L6599 HB-LLC控制IC的内部等效电路L6599的16PIN功能如下:1 PIN CSS 软起动。
此端接一外部电容到GND,接一电阻到RF端(4PIN),它设置了最高振荡频率及频率移动到恒定的时间,IC加一个内部开关可以在芯片每次关闭时将此电容放电(Vcc<UVLO,LINE<1.25等),以确保下次正常软起动。
此时,ISEN端上的电压超过0.8V,然后长期保留在0.75V以上。
8 PIN DELAY 过流的延迟关断。
从此端接一电容及电阻到GND,设置IC关断前的过流最大时间以及IC重起动之后的延迟,每个时段ISEN端电压超过0.8V时,电容就由内部150ua 电流源发生器来缓慢放电。
MTK手机外围电路详细介绍

MTK电路原理分析MTK使用的是6229的BB芯片,Transeiver使用的是MT6140,PA为3159芯片。
6229和6230的区别为CAMERA的支持像数,6229支持200万像数,6230只支持30万像数。
6229和6226,6225等BB芯片的区别为6229内部多了一个DSP用于支持EDGE,并且6229的主频为104MHZ,相对于传统的BB芯片52MHZ的主频处理速度快了许多,所以6229不仅可以支持OTG,TVOUT,并且还支持WI-FI。
OTG只支持USB1.1版本,OTG的数据线规范要求不能大于20CM,如果过长会对信号有较大的衰减和反射。
6229也使用的是32.768KHZ的晶振产生时序电路基准信号。
32.768kHz是RTC(实时时钟)晶振,用32.768是因为32768是2的15次幂,可以很方便的分频,很精确的得到一秒的计时。
所有的RTC晶振一般都是32.768或是其倍频。
在手机电路中还有一主时钟,一般为13MHz或是其倍频。
之所以选用13M这样的时钟是为了与基站同步。
MTK和其他机种使用的FLASH也是不同的。
MTK采用混合储存器的方式不同于以往的NOR+NAND存储器方式。
注:NOR+NAND存储器采用NOR来存储BIOS代码,采用NAND存储代码(操作系统和应用软件)和数据,易失性RAM被用来存储执行代码时的变量和数据结构。
这种存储器解决方案采用代码映射或请求调页来执行存储在NAND中的操作系统和应用软件。
混合存储器采用SRAM和NAND,采用NAND作为非易失性存储器,所以这类解决方案的存储密度能做得很高。
这些解决方案可以直接从NAND引导,不再需要高端蜂窝手机中昂贵的引导NOR,因此可降低总系统成本。
它们还可以减少元器件数量,节省了电路板空间。
但是,这些混合解决方案的引导时间较长、复杂度较高、难以集成且需要主机上有支持请求调页的先进操作系统。
MIC电路MICBIASP和MICBIASN为MIC电路的正负两路偏置电压,一般为2.4V-2.7V左右的电压。
L6203中文资料

3
OUT1 Output of first Half Bridge
4
BOOT1 A boostrap capacitor connected to this pin ensures efficient
driving of the upper POWER DMOS transistor.
5
IN1
Digital Input from the Motor Controller
10
15
mA
8
15
mA
30
100 KHz
150
°C
100
ns
OFF IDSS
ON RDS
VDS(ON)
Leakage Current
On Resistance Drain Source Voltage
Vsens
Sensing Voltage
SOURCE DRAIN DIODE
Fig. 11 Vs = 52 V
The I.C. is mounted in three different packages.
July 2003
1/20
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
元器件交易网
L6201 - L6202 - L6203
PIN CONNECTIONS (Top view)
SO20
POWERDIP
GND N.C. N.C. OUT2
VS OUT1 BOOT1
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1/25L6229October 20041FEATURES■OPERATING SUPPLY VOLTAGE FROM 8 TO 52V■2.8A OUTPUT PEAK CURRENT (1.4A DC)■R DS(ON) 0.73Ω TYP. VALUE @ T j = 25 °C ■OPERATING FREQUENCY UP TO 100KHz ■NON DISSIPATIVE OVERCURRENT DETECTION AND PROTECTION ■DIAGNOSTIC OUTPUT■CONSTANT t OFF PWM CURRENT CONTROLLER■SLOW DECAY SYNCHR. RECTIFICATION ■60° & 120° HALL EFFECT DECODING LOGIC ■BRAKE FUNCTION■TACHO OUTPUT FOR SPEED LOOP ■CROSS CONDUCTION PROTECTION ■THERMAL SHUTDOWN■UNDERVOLTAGE LOCKOUT■INTEGRATED FAST FREEWEELING DIODES2DESCRIPTIONThe L6229 is a DMOS Fully Integrated Three-Phase Motor Driver with Overcurrent Protection.Realized in MultiPower-BCD technology, the device combines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip.The device includes all the circuitry needed to drive a three-phase BLDC motor including: a three-phase DMOS Bridge, a constant off time PWM Current Con-troller and the decoding logic for single ended hall sensors that generates the required sequence for the power stage.Available in PowerDIP24 (20+2+2), PowerSO36 and SO24 (20+2+2) packages, the L6229 features a non-dissipative overcurrent protection on the high side Power MOSFETs and thermal shutdown.DMOS DRIVER FORTHREE-PHASE BRUSHLESS DC MOTORTable 1. Order CodesPart Number Package L6229N PowerDIP24L6229PD PowerSO36L6229PDTR PowerSO36 in T ape & ReelL6229D SO24L6229DTRSO24 in T ape & ReelRev. 3L62292/25Table 2. Absolute Maximum RatingsSymbol ParameterTest conditionsValue Unit V S Supply VoltageV SA = V SB = V S60V V ODDifferential Voltage between:VS A , OUT 1, OUT 2, SENSE A and VS B , OUT 3, SENSE B V SA = V SB = V S = 60V;V SENSEA = V SENSEB = GND 60VV BOOT Bootstrap Peak Voltage V SA = V SB = V SV S + 10V V IN , V EN Logic Inputs Voltage Range -0.3 to 7V V REF Voltage Range at pin VREF -0.3 to 7V V RCOFF Voltage Range at pin RCOFF -0.3 to 7V V RCPULSE Voltage Range at pin RCPULSE -0.3 to 7V V SENSE Voltage Range at pins SENSE A and SENSE B-1 to 4V I S(peak)Pulsed Supply Current (for each VS A and VS B pin)V SA = V SB = V S ; T PULSE < 1ms 3.55A I S DC Supply Current (for each VS A and VS B pin)V SA = V SB = V S1.4A T stg , T OPStorage and Operating T emperature Range-40 to 150°C3/25L6229Table 3. Recommended Operating ConditionTable 4. Thermal DataSymbol ParameterTest ConditionsMIN MAX Unit V S Supply VoltageV SA = V SB = V S 1252V V ODDifferential Voltage between:VS A , OUT 1, OUT 2, SENSE A and VS B , OUT 3, SENSE B V SA = V SB = V S ;V SENSEA = V SENSEB52VV REF Voltage Range at pin VREF -0.15V V SENSE Voltage Range at pins SENSE A and SENSE B (pulsed t W < t rr )(DC)-6-161V V I OUT DC Output CurrentV SA = V SB = V S1.4A T J Operating Junction T emperature -25125°C f SWSwitching Frequency100KHzSymbol DescriptionPDIP24SO24PowerSO36Unit R th(j-pins)Maximum Thermal Resistance Junction-Pins 1915°C/W R th(j-case)Maximum Thermal Resistance Junction-Case 2°C/W R th(j-amb)1MaximumThermal Resistance Junction-Ambient (1)(1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm 2 (with a thickness of 35 µm).4455-°C/W R th(j-amb)1Maximum Thermal Resistance Junction-Ambient (2)(2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 µm).--36°C/W R th(j-amb)1MaximumThermal Resistance Junction-Ambient (3)(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 µm),16 via holes and a ground layer.--16°C/W R th(j-amb)2Maximum Thermal Resistance Junction-Ambient (4)(4) Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board.597863°C/WL62294/25Table 5. Pin DescriptionPACKAGENameTypeFunctionSO24/PowerDIP24PowerSO36PIN #PIN #110H 1Sensor Input Single Ended Hall Effect Sensor Input 1.211DIAGOpen Drain OutputOvercurrent Detection and Thermal Protection pin. An internal open drain transistor pulls to GND when an overcurrent on one of the High Side MOSFE Ts is detected or during Thermal Protection.312SENSE APower Supply Half Bridge 1 and Half Bridge 2 Source Pin. This pinmust be connected together with pin SE NSE B to Power Ground through a sensing power resistor.413RCOFFRC PinRC Network Pin. A parallel RC network connectedbetween this pin and ground sets the Current Controller OFF-Time.515OUT 1Power OutputOutput 16, 7,18, 191, 18,19, 36GNDGNDGround terminals. On PowerDIP24 and SO24packages, these pins are also used for heat dissipation toward the PCB. On PowerSO36 package the slug is connected on these pins.822T ACHOOpen Drain Output Frequency-to-Voltage open drain output. E very pulse from pin H 1 is shaped as a fixed and adjustable length pulse.924RCPULSERC PinRC Network Pin. A parallel RC network connected between this pin and ground sets the duration of the Monostable Pulse used for the Frequency-to-Voltage converter.5/25L6229PACKAGENameTypeFunctionSO24/PowerDIP24PowerSO36PIN #PIN #1025SENSE BPower Supply Half Bridge 3 Source Pin. This pin must be connectedtogether with pin SENSE A to Power Ground through a sensing power resistor. At this pin also the Inverting Input of the Sense Comparator is connected.1126FWD/RE VLogic InputSelects the direction of the rotation. HIGH logic level sets Forward Operation, whereas LOW logic level sets Reverse Operation.If not used, it has to be connected to GND or +5V ..1227EN Logic InputChip Enable. LOW logic level switches OFF all Power MOSFETs.If not used, it has to be connected to +5V .1328VREF Logic Input Current Controller Reference Voltage.Do not leave this pin open or connect to GND.1429BRAKELogic InputBrake Input pin. LOW logic level switches ON all High Side Power MOSFE Ts, implementing the Brake Function.If not used, it has to be connected to +5V .1530VBOOT Supply Voltage Bootstrap Voltage needed for driving the upper PowerMOSFETs.1632OUT 3Power OutputOutput 3.1733VS B Power Supply Half Bridge 3 Power Supply Voltage. It must beconnected to the supply voltage together with pin VS A .204VS APower Supply Half Bridge 1 and Half Bridge 2 Power Supply Voltage.It must be connected to the supply voltage together with pin VS B .215OUT 2Power OutputOutput 2.227VCP Output Charge Pump Oscillator Output.238H 2Sensor Input Single Ended Hall Effect Sensor Input 2.249H 3Sensor InputSingle Ended Hall Effect Sensor Input 3.Table 6. Electrical Characteristics(V S = 48V , T amb = 25 °C , unless otherwise specified)SymbolParameter Test Conditions MinTyp Max UnitV Sth(ON)T urn ON threshold 5.8 6.3 6.8V V Sth(OFF)T urn OFF threshold55.56V I S Quiescent Supply Current All Bridges OFF;Tj = -25 to 125°C (6)510mA T J(OFF)Thermal Shutdown T emperature165°COutput DMOS TransistorsR DS(ON)High-Side + Low-Side Switch ONResistance T j = 25 °C 1.47 1.69ΩT j =125 °C (7)2.352.70ΩI DSSLeakage CurrentEN = Low; OUT = V CC 2mA EN = Low; OUT = GND-0.3mATable 5. Pin Description (continued)L62296/25SymbolParameter Test Conditions MinTypMax UnitSource Drain Diodes V SD Forward ON Voltage I SD = 1.4A, EN = LOW 1.15 1.3V t rr Reverse Recovery Time I f = 1.4A300ns t fr Forward Recovery Time200nsLogic Input (H1, H2, H3, EN, FWD/REV, BRAKE)V IL Low level logic input voltage -0.30.8V V IH High level logic input voltage 27V I IL Low level logic input current GND Logic Input Voltage -10µA I IH High level logic input current 7V Logic Input Voltage10µA V th(ON)T urn-ON Input Threshold1.82.0V V th(OFF)T urn-OFF Input Threshold 0.8 1.3V V thHYS Input Thresholds Hysteresys0.250.5VSwitching Characteristicst D(on)EN Enable to out turn-ON delay time (7)I LOAD = 1.4 A, Resistive Load 500650800ns t D(off)EN Enable to out turn-OFF delay time (7)I LOAD = 1.4 A, Resistive Load 5001000ns t D(on)IN Other Logic Inputs to Output T urn-ON delay TimeI LOAD = 1.4 A, Resistive Load1.6µs t D(off)IN Other Logic Inputs to out T urn-OFF delay TimeI LOAD = 1.4 A, Resistive Load800ns t RISE Output Rise Time (7)I LOAD = 1.4 A, Resistive Load 40250ns t FALL Output Fall Time (7)I LOAD = 1.4 A, Resistive Load40250ns t DT Dead Time0.51µs f CPCharge Pump FrequencyTj = -25 to 125°C (6)0.61MHzPWM Comparator and Monostable I RCOFFSource current at pin RC OFFV RCOFF = 2.5 V 3.55.5mA V OFFSET Offset Voltage on SenseComparator V ref = 0.5 V ±5mV t prop T urn OFF Propagation delay (8)V ref = 0.5 V500ns t blank Internal Blanking Time on Sense Comparator 1µs t ON(min)Minimum on Time 2.53µs t OFFPWM RecirculationTimeR OFF = 20k Ω ; C OFF =1nF 13µs R OFF = 100k Ω ; C OFF =1nF61µs I BIASInput Bias Current at pin VREF10µATacho MonostableI RCPULSE Source Current at pin RCPULSEV RCPULSE = 2.5V3.55.5mATable 6. Electrical Characteristics (continued)(V S = 48V , T amb = 25 °C , unless otherwise specified)7/25L6229(6) Tested at 25°C in a restricted range and guaranteed by characterization.(7) See Fig. 4.(8) Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.(9) See Fig. 5.Symbol Parameter Test Conditions MinTyp Max Unitt PULSEMonostable of TimeR PUL = 20k Ω ; C PUL =1nF 12µs R PUL = 100k Ω ; C PUL =1nF60µs R TACHO Open Drain ON Resistance 4060ΩOver Current Detection & Protection I SOVER Supply Overcurrent ProtectionThresholdT J = -25 to 125°C (6)22.83.55A R OPDR Open Drain ON Resistance I DIAG = 4mA 4060ΩI OHOCD high level leakage currentV DIAG = 5V1µA t OCD(ON)OCD T urn-ON Delay Time (9)I DIAG = 4mA; C DIAG < 100pF 200ns t OCD(OFF)OCD T urn-OFF Delay Time (9)I DIAG = 4mA; C DIAG < 100pF100nsTable 6. Electrical Characteristics (continued)(V S = 48V , T amb = 25 °C , unless otherwise specified)L62293CIRCUIT DESCRIPTION3.1POWER STAGES and CHARGE PUMPThe L6229 integrates a Three-Phase Bridge, which consists of 6 Power MOSFETs connected as shown on the Block Diagram. Each Power MOS has an R DS(ON) = 0.73Ω (typical value @25°C) with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM Current Controller and the Hall Effect Sensor Decoding Logic (see relative paragraphs). Cross conduction protection is implemented by using a dead time (t DT = 1µs typical value) set by internal timing circuit between the turn off and turn on of two Power MOSFETs in one leg of a bridge.Pins VS A and VS B MUST be connected together to the supply voltage (V S).Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The Bootstrapped Supply (V BOOT) is obtained through an internal oscillator and few ex-ternal components to realize a charge pump circuit as shown in Figure 6. The oscillator output (pin VCP) is a square wave at 600KHz (typically) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table 7.Table 7. Charge Pump External Component Values.C BOOT220nFC P10nFR P100ΩD11N4148D21N41483.2LOGIC INPUTSPins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS and µC compatible logic inputs. The internal struc-ture is shown in Figure 4. Typical value for turn-ON and turn-OFF thresholds are respectively V th(ON) = 1.8V and V th(OFF) = 1.3V.Pin EN (enable) may be used to implement Overcurrent and Thermal protection by connecting it to the open collector DIAG output If the protection and an external disable function are both desired, the appropriate connection must be implemented. When the external signal is from an open collector output, the circuit in Figure 8 can be used . For ex-ternal circuits that are push pull outputs the circuit in Figure 9 could be used. The resistor R EN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for R EN and C EN are respectively 100KΩ and 5.6nF. More information for selecting the values can be found in the Overcurrent Protection section.8/25L62293.3PWM CURRENT CONTROLThe L6229 includes a constant off time PWM Current Controller. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the three lower power MOS transistors and ground, as shown in Figure 10. As the current in the motor increases the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input pin VRE F the sense comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the monostable and the mo-tor current recirculates around the upper half of the bridge in Slow Decay Mode as described in the next section. When the monostable times out, the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective Off Time t OFF is the sum of the monostable time plus the dead time.Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-sistor, the pin RC voltage and the status of the bridge. More details regarding the Synchronous Rectification and the output stage configuration are included in the next section.Immediately after the Power MOS turn on, a high peak current flows through the sense resistor due to the re-9/25L6229verse recovery of the freewheeling diodes. The L6229 provides a 1µs Blanking Time t BLANK that inhibits the comparator output so that the current spike cannot prematurely retrigger the monostable.10/25Figure 12 shows the magnitude of the Off Time t OFF versus C OFF and R OFF values. It can be approximately calculated from the equations:t RCFALL = 0.6 · R OFF · C OFFt OFF = t RCFALL + t DT = 0.6 · R OFF · C OFF + t DTwhere R OFF and C OFF are the external component values and t DT is the internally generated Dead Time with:20K Ω ≤ R OFF ≤ 100K Ω0.47nF ≤ C OFF ≤ 100nF t DT = 1µs (typical value)Therefore:t OFF(MIN) = 6.6µs t OFF(MAX) = 6msThese values allow a sufficient range of t OFF to implement the drive circuit for most motors.The capacitor value chosen for C OFF also affects the Rise Time t RCRISE of the voltage at the pin RCOFF. The Rise Time t RCRISE will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. Therefore, the On Time t ON , which depends by motors and supply parameters, has to be bigger than t RCRISE for allowing a good current regulation by the PWM stage. Furthermore, the On Time t ON can not be smaller than the minimum on time t ON(MIN).t RCRISE = 600 · C OFFFigure 13 shows the lower limit for the On Time t ON for having a good PWM current regulation capacity. It has to be said that t ON is always bigger than t ON(MIN) because the device imposes this condition, but it can be smaller than t RCRISE - t DT . In this last case the device continues to work but the Off Time t OFF is not more constant.So, small C OFF value gives more flexibility for the applications (allows smaller On Time and, therefore, higher switching frequency), but, the smaller is the value for C OFF , the more influential will be the noises on the circuit performance.t ON t ON MIN ()> 2.5µs (typ. value)=t ON t RCRISE t DT –>⎩⎨⎧3.4SLOW DECAY MODEFigure 14 shows the operation of the bridge in the Slow Decay mode during the Off Time. At any time only two legs of the three-phase bridge are active, therefore only the two active legs of the bridge are shown in the figure and the third leg will be off. At the start of the Off Time, the lower power MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slow-ly. After the Dead Time the upper power MOS is operated in the synchronous rectification mode reducing the impendence of the freewheeling diode and the related conducting losses. When the monostable times out, up-per MOS that was operating the synchronous mode turns off and the lower power MOS is turned on again after some delay set by the Dead Time to prevent cross conduction.3.5DECODING LOGICThe Decoding Logic section is a combinatory logic that provides the appropriate driving of the three-phase bridge outputs according to the signals coming from the three Hall Sensors that detect rotor position in a 3-phase BLDC motor. This novel combinatory logic discriminates between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical degrees. This decoding method allows the implementation of a uni-versal IC without dedicating pins to select the sensor configuration.There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor posi-tions with 120 electrical degrees sensor phasing (see Figure 15, positions 1, 2, 3a, 4, 5 and 6a) and six combi-nations are valid for rotor positions with 60 electrical degrees phasing (see Figure 17, positions 1, 2, 3b, 4, 5 and 6b). Four of them are in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 elec-trical degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phas-ing (3b and 6b).The decoder can drive motors with different sensor configuration simply by following the Table 8. For any input configuration (H1, H2 and H3) there is one output configuration (OUT1, OUT2 and OUT3). The output configura-tion 3a is the same than 3b and analogously output configuration 6a is the same than 6b.The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive the motor with all the four conventions by changing the direction set.Table 8. 60 and 120 Electrical Degree Decoding Logic in Forward Direction.Hall 120°123a-456a-Hall 60°12-3b45-6b H1H H L H L L H L H2L H H H H L L L H3L L L H H H H L OUT1Vs High Z GND GND GND High Z Vs Vs OUT2High Z Vs Vs Vs High Z GND GND GND OUT3GND GND High Z High Z Vs Vs High Z High Z Phasing1->32->32->12->13->13->21->21->23.6TACHOA tachometer function consists of a monostable, with constant off time (t PULSE ), whose input is one Hall Effect signal (H 1). It allows developing an easy speed control loop by using an external op amp, as shown in Figure 18. For component values refer to Application Information section.The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall Effect Sensors H 1, the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time t PULSE (see Figure 17). The off time t PULSE can be set using the external RC network (R PUL , C PUL ) connected to the pin RCPULSE. Figure 19 gives the relation between t PULSE and C PUL , R PUL . We have approximately:t PULSE = 0.6 · R PUL · C PULwhere C PUL should be chosen in the range 1nF … 100nF and R PUL in the range 20K Ω … 100K Ω.By connecting the tachometer pin to an external pull-up resistor, the output signal average value V M is propor-tional to the frequency of the Hall Effect signal and, therefore, to the motor speed. This realizes a simple Fre-quency-to-Voltage Converter. An op amp, configured as an integrator, filters the signal and compares it with a reference voltage V REF , which sets the speed of the motor.V M t PULSET-----------------V DD⋅=3.7NON-DISSIPATIVE OVERCURRENT DETECTION and PROTECTIONThe L6229 integrates an Overcurrent Detection Circuit (OCD) for full protection. This circuit provides Output-to-Output and Output-to-Ground short circuit protection as well. With this internal over current detection, the exter-nal current sense resistor normally used and its associated power dissipation are eliminated. Figure 20 shows a simplified schematic for the overcurrent detection circuit.To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-put current is implemented with each High Side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference cur-rent I REF. When the output current reaches the detection threshold (typically I SOVER = 2.8A) the OCD compar-ator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4mA connected to pin DIAG is turned on.The pin DIAG can be used to signal the fault condition to a µC or to shut down the Three-Phase Bridge simply by connecting it to pin EN and adding an external R-C (see R EN, C EN).Figure 21 shows the Overcurrent Detetection operation. The Disable Time t DISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by C EN and R EN values and its magnitude is reported in Figure 22. The Delay Time t DELAY before turn-ing off the bridge when an overcurrent has been detected depends only by C EN value. Its magnitude is reported in Figure 23C EN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C EN should be chosen as big as possible according to the maximum tolerable Delay Time and the R EN value should be chosen according to the desired Disable Time.The resistor R EN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for R EN and C EN are respectively 100KΩ and 5.6nF that allow obtaining 200µs Disable Time.4APPLICATION INFORMATIONA typical application using L6229 is shown in Figure 24. Typical component values for the application are shown in Table 9. A high quality ceramic capacitor (C2) in the range of 100nF to 200nF should be placed between the power pins VS A and VSB and ground near the L6229 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor (C EN) connected from the EN input to ground sets the shut down time when an over current is detected (see Overcurrent Protection). The two current sensing inputs (SENSE A and SENSE B) should be connected to the sensing resistor R SENSE with a trace length as short as possible in the layout. The sense resistor should be non-inductive resistor to minimize the di/ dt transients across the resistor. To increase noise immunity, unused logic pins are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB.Table 9. Component Values for Typical Application.C1100µF R15K6ΩC2100nF R21K8ΩC3220nF R34K7ΩC BOOT220nF R41MΩC OFF1nF R DD1KΩC PUL10nF R EN100KΩC REF133nF R P100ΩC REF2100nF R SENSE0.6ΩC EN 5.6nF R OFF33KΩC P10nF R PUL47KΩD11N4148R H1, R H2, R H310KΩD21N41484.1OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATIONIn Figure 25 is shown the approximate relation between the output current and the IC power dissipation using PWM current control.For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe op-erating junction temperature (125°C maximum).4.2THERMAL MANAGEMENTIn most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Selecting the appropriate package and heatsinking con-figuration for the application is required to maintain the IC within the allowed operating temperature range for the application. Figures 26, 27 and 28 show the Junction-to-Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages.For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board with 6cm2 dissipating footprint (copper thickness of 35µm), the R th(j-amb) is about 35°C/W. Figure 29 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15°C/W.Table 10. Revision HistoryDate Revision Description of Changes September 20031First IssueJanuary 20042Migration from ST-Press dms to EDOCS.October 20043Updated the style graphic form.Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics.All other names are the property of their respective owners© 2004 STMicroelectronics - All rights reservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America。