R4IBLKBLKEF0;中文规格书,Datasheet资料
IRLML2244TRPBF;中文规格书,Datasheet资料
1/24/111ORDERING INFORMATION:See detailed ordering and shipping information on the last page of this data sheet.Notes through are on page 10Features and BenefitsBenefitsApplication(s)• System/Load Switchresults in ⇒IRLML2244TRPbFIRLML2244TRPbF 3Fig 2. Typical Output CharacteristicsFig 1. Typical Output CharacteristicsFig 4. Normalized On-ResistanceVs. Temperature-V DS , Drain-to-Source Voltage (V)0.1110100-V DS , Drain-to-Source Voltage (V)-I D , D r a i n -t o -S o u r c e C u r r e n t (A )T J , Junction Temperature (°C)R D S (o n ) , D r a i n -t o -S o u r c e O n R e s i s t a n c eIRLML2244TRPbFFig 6. Typical Gate Charge Vs.Gate-to-Source VoltageFig 5. Typical Capacitance Vs.Drain-to-Source Voltage Fig 8. Maximum Safe Operating AreaFig 7. Typical Source-Drain DiodeForward Voltage110100-V DS , Drain-to-Source Voltage (V)10100100010000C , C a p a c i t a n c e (p F )-V SD , Source-to-Drain Voltage (V)0.1110100-I S D , R e v e r s e D r a i n C u r r e n t (A )110100-V DS , Drain-to-Source Voltage (V)0.010.1110100-I D , D r a i n -t o -S o u r c e C u r r e n t (A)048121620Q G, Total Gate Charge (nC)2468101214-V G S , G a t e -t o -S o u r c e V o l t a g e (V )IRLML2244TRPbF 5Fig 11. Typical Effective Transient Thermal Impedance, Junction-to-AmbientFig 9. Maximum Drain Current Vs.Ambient TemperatureFig 10b. Switching Time WaveformsFig 10a. Switching Time Test Circuit255075100125150T A , Ambient Temperature (°C)012345-I D , D r a i n C u r r e n t (A)t 1 , Rectangular Pulse Duration (sec)R DV DDV DSV t t t tFig 13. Typical On-Resistance Vs. DrainCurrentFig 12. Typical On-Resistance Vs. GateVoltageFig 14b. Gate Charge Test CircuitFig 14a. Basic Gate Charge Waveform 24681012-V GS, Gate -to -Source Voltage (V)20406080100120R D S (o n ), D r a i n -t o -S o u r c e O n R e s i s t a n c e (m Ω)5101520253035-I D , Drain Current (A)04080120160200R D S (o n ), D r a i n -t o -S o u r c e O n R e s i s t a n c e (m Ω)Vgs = -4.5VIdQgs1Qgs2Qgd Qgodr 0 7Fig 15. Typical Threshold Voltage Vs.Junction TemperatureFig 16. Typical Power Vs. TimeT J , Temperature ( °C )-V G S (t h ), G a t e t h r e s h o l d V o l t a g e (V )Time (sec)P o w e r (W )IRLML2244TRPbFMicro3 (SOT-23/TO-236AB) Part Marking InformationMicro3 (SOT-23) Package OutlineDimensions are shown in millimeters (inches)Note: For the most current drawing please refer to IR website at: /package/cF =DA T E C E =X = D =C =B =A =W = (1-26) IF PRECEDED BY LAST DIG IT O F C ALENDA R YEA RH =G =KH G F E D C B 200620032002200520042008200720102009J Y 51292830C B D52ZNote: A line a bove the work we e k(a s s how n he re ) indic a tes Le a d - Fre e.I =J = IRLML2030L = IRLML0060M = IRLML0040K = IRLML0100N = IRLML2060P = IRLML9301R = IRLML9303C u HALOG PAIRLML2244TRPbF 9Micro3™ Tape & Reel InformationDimensions are shown in millimeters (inches)2.05 ( .080 )1.95 ( .077 )TRFEED DIRECTION4.1 ( .161 )3.9 ( .154 )1.6 ( .062 )1.5 ( .060 )1.85 ( .072 )1.65 ( .065 )3.55 ( .139 )3.45 ( .136 )1.1 ( .043 )0.9 ( .036 )4.1 ( .161 )3.9 ( .154 )0.35 ( .013 )0.25 ( .010 )8.3 ( .326 )7.9 ( .312 )1.32 ( .051 )1.12 ( .045 )9.90 ( .390 )8.40 ( .331 )178.00( 7.008 ) MAX.NOTES:1. CONTROLLING DIMENSION : MILLIMETER.2. OUTLINE CONFORMS TO EIA-481 & EIA-541.Note: For the most current drawing please refer to IR website at: /package/IRLML2244TRPbFData and specifications subject to change without notice.IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105TAC Fax: (310) 252-7903Visit us at for sales contact information .01/2011Qualification standards can be found at International Rectifier’s web site /product-info/reliabilityHigher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information: /whoto-call/salesrep/Applicable version of JEDEC standard at the time of product release.Notes:Repetitive rating; pulse width limited by max. junction temperature. Pulse width ≤ 400μs; duty cycle ≤ 2%. Surface mounted on 1 in square Cu board Refer to application note #AN-994.Qualification information †分销商库存信息: IRIRLML2244TRPBF。
RX424024中文资料
V REG.-Nr. A651, Z E214025Contact dataContact configuration 2 COContact setsingle contact Type of interruption micro disconnectionRated current8ARated voltage / max.switching voltage AC 240/400VAC Maximum breaking capacity AC2000VA Limiting making capacity, max 4 s, duty factor 10%15A Contact materialAgNi 90/106AC coil> 1 x 106cycles Rated frequency of operation with / without load 6 / 600 min -1Contact ratings Type Load Cycles RX48A, 250VAC, 70°C, EN61810-14x104RX48A, 250VAC, 70°C, UL508 General purpose4x104Coil dataAC coil24...230VAC AC coiltyp 0,75VAOperative range2Coil insulation system according UL1446class FCoil versions,DC-coil Coil Rated Operate Release Coil Rated coil code voltage voltage voltage resistance powerVDC VDC VDC Ohm mW0055 3.50.550+10%5000066 4.20.668+10%529012128.4 1.2274+10%5260242416.8 2.41095+10%5260484833.6 4.84380+10%5260606042.0 6.06845+10%52611011077.011.023010+10%526All figures are given for coil without preenergization, at ambient temperature +23°CS0271-ACoil versions,AC-coil 50HzCoil Rated Operate Release Coil Rated coil code voltage voltage voltage resistance power50Hz50Hz50Hz VAC VAC VAC Ohm VA 5242418.0 3.6350+10%0.76 61511586.317.38100+15%0.76 730230172.534.532500+15%0.74 All figures are given for coil without preenergization, at ambient temperature +23°C Insulationrmsopen contact circuit1000 V rmsadjacent contact circuits2500 V rmsClearance/creepage coil-contact circuit W8 / 8 mmadjacent contact circuits W3 / 4 mmMaterial group of insulation parts W IIIaTracking index of relay base PTI 250 VInsulation to IEC 60664-1Type of insulation coil-contact circuit reinforcedopen contact circuit functionaladjacent contact circuits basicRated insulation voltage250 VPollution degree32Rated voltage system 240V400VOvervoltage category IIIOther dataRoHS - Directive 2002/95/EC compliant as per product date code 0413 Flammability class according to UL94 V-0 1)Ambient temperature range-40...+70°COperate- / release time DC coil typ 7 / 2msBounce time DC coil, NO / NC contact typ 1 / 3msVibration resistance (function) NO / NC contact20 / 4g, 10 ... 150 HzShock resistance (destruction) 100 gCategory of protection RTII - flux proof transparent version pcbMounting distance 2,5 mm 2)Resistance to soldering heat flux-proof version270°C / 10 sRelay weight14 gPackaging unit500 pcs12) Version with transparent cover: 5 mmAccessoriesFor standard version (white cover), details seeaccessories RT PCB layout / terminal assignmentBottom view on solder pinsS0163-BJDimensionsS0272-BA *) With the recommended PCB hole sizes a grid pattern from 2.5mm to 2.54mm can be used.。
IRG4PC40KPBF;中文规格书,Datasheet资料
VCC = 80%(VCES), VGE = 20V, L = 10µH, RG = 10Ω,
(See fig. 13a)
Pulse width ≤ 80µs; duty factor ≤ 0.1%. Pulse width 5.0µs, single shot.
2
TO-247AC
Max.
600 42 25 84 84 10 ±20 15 160 65 -55 to +150 300 (0.063 in. (1.6mm) from case) 10 lbfin (1.1Nm)
Units
V A
µs V mJ W
°C
Thermal Resistance
Parameter
Repetitive rating; VGE = 20V, pulse width limited by
max. junction temperature. ( See fig. 13b )
Repetitive rating; pulse width limited by maximum
junction temperature.
TC , Case Temperature ( ° C)
TJ , Junction Temperature ( ° C)
Fig. 4 - Maximum Collector Current vs. Case Temperature
Fig. 5 - Typical Collector-to-Emitter Voltage vs. Junction Temperature
Switching Characteristics @ TJ = 25°C (unless otherwise specified)
nRF24L01P产品说明书V1.0资料
nRF24L01+单片机2.4 GHz收发器产品说明书v1.0主要功能：全球通用的2.4 GHz ISM波段操作250kbps, 1Mbps and 2Mbps空中数据传输速率超低功率运行发射功率为0dBm（1.0mW）时，发射电流为11.3mA2Mbps空中数据传输速率，接收电流为13.5mA掉电电流为900nA待机-I电流26μA片内电压调整器1.9至3.6V电源供电范围增强型ShockBurst TM自动数据包处理自动包数据包事务处理6数据通道的MultiCeiver TM与nRF24L01嵌入式兼容空中数据速率250kbps 和1Mbps，与nRF2401A，nRF2402, nRF24E1和nRF24E2兼容低BOM成本±60ppm 16MHz晶振容许5V输入紧凑的20引脚4x4mm QFN封装应用无线 PC外围设备鼠标,键盘和遥控器三和一桌面捆绑先进的媒体中心遥控器网络电话耳机游戏控制器蓝牙模块运动手表和传感器消费电子产品射频遥控器家庭和商业自动化超低功率无线传感器网络RFID 射频识别资产跟踪系统玩具免责条款北欧半导体ASA有权做出随时更改,提高产品可靠性、功能或设计,不另行通知。
北欧半导体ASA不承担由于应用程序或使用任何所述产品或电路引起的责任。
所有应用程序的信息咨询，不构成说明书的组成部分。
极限值超过一个或多个限制的应力可能会造成设备永久性损坏。
这些应力等级只有在这样或那样的操作环境中提出，在规范中没有给出。
长时间暴露在限制值附近可能会影响设备的可靠性。
生命支持应用这些产品并非为因故障会引起人身伤害的维生装备,设备或系统设计的。
北欧半导体ASA客户使用或出售这些产品，他们将自担风险并同意完全赔偿北欧半导体ASA因使用不当或销售行为造成任何损害。
详细联系方式访问www.nordicsemi.no进入北欧半导体销售办事处和全世界的分销商网站总办公室：Otto Nielsens vei 127004 Trondheim电话: +47 72 89 89 00传真: +47 72 89 89 89www.nordicsemi.no写作惯例本产品规范遵循一套排版规则,文档一致,容易阅读。
LMK04011BISQENOPB;LMK04000BISQENOPB;LMK04002BISQENOPB;中文规格书,Datasheet资料
LMK04000,LMK04001,LMK04002,LMK04010, LMK04011,LMK04031,LMK04033LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLsLiterature Number: SNOSAZ8JLMK04000 FamilyLow-Noise Clock Jitter Cleaner with Cascaded PLLs1.0 General DescriptionThe LMK04000 family of precision clock conditioners pro-vides low-noise jitter cleaning, clock multiplication and distri-bution without the need for high-performance voltage con-trolled crystal oscillators (VCXO) module. Using a cascaded PLLatinum™ architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance. The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator cir-cuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock gen-eration. PLL1 can be configured to either work with an exter-nal VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the inte-grated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default start-up clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.2.0 Features■Cascaded PLLatinum PLL Architecture—PLL1■Phase detector rate of up to 40 MHz■Integrated Low-Noise Crystal Oscillator Circuit■Dual redundant input reference clock with LOS —PLL2■Normalized [1 Hz] PLL noise floor of -224 dBc/Hz■Phase detector rate up to 100 MHz■Input frequency-doubler■Integrated Low-Noise VCO■Ultra-Low RMS Jitter Performance—150 fs RMS jitter (12 kHz – 20 MHz)—200 fs RMS jitter (100 Hz – 20 MHz)■LVPECL/2VPECL, LVDS, and LVCMOS outputs■Support clock rates up to 1080 MHz■Default Clock Output (CLKout2) at power up■Five dedicated channel divider and delay blocks■Pin compatible family of clocking devices■Industrial Temperature Range: -40 to 85 °C■ 3.15 V to 3.45 V operation■Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)3.0 Target Applications■Data Converter Clocking■Wireless Infrastructure■Networking, SONET/SDH, DSLAM■Medical■Military / Aerospace■Test and Measurement■Video30027140PLLatinum™ is a trademark of National Semiconductor Corporation.TRI-STATE® is a registered trademark of National Semiconductor Corporation.© 2011 National Semiconductor K04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLsNSID PROCESS 2VPECL / LVPECLOUTPUTSLVDS OUTPUTSLVCMOS OUTPUTSVCOLMK04000BISQ BiCMOS 3 41185 to 1296 MHLMK04001BISQ BiCMOS 3 41430 to 1570 MHLMK04002BISQ BiCMOS 3 41600 to 1750 MHLMK04010BISQ BiCMOS 5 1185 to 1296 MHLMK04011BISQ BiCMOS 5 1430 to 1570 MHLMK04031BISQ BiCMOS 2221430 to 1570 MHLMK04033BISQBiCMOS 2221840 to 2160 MHNSID CLKout0CLKout1CLKout2CLKout3CLKout4LMK04000BISQ 2VPECL / LVPECL LVCMOS x 2LVCMOS x 22VPECL / LVPECL 2VPECL / LVPECLMK04001BISQ 2VPECL / LVPECL LVCMOS x 2LVCMOS x 22VPECL / LVPECL 2VPECL / LVPECLMK04002BISQ 2VPECL / LVPECLLVCMOS x 2LVCMOS x 22VPECL / LVPECL 2VPECL / LVPECLMK04010BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECLMK04011BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECLMK04031BISQ LVDS 2VPECL / LVPECL LVCMOS x 22VPECL / LVPECL LVDS LMK04033BISQLVDS2VPECL / LVPECLLVCMOS x 22VPECL / LVPECLLVDS 2L M K 0400030027101 04000 Family1.0 General Description .........................................................................................................................2.0 Features ........................................................................................................................................3.0 Target Applications ..........................................................................................................................4.0 Functional Block Diagram .................................................................................................................5.0 Connection Diagram ........................................................................................................................6.0 Pin Descriptions .............................................................................................................................7.0 Absolute Maximum Ratings ..............................................................................................................8.0 Package Thermal Resistance ............................................................................................................9.0 Recommended Operating Conditions ................................................................................................10.0 Electrical Characteristics ............................................................................................................... 111.0 Serial Data Timing Diagram .......................................................................................................... 212.0 Charge Pump Current Specification Definitions .. (2)12.1 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. CHARGE PUMP OUTPUTVOLTAGE ................................................................................................................................ 212.2 CHARGE PUMP SINK CURRENT VS. CHARGE PUMP OUTPUT SOURCE CURRENTMISMATCH .............................................................................................................................. 212.3 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. TEMPERATURE ................ 213.0 Typical Performance Characteristics . (2)13.1 CLOCK OUTPUT AC CHARACTERISTICS ............................................................................. 214.0 Features . (2)14.1 SYSTEM ARCHITECTURE ................................................................................................... 214.2 REDUNDANT REFERENCE INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*)................................... 214.3 PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS)....................................................................... 214.4 INTEGRATED LOOP FILTER POLES ..................................................................................... 214.5 CLOCK DISTRIBUTION ....................................................................................................... 214.6 CLKout DIVIDE (CLKoutX_DIV, X = 0 to 4).............................................................................. 214.7 CLKout DELAY (CLKoutX_DLY, X = 0 to 4)............................................................................. 214.8 GLOBAL CLOCK OUTPUT SYNCHRONIZATION (SYNC*)....................................................... 214.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT .................................................................... 215.0 Functional Description (2)15.1 ARCHITECTURAL OVERVIEW .............................................................................................. 215.2 PHASE DETECTOR 1 (PD1)................................................................................................. 215.3 PHASE DETECTOR 2 (PD2)................................................................................................. 215.4 PLL2 FREQUENCY DOUBLER .............................................................................................. 215.5 INPUTS / OUTPUTS . (2)15.5.1 PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*).......................................... 215.5.2 PLL2 OSCin / OSCin* Port ........................................................................................... 215.5.3 CPout1 / CPout2........................................................................................................ 215.5.4 Fout .......................................................................................................................... 215.5.5 Digital Lock Detect 1 Bypass ........................................................................................ 215.5.6 Bias .. (2)16.0 General Programming Information (2)16.1 RECOMMENDED PROGRAMMING SEQUENCE .................................................................... 216.2 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET .................................... 316.3 REGISTER R0 TO R4.. (3)16.3.1 CLKoutX_DIV: Clock Channel Divide Registers .............................................................. 316.3.2 EN_CLKoutX: Clock Channel Output Enable .................................................................. 316.3.3 CLKoutX_DLY: Clock Channel Phase Delay Adjustment .................................................. 316.3.4 CLKoutX/CLKoutX* LVCMOS Mode Control ................................................................... 316.3.5 CLKoutX/CLKoutX* LVPECL Mode Control .................................................................... 316.3.6 CLKoutX_MUX: Clock Output Mux ................................................................................ 316.4 REGISTERS 5, 6.................................................................................................................. 316.5 REGISTER 7.. (3)16.5.1 RESET bit ................................................................................................................. 316.6 REGISTERS 8, 9.................................................................................................................. 316.7 REGISTER 10 (3)16.7.1 RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit ............................................... 316.8 REGISTER 11 (3)16.8.1 CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer Mode Control ...................................... 316.8.2 CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits .................. 316.8.3 CLKinX_LOS ............................................................................................................. 316.8.4 PLL1 Reference Clock LOS Timeout Control .................................................................. 316.8.5 LOS Output Type Control ............................................................................................ 316.9 REGISTER 12 (3)4L M K 0400004000 Family16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control(PLL1_CP_POL) (36)16.10 REGISTER 13 (36)16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable (36)16.10.2 EN_Fout: Fout Power Down Bit (36)16.10.3 CLK Global Enable: Clock Global enable bit (36)16.10.4 POWERDOWN Bit -- Device Power Down (36)16.10.5 EN_PLL2 REF2X: PLL2 Frequency Doubler control bit (36)16.10.6 PLL2 Internal Loop Filter Component Values (36)16.10.7 PLL1 CP TRI-STATE and PLL2 CP TRI-STATE (37)16.11 REGISTER 14 (37)16.11.1 OSCin_FREQ: PLL2 Oscillator Input Frequency Register (37)16.11.2 PLL2_R: PLL2_R Counter (37)16.11.3 PLL_MUX: LD Pin Selectable Output (37)16.12 REGISTER 15 (38)16.12.1 PLL2_N: PLL2_N Counter (38)16.12.2 PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control (38)16.12.3 VCO_DIV: PLL2 VCO Divide Register (38)17.0 Application Information (39)17.1 SYSTEM LEVEL DIAGRAM (39)17.2 LDO BYPASS AND BIAS PIN (40)17.3 LOOP FILTER (40)17.4 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS (43)17.5 POWER SUPPLY CONDITIONING (43)17.6 THERMAL MANAGEMENT (43)17.7 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) (44)17.8 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) (47)17.8.1 Termination for DC Coupled Differential Operation (47)17.8.2 Termination for AC Coupled Differential Operation (47)17.8.3 Termination for Single-Ended Operation (48)17.9 DRIVING CLKin AND OSCin INPUTS (49)17.9.1 Driving CLKin Pins with a Differential Source (49)17.9.2 Driving CLKin Pins with a Single-Ended Source (49)17.10 ADDITIONAL OUTPUTS WITH AN LMK04000 FAMILY DEVICE (49)17.11 OUTPUT CLOCK PHASE NOISE PERFORMANCE VS. VCXO PHASE NOISE (49)18.0 Physical Dimensions (53)19.0 Ordering Information (53)5.0 Connection Diagram48-Pin LLP Package30027102 6L M K 0400004000 Family Pin Number Name(s)I/O Type Description1GND GND Ground (For Fout Buffer)2Fout O ANLG VCO Frequency Output Port1PWR Power Supply for VCO Output Buffer 3VCC4CLKuWire I CMOS Microwire Clock Input5DATAuWire I CMOS Microwire Data Input6LEuWire I CMOS Microwire Latch Enable Input7NC No Connection2PWR Power Supply for VCO8VCC9LDObyp1ANLG LDO Bypass, bypassed to ground with a 10 µFcapacitor10LDObyp2ANLG LDO Bypass, bypassed to ground with a 0.1 µFcapacitor11GOE I CMOS Global Output Enable12LD O CMOS Lock Detect and PLL multiplexer Output3PWR Power Supply for CLKout013VCC14CLKout0O LVDS/LVPECL Clock Channel 0 Output15CLKout0*O LVDS/LVPECL Clock Channel 0* Output16DLD_BYP ANLG DLD Bypass, bypassed to ground with a 0.47 µFcapacitor17GND GND Ground (Digital)18V4PWR Power Supply for DigitalCC5PWR Power Supply for CLKin buffers and PLL1 R-divider 19VCC20CLKin0I ANLG Reference Clock Input Port for PLL1 - AC or DCCoupled (Note 1)21CLKin0*I ANLG Reference Clock Input Port for PLL1 (complimentary)- AC or DC Coupled (Note 1)6PWR Power Supply for PLL1 Phase Detector and Charge 22VCCPump23CPout1O ANLG Charge Pump1 Output7PWR Power Supply for PLL1 N-Divider 24VCC25CLKin1I ANLG Reference Clock Input Port for PLL1 - AC or DCCoupled (Note 1)26CLKin1*I ANLG Reference Clock Input Port for PLL1 (complimentary)- AC or DC Coupled (Note 1)27SYNC*I CMOS Global Clock Output Synchronization28OSCin I ANLG Reference oscillator Input for PLL2 - AC Coupled29OSCin*I ANLG Reference oscillator Input for PLL2 - AC Coupled8PWR Power Supply for OSCin Buffer and PLL2 R-Divider 30VCC9PWR Power Supply for PLL2 Phase Detector and Charge 31VCCPump32CPout2O ANLG Charge Pump2 Output10PWR Power Supply for VCO Divider and PLL2 N-Divider 33VCC34CLKin0_LOS O LVCMOS Status of CLKin0 reference clock input35CLKin1_LOS O LVCMOS Status of CLKin1 reference clock input36Bias I ANLG Bias Bypass. AC coupled with 1 µF capacitor to Vcc111PWR Power Supply for CLKout137VCC38CLKout1O LVPECL/LVCMOS Clock Channel 1 Output39CLKout1*O LVPECL/LVCMOS Clock Channel 1* Output12PWR Power Supply for CLKout240VCC41CLKout2O LVPECL/LVCMOS Clock Channel 2 Output 42CLKout2*O LVPECL/LVCMOSClock Channel 2* Output 43V CC 13 PWR Power Supply for CLKout344CLKout3O LVPECL Clock Channel 3 Output 45CLKout3*O LVPECL Clock Channel 3* Output 46V CC 14 PWR Power Supply for CLKout447CLKout4O LVDS/LVPECL Clock Channel 4 Output 48CLKout4*O LVDS/LVPECLClock Channel 4* OutputDAPDAPDIE ATTACH PAD, connect to GNDNote 1:The reference clock inputs may be either AC or DC coupled. 8L M K 04000If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Parameter Symbol Ratings Units Supply Voltage (Note 5)V CC-0.3 to 3.6V Input Voltage V IN-0.3 to (V CC + 0.3)V Storage Temperature Range T STG-65 to 150°CLead Temperature (solder 4 sec)T L+260°CDifferential Input Current (CLKinX/X*, OSCin/OSCin*)IIN± 5mANote 2:"Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only to the test conditions listed.Note 3:This device is a high performance RF integrated circuit with an ESD rating up to 8 KV Human Body Model, up to 300 V Machine Model and up to 1,250 V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations.Note 4:Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.Note 5:Never to exceed 3.6 V.8.0 Package Thermal ResistancePackageθJAθJ-PAD (Thermal Pad) 48-Lead LLP (Note 6)27.4° C/W 5.8° C/WNote 6:Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.9.0 Recommended Operating ConditionsParameter Symbol Condition Min Typical Max UnitAmbient Temperature TAVCC= 3.3 V-402585°CSupply Voltage VCC3.15 3.3 3.45V04000 Family分销商库存信息: NATIONAL-SEMICONDUCTORLMK04011BISQE/NOP B LMK04000BISQE/NOPBLMK04002BISQE/NOPBLMK04031BISQE/NOP B LMK04033BISQE/NOPBLMK04001BISQE/NOPBLMK04010BISQE/NOP B LMK04011BISQX/NOPBLMK04031BISQX/NOPBLMK04033BISQX/NOP B LMK04000BISQX/NOPBLMK04001BISQX/NOPBLMK04002BISQX/NOP B LMK04010BISQX/NOPBLMK04011BISQ/NOPBLMK04031BISQ/NOPB LMK04033BISQ/NOPB LMK04000BISQ/NOPB LMK04001BISQ/NOPB LMK04002BISQ/NOPB LMK04010BISQ/NOPB LMK04002BEVAL LMK04033BEVAL LMK04000BEVAL/NOPBLMK04000BEVALXO LMK04033BEVAL/NOPB LMK04031BEVAL/NO PBLMK04031BEVALXO。
IRLML0040TRPBF;中文规格书,Datasheet资料
100 D = 0.50
0.20
10
0.10
0.05
0.02
1
0.01
0.1
0.01
0.001 1E-006
1E-005
Fig 4. Normalized On-Resistance Vs. Temperature 3
ID, Drain-to-Source Current (A)
/
IRLML0040TRPbF
C, Capacitance (pF)
10000 1000 100
VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd
IRLML0040TRPbF
ID, Drain Current (A)
4.2
3.6
3
2.4
1.8
1.2
0.6
0 25
50
75
100 125 150
TA , Ambient Temperature (°C)
Fig 9. Maximum Drain Current Vs. Ambient Temperature
4
1
1msec
0.1 TA = 25°C Tj = 150°C Single Pulse
10msec
0.01
0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
/
PD @TA = 25°C
Maximum Power Dissipation
BLF2022-40中文资料
DISCRETE SEMICONDUCTORS
DATA SHEET
M3D750
BLF2022-40 UHF power LDMOS transistor
Preliminary specification 2001 April 05
元器件交易网
1
BLF2022-40
PINNING PIN 1 2 3 drain gate source, connected to flange DESCRIPTION
APPLICATIONS • Common source class-AB operation for PCN and PCS applications in the 2000 to 2200 MHz frequency range • Suitable for GSM, Edge, CDMA and WCDMA applications. DESCRIPTION Silicon N-channel enhancement mode lateral D-MOS transistors encapsulated in a 2-lead SOT608A flange package with a ceramic cap. The common source is connected to the mounting flange. Fig.1 Simplified outline SOT608A.
SOT608A
Package under development
D
Philips Semiconductors reserves the right to make changes without notice.
A F
3
VLF4012AT-4R7M1R1;VLF4012AT-100MR79;VLF4012AT-3R3M1R3;VLF4012AT-2R2M1R5;中文规格书,Datasheet资料
Inductance tolerance(%) ±30 ±20 ±20 ±20 ±20 ±20 ±20
Test frequency (kHz) 100 100 100 100 100 100 100
DC resistance( ) max. 0.054 0.1 0.15 0.2 0.31 0.46 1.20 typ. 0.047 0.091 0.13 0.1R7
2.8±0.2
1.4max. Dimensions in mm
RECOMMENDED PC BOARD PATTERN
1.2 2.1 3.4 Dimensions in mm
Inductance [at 1/2 Idc1]3 (µH) 1 2.2 3.3 4.7 6.8 10 22
• All specifications are subject to change without notice.
/
001-04 / 20120310 / e531_vlf
(3/17)
Inductors for Power Circuits Wound/STD • Magnetic Shielded
Part No. VLF3014AT-1R0N1R7 VLF3014AT-2R2M1R2 VLF3014AT-3R3M1R0 VLF3014AT-4R7MR90 VLF3014AT-6R8MR72 VLF3014AT-100MR59 VLF3014AT-220MR37
1
SHAPES AND DIMENSIONS
VLF-MT Series VLF302510MT
With the VLF302510MT Series, a DC to DC converter with topclass voltage conversion efficiency for similar size products was achieved by optimizing the magnetic material and configuration. These products are optimal for use as choke coils in switching power supplies such as those in mobile devices requiring spacesaving design. FEATURES • Miniature size Mount area: 3.02.5mm Low profile: 1.0mm max. height • Generic use for portable DC to DC converter line. • High magnetic shield construction should actualize high resolution for EMC protection. • The products contain no lead and also support lead-free soldering. • The products is halogen-free. • It is a product conforming to RoHS directive. APPLICATIONS Smartphones, cellular phones, DSCs, DVCs, HDDs, LCD displays, compact power supply modules, etc. SHAPES AND DIMENSIONS