CMM6003-SC_07中文资料

合集下载

中文版AS_4777[1].

配电网的另一个术语。
3.4逆变器
使用半导体器件在直流电源或者负载和交流电源或者负载之间传输能量的装置。
说明：尽管本标准的编写基础为来自于直流电源（例如光电池阵）的再生能源，但是本标准可以用于来自于可变的交流电源系统（例如风力涡轮机或者微型水电系统）的能源，因此，在本标准中，使用半导体器件的交流变流器同样可以视为逆变器，因为本标准中的这些要求适用于这种系统。
通过监控配电网避免形成孤岛的方法。
3.9机电式开关
OFF状态导致导线物理分离（例如机械继电器）的电气开关。这不包括晶体管或者类似的半导体器件。
3.10不间断电源（UPS）系统
电源系统包含逆变器、开关、控制回路以及在配电网电源中断时用来保持负载电源连续性的一种蓄能设备。
4通用要求和安全要求
4.1概述
逆变器能源系统电网防护应当通过电网保护装置提供。这不排除电网保护装置作为逆变器整体一部分的情况，也不排除用来保护逆变器能源系统（包含多重逆变器）的单一电网保护装置。
（a）单相系统的Vmin应该在200-230V范围内，三相系统在350-400V范围内；
（b）单相系统的Vmax应该在230-270V范围内，三相系统在400-470V范围内；
（c）fmin应该在45-50 Hz范围内。
（d）fmax应该在50-55Hz范围内。
Vmax、Vmin、fmax和fmin范围可以预置或者可编程序。Vmax、Vmin、fmax和fmin值可以与相关电力分销商协商。电网保护装置的整定值不应超过逆变器的容量。
澳大利亚标准™
能源系统通过逆变器并网
第3部分电网保护要求
最初作为AS 4777.3—2002发布。
2005年再版
版权所有
© Standards Australia

马兰士PM6003

ቤተ መጻሕፍቲ ባይዱ
应用连接 ............................................................................................................. 10
连接遥控器插孔 ...............................................................................................................10
「根据电子信息产品污染控制管理办法的有毒・有害物质或元素的标识表」
零部件名称对象零部件电路板组件，・安装插入零部件，电路板 ( 不包括特定电子零部件 ) 顶盖，底盖，底壳，框架，垫片，螺丝等 ( 金属，塑胶 )， ( 包含的接合材料 ) 变压器，插入物，电源插座，电源用大型电解质电容器等电子零部件，机内连结线遥控器 /AC 适配器、电源线、 RCA 信号线等附件，包装铅 (Pb) 有毒有害物质或元素备注多溴多溴汞镉六价铬联苯二苯醚 (Hg) (Cd) (Cr6+) (PBB) (PBDE) ○ × ○ ○ ○
目录
称与功能基
功能 ...................................................................................................................... 2 简介 ...................................................................................................................... 1 目录 ...................................................................................................................... 1

SC-003 FMEA手册

FMEA 手册
FMEA 手册
文件编号
SC-003
文件版本
A/2
生效日期
2006/03/30
第1 页共6 页
1. 概述明确失效模式和后果分析的概念，规范公司运用和实施FMEA 的流程，指导产品设计与过程开发中运用FMEA 技术。本手册参考《潜在失效模式及后果分析参考手册》第三版编写。 2. 范围适用于新产品设计、新产品过程开发时，失效模式与后果影响分析；适用于设计/过程变更、供应商/材料变更以及其他影响产品/过程的变更时，FMEA 的评审与更新。3. 术语和定义3.1 FMEA（Failure Mode and Effects Analysis）：一个系统化的过程用以识别尚未发生的潜在失效并试图将相应的风险消除或减至最小。可以使设计过程更加完善，以确保顾客满意。其目的是：3.1.1 发现、评价产品/过程中潜在的失效及其结果；3.1.2 找到能够避免或减少这些潜在失效发生的措施；3.1.3 将上述过程文件化。3.2. DFMEA：Design Failure Mode & Effects Analysis 的缩写，即设计失效模式与后果分析；3.3. PFMEA：Process Failure Mode & Effects Analysis 的缩写，即过程失效模式与后果分析；3.4. 潜在的失效模式3.4.1 潜在的设计失效模式：指系统、子系统或零部件有可能未达到设计意图的形式；3.4.2 潜在的过程失效模式：指过程有可能不能满足过程功能/要求栏中所描述的过程要求和/或设计意图。3.4.3 失效：在规定条件下(环境、操作、时间等)不能完成既定功能或产品参数值不能维持在规定的上下限之间。 3.5. 潜在失效后果：是指失效模式对系统功能的影响和/或对顾客产生的影响。3.6. 严重度(S)：是给定失效模式最严重的影响后果的级别（是潜在失效模式对顾客的影响后果的严重程度的评价指标）。3.7. 频度(O)：是指具体的失效起因/机理发生的频率。3.8. 探测度(D)：是指由设计控制可探测的可能性，或由现行过程控制方法找出失效起因/机理过程缺陷的可能性。3.9. 风险系数（RPN）：风险系(RPN)是严重度(S)，频度(O)和探测度(D)的乘积。3.10. 特性：一种可测量的产品特性/过程特性。3.11. 过程特殊特性：是指在制造和组装过程中，必须采取措施以控制其变异并确保其在预定的目标值之内的过程特性。

CC8800 系列 CMTS 产品规格书说明书

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用户服务热线：联系电话：+86-10-58858351（周一至周五8:30－17:30）传真：+86-10-58858592公司地址：北京海淀区上地东路1号盈创动力大厦A2座6层邮编：100085登录网址：或目录第1章产品简介 (1)1.1 产品介绍 (1)1.2 产品特点 (1)第2章性能与规格 (3)2.1 简介 (3)2.2 整机规格 (4)2.3 DOCSIS模块 (4)2.4 电源模块 (8)2.5 射频模块 (9)2.6 （可选）CWDM组件规格 (10)2.7 （可选）工业级SFP+光模块 (11)2.7.1 10GE以太网光模块 (11)2.7.2 ONU侧10G EPON光模块 (12)2.7.3 ONU侧XG-PON光模块 (12)第1章产品简介DOCSIS定义了一种利用有线同轴网络中传输数据业务的规范，是稳定、可靠的运营级同轴网络国际标准，并且经过了多年的实际运营检验。

hes d 6003标准

hes d 6003标准英文回答：HES D 6003 Standard.HES D 6003 is a standard developed by the Health and Environmental Sciences Institute (HESI) that establishes specific requirements and guidelines for the design, construction, and operation of healthcare facilities. It is widely recognized as the industry standard for healthcare facility design and construction in the United States.Key Requirements of HES D 6003。

Functional Requirements: HES D 6003 outlines the functional requirements for healthcare facilities,including space planning, circulation, and infectioncontrol measures. It ensures that facilities are designedto meet the specific needs of patients, staff, and visitors.Construction Requirements: The standard specifies technical requirements for the construction of healthcare facilities, including structural design, fire protection, and mechanical systems. It aims to ensure that facilities are safe, durable, and compliant with relevant building codes.Equipment Requirements: HES D 6003 provides guidelines for the selection and installation of medical equipment and technology. It helps healthcare providers equip their facilities with the latest advancements to enhance patient care.Environmental Requirements: The standard addresses environmental factors that can impact patient health andwell-being, such as indoor air quality, lighting, and acoustics. It promotes the creation of a healing environment that supports patient recovery.Sustainability Requirements: HES D 6003 encourages the adoption of sustainable design and construction practicesto minimize environmental impact and reduce operating costs.It provides guidance on energy efficiency, water conservation, and waste management.Benefits of HES D 6003 Compliance.Improved Patient Outcomes: Well-designed healthcare facilities promote infection control, reduce errors, and enhance patient safety.Increased Efficiency: Optimized space planning and circulation improve workflow and reduce staff time spent on non-patient care activities.Enhanced Patient Satisfaction: Comfortable and welcoming facilities create a positive experience for patients and their families.Reduced Operating Costs: Sustainable design practices can lead to lower energy consumption, water usage, and waste disposal expenses.中文回答：HES D 6003 标准。

AN-6003资料

AN-6003“Shoot-through” in Synchronous Buck ConvertersJon KleinPower Management ApplicationsAbstractThe synchronous buck circuit is in widespread use to provide “point of use” high current, low voltage power for CPU’s, chipsets, peripherals etc. In the synchronous buck converter, the power stage has a “high-side” (Q1 below) MOSFET to charge theinductor, and a “Low-side” MOSFET which replaces a conventional buck regulator’s “catch diode” to provide a low-loss recirculation path for the inductor current.V Figure 1. Synchronous Buck output stage Shoot-through is defined as the condition when both MOSFETs are either fully or partially turned on,providing a path for current to “shoot through” from V IN to GND. To minimize shoot-through,synchronous buck regulator IC’s employ one of two techniques to ensure “break before make” operation of Q1 and Q2 to minimize shoot-through:1. Fixed “dead-time”: A MOSFET is turned off,then a fixed delay is provided before the low-side is turned on. This circuit is simple and usually effective, but suffers from its lack of flexibility if a wide range of MOSFET gate capacitances are to be used with a givencontroller. Too long a dead-time means high conduction losses. Too short a dead time can cause shoot-through. A fixed dead-timetypically must err on the “too long” side to allow high C GS MOSFETs to fully discharge before turning on the complementary MOSFET.2. Adaptive gate drive: This circuit looks at theV GS of the MOSFET that’s being driven off to determine when to turn on the complementary MOSFET. Theoretically, adaptive gate drives produce the shortest possible dead-time for a given MOSFET without producing shoot-through.In practice, a combination of adaptive and fixed produces the best results, and is typically what is in today’s PWM controllers and gate drivers as shown in Figure 2Figure 2. Typical Adaptive Gate driveEven though there apparently is a “break before make” action by the controller, shoot-through can still occur when the High-side MOSFET turns on,due to Gate Step.Shoot-through is very difficult to measure directly.Shoot-through currents persist for only a few nS,hence the added inductance in a current probe drastically affects the shoot-through waveform.Shoot-through manifests itself typically as increased ringing, reduced efficiency, higher MOSFET temperatures (especially in Q1) and higher EMI.This paper will provide analytical techniques to predict shoot-through, and methods to reduce it.Shoot-through in Synchronous Buck RegulatorsAN-6003“Gate Step” – The shoot-through culpritIf the adaptive circuits are working, then we shouldn’t see any shoot-through, right?Not exactly. Most shoot-through occurs when the high-side MOSFET is turned on. The high dv/dT on the SW node (Drain of the low-side MOSFET)couples charge through C GD . This drives the gate positive at the very moment when the driver is trying to hold the gate low. C GD and C GS form a capacitive voltage divider, which attenuates the gate step such that the worst case peak amplitude of the gate step (V STEP ) seen is:−•••≈ +•−)C C (R T R IN GD T )PK (STEP GS GD T R e 1T V C R V (1a)Where R T = R DRIVER + R GATE + R DAMPING (see Figure 5),and T R is the rise-time of the SW node.The limiting case is when T R = 0. ThenGSGD GD IN )MAX (STEP C C C V V +•≈(1b)This expression only illustrates the AC portion of the gate step. The gate step is injected onto whatever voltage the MOSFET’s gate has discharged to. For example, if the switch node rises when VGS = 1V,and the gate step amplitude is 2V, instantaneously there will be 3 V GS which is more than enough to have a high instantaneous current through both MOSFETs. It’s important, therefore that adaptive gate drive circuits allow sufficient delay to prevent the high side from turning on before the low-side V GS is discharged down to a few hundred mV.An illustration of gate step is seen below.0123456020406080t (nS)V G S-202468101214VSW NODE VOLTAGELS MOSFET GATEFigure 3. Gate Step for V IN .=12V.123456020406080t (nS)V G S-50510152025VSW NODE VOLTAGELS MOSFET GATEFigure 4. Gate Step for V IN .=20VFurther exacerbating the problem for adaptivecircuits is the fact that the adaptive comparator is not actually sensing the voltage at the internal gate junction of the MOSFET. As seen in Figure 5, the internal MOSFET’s gate voltage has an unavoidable internal R GATE resistance. In addition, some designers like to have a “damping” resistor in series with the gates of MOSFETs that are located physically far away from their gate drives. This creates a bigger problem for the adaptive gate drive circuit. These series resistances form a voltage divider with the internal pull-down resistance of the low-side gate drive of the IC, causing it to think the gate voltage is lower than it really is when it decides to release the High-side driver.Figure 5. Resistance in the gate drive path attenuates the voltage at the MOSFET gate node.When there is 1V at the pin of the IC, the internal MOSFET V GS is:()DampingGATE DRIVER DRIVER)I (GS R R R R V 1V ++•=Consider an example where:R DRIVER = 2Ω,R GATE = 1.2ΩR DAMPING = 5ΩShoot-through in Synchronous Buck Regulators AN-6003When the adaptive gate circuit switches, the internal MOSFET gate voltage will be:()V 1.452.122V1=Ω++•ΩIn this example, if there were no delay in the circuit,the HDRV would turn on when the low-sideMOSFET has just begun to discharge, causing a very high shoot-through current.Much of the problem in the above circuit is the damping resistor. If a damping resistance isnecessary, place a Schottky diode across the resistor (as shown below) to reduce the effect the damping resistor will have on the adaptive gate drive.Figure 6. Schottky diode reduces dampingresistor error in adaptive gate driveWhen using the schottky, the internal gate node will be at:()GATE DRIVER DRIVER)I (GS R R R V 15.0V +•+=or 2.1V for our example. A dramatic improvement.Furthermore, the Schottky reduces the duration of the shoot-through step, since only R GATE + R DRIVER will be discharging C GS , rather than the sum of R GATE + R DAMPING + R DRIVER .Table 1 below illustrates the performanceimprovement in our example with and without the Schottky diode:Conditions: Typical low-side MOSFET, 25nS delay from comparator sense to beginning of SW node rise, 19V IN , 10nS SW node rise time.Table 1 . Peak Currents with and withoutSchottky with R DAMPING = 5Ω .MOSFET ChoicesMOSFET characteristics can have a dramatic effect on how much shoot-through current can be induced by the gate step. The worst case for shoot-through is an infinitely fast (0 rise time) on the drain node. The amount of gate step is largely determined by the ration of C GS and C GD . Once the size of the gate step is determined (eq. 1 above), the peak magnitude of the shoot-through current can be calculated as :())MIN (TH STEP(MAX)M )MAX (PEAK V V G K I −••≈(2)where G M is the transconductance (in S, or A/V)given in the datasheet. While only a smallpercentage of MOSFETs exhibit V TH(MIN) at room temperature, V TH goes down with increasing junction temperature, therefore V TH(MIN) is a good proxy for the V TH at the operating junction temperature of the MOSFET. Subsequent calculations use V TH(MIN) for this reason.G M is not really a contstant, however, and its value is greatly reduced low enhancement voltages (V GS -V TH ).In these calculations we use a factor "K" from the graph below, which is typical of G M with low values of enhancement. The X axis of Figure 7 is calculated as)MIN (TH )MIN (TH GS V V V −0.00.20.40.60.81.00%50%100%150%200%250%300%Normalized Enhancement VoltageK (G M M u l t i p le r )Figure 7 G M factor (K)Table 2 shows the relevant MOSFET characteristics which determine the maximum shoot-through current.Table 2 . Low-Side MOSFET CharacteristicsShoot-through in Synchronous Buck Regulators AN-6003Each of the MOSFETs represented is from a different process and has different ratios of internal capacitance.Table 3. Maximum V STEP and I SHOOTTHROUGH @V IN = 19V and V GS(START) = 0V.Table 3 assumes that the V GS has dropped to 0 before the SW node rises when HDRV turns on. Asdemonstrated above, the smallest amplitude of V STEP comes from MOSFET2 and MOSFET5, which are low-threshold devices. Low threshold in large part is due to a thin gate oxide, giving the MOSFET a high GDGSC C ratio, which attenuates V STEP . more than other MOSFETs.Also, Table 3 only shows the theoretical peak current in Q2 due to the gate step. In a real converter,parasitic inductance limits the rise in current to4A/nS. Even for the MOSFET4, the gate pulse only stays above threshold for about 5nS, so the shoot-through current would be further limited.An additional shortcoming of the simplifiedcalculations of Table 3 is the assumption that SW node turn-on begins when V GS of the low-side is at 0.As we saw from the earlier discussion, this may not be the case.Reducing gate step by slowing down Q1 rise timeUsually, designers attempt to achieve the fastest rise-time possible on the High-Side MOSFET in order to minimize switching losses. A simplified expression for turn-on losses (P (TURN-ON)) for the high-side MOSFET is:•••≈−2I V T F P OUT IN R SW ON TURN (3)where T R is the rise-time of the MOSFET. A veryfast rise-time (high dtdVon SW) is desirable to minimize high-side power dissipation, but if it results in a large gate-step, causing shoot-through, thedissipation effect can be greater than the dissipation induced by slowing the rise time. In some situations this is the only practical approach to eliminate shoot-through.As can be seen in Figure 8, slowing down the rise time has a dramatic effect on the amplitude of V STEP that is coupled into the Low-side MOSFET gate. T R slowdown has the added benefit of reducing EMI, but comes at a cost of efficiency loss . Figure 8 and subsequent tables were simulated with MOSFETs typical of those used in notebook PC’s (2 in parallel)with 15A output current and 19V IN . Figure 8 assumes that the SW node begins to rise when the internal gate node has discharged down to 0.5V.Shoot-through in Synchronous Buck Regulators AN-60030.00.20.40.60.81.01.21.41.61.82.00510152025303519V RiseTime(nS)V (S T E P ) P e a kFigure 8 . Effect of SW node rise-time on V STEPVIN=19V, SW rise starts @ V GS(Q2) = 0.5VTable 4 shows the power loss due to shoot-through for each MOSFET.The major component of switching loss during Q1turn-on is:2I V F t P OUTIN SW R ON TURN •••≈−(3)and is computed in the right-most column for each rise-time in Table 4 for I= 15A.Table 4. Worst case (Min V TH ) shoot-throughpower loss (mW)SW rise starts @ V GS(Q2) = 0.5VIn most cases, the shoot-through is negligble, so slowing down high-side rise-time would not be a prudent choice, since the more power would be lost in slowing down the rise time than power saved by eliminating shoot-through.If, the controller's gate drive starts to turn Q1 on before allowing the internal node of Q2 to discharge,SW will rise when there is still a substantial V GS on Q2 as shown is Table 5. Slowing down Q1 can thenbe an effective strategy to reduce shoot-through losses.Table 5. Worst case (Min V TH ) shoot-throughpower loss (mW)SW rise starts @ V GS(Q2) = 1VThis is typically achieved by adding resistance (RG in Figure 2) in series with C BOOT . An approximation for T R provides a good starting point for choosing a value of RG:()RG R C T )H L (DRIVE GS R +•≈−(4)where R DRIVE(L-H) is the resistance of the IC’s high-side MOSFET gate driver when driving from low to high.Shoot-through in Synchronous Buck Regulators AN-6003DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENTOF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody or (b) support or sustain life, and (c) whose failure to perform when properly used in accordanceinstructions for use provided in the labeling, can bereasonably expected to result in a significant injury ofthe user.2. A critical component in any component of a life support,device or system whose failure to perform can bereasonably expected to cause the failure of the lifesupport device or system, or to affect its safety oreffectiveness.。

AC6003 产品描述

本文档提供AC6003设备的总体情况，便于读者全面了解产品特征。
本文档主要适用于以下工程师：
l 网络规划工程师 l 硬件安装工程师 l 调测工程师 l 数据配置工程师 l 现场维护工程师 l 网络监控工程师 l 系统维护工程师
符号约定
在本文中可能出现下列标志，它们所代表的含义如下。
符号
说明
用于警示紧急的危险情形，若不避免，将会导致人员死亡或严重的人身伤害。
2 产品应用场景................................................................................................................................... 4
2.1 旁挂式组网.................................................................................................................................................................... 4 2.2 直连式组网.................................................................................................................................................................... 7 2.3 无线回传组网................................................................................................................................................................ 8 2.4 AC 冗余备份组网........................................................................................................................................................11

PCD6003资料

INTEGRATED CIRCUIgital telephone answering machine chip
Product speciﬁcation Supersedes data of 2001 Mar 07 File under Integrated Circuits, IC17 2001 Apr 17
Philips Semiconductors
Product speciﬁcation
Digital telephone answering machine chip
CONTENTS 1 2 2.1 3 4 5 6 6.1 6.2 6.3 7 7.1 7.2 7.3 8 8.1 8.2 9 9.1 9.2 9.3 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 11 11.1 FEATURES APPLICATION SUMMARY Metalink emulation GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description Pin types FUNCTIONAL DESCRIPTION Architecture I/O summary Overview of functional description POWER SUPPLY, RESET AND START-UP Power supply Reset and start-up TICB - GENERATION AND SELECTION OF SYSTEM CLOCKS Microprocessor, DSP, CODEC and IOM clock generation System clocks Real-Time Clock generation THE MICROCONTROLLER Microcontroller architecture Memory mapping SFR mapping Microcontroller interrupts Interface to DSP Interface to Real-Time Clock (RTC) Interface to the Memory Control Block (MCB) The test registers CDTRx, PMTRx and TCTRL Interface to Timing and Control Block (TICB) Power and Interrupt Control Register (PCON) I2C-bus MSK modem LE control DSP I/O REGISTERS Interface to CODEC 13 13.1 13.2 14 14.1 14.2 15 15.1 15.2 15.3 15.4 15.5 15.6 16 16.1 16.2 17 17.1 17.2 17.3 17.4 17.5 18 19 20 20.1 20.2 20.3 20.4 20.5 21 22 23 24 12 12.1 12.2

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Operation of this device above any of these parameters may cause damage.*Operation with more than 10 dBm of input power may cause 2 dB degradation in OIP3 performance.Page 1 of 5August 2007 - Rev 07-Aug-07FeaturesDescription50 to 900 MHz Frequency Range +41 dBm Output IP3-71 dBc CTB -48 dBc CSO1.6 dB Noise Figure (@ 450 MHz)17 dB Gain 22 dBm P1dBRoHS Compliant SOT-89 SMT Package Single Power Supply +3V to +5V Voltage Rail MTBF > 100 YearsIdeal for CATV ApplicationsThe CMM6003-SC is a high dynamic range amplifier suitable for cable TV applications between 50 and 900 MHz. Thecombination of gain flatness, bandwidth, low noise figure and high third order intercept point make it ideal for cable modem, CATV distribution and laser diode driver applications. The CMM6003-SC can operate directly from 5V or 3.3V supply voltage in 75 ohm systems. The device is manufactured using a highly reliable GaAs MESFET technology with an MTBF of over 100 years at a mounting temperature of +85ºC. All devices are 100% RF (at 800Mhz) and DC tested and they come in an RoHs compliant SOT-89 package which provides excellent electrical stability and low thermal resistance.Supply Voltage RF Input Power*Storage Temperature Junction Temperature Operating Temperature Thermal Resistance+6.0 V +10 dBm -55ºC to 150ºC 150ºC -40ºC to +85ºC 59º C/WAbsolute Maximum RatingsParameter Condition Min Typ Max Unitsz H M 90050800e g n a R y c n e u q e r F Gain Externally matched 15 17 18 dB Input Return Loss Externally matched -11dB m B d 41+3P I t u p t u O Bd 3.3Noise Figure Noise Figure Output P1dBOperating Current RangeSupply Voltage@ 50 MHz @ 800 MHzdB dBm mA V 1.9081221501200.5Electrical CharacteristicsUnless otherwise specified, the following specifications are guaranteed at room temperature in a Mimix test fixture.Notes:1. T = 25°C, Vdd = 5.0, Frequency = 800 MHz, 50 Ohm system2. OIP3 measured with two tones at output power of 5 dBm/tone separated by 10 MHz.T ypical ParametersNotes:1. Typical values reflect performance in recommended application circuit.UnitsTypicalParameterFrequency Range 100 450 900 MHz Gain 17.5 17.2 16.3 dB Input Return Loss -12 -12 -11 dB Output Return Loss -16 -16 -13 dB Output IP3 40 39 37 dBm Output IP2 52 52 52 dBm Output P1dB 23 23.623.8dBm Noise Figure 3.5 1.6 2 dB CTB -72 dBc Xmod -65 dBc Supply Voltage 5 5 5 V CSO -48 dBc Current 150 150 150 mAPage 2 of 5Application Circuit: (75 )Ref Designator Value Size C1,C2,C3 1000 pF 0603L1 12 nH 0603L2 270 nH 0603FrequencyMHz 100450870GaindB 17.517.216.3Input Return Loss dB -12-12-11Output Return Loss dB-16-16-13Output P1dB dBm 2323.623.8Output IP3dBm 403937Output IP2dBm 525252Noise Figure dB 3.5 1.62CTB dBc -72CSO dBc -48XmoddBc -65Supply Voltage V 555CurrentmA150150150August 2007 - Rev 07-Aug-07CMM6003-SC: 75 Ohm Board, P1dB 101112131415161718192021222324250.10.20.30.40.50.60.70.80.91Frequency (GHz)O P 1d B (d B m )CMM6003-SC: 75 Ohm Board, Gain1414.51515.51616.51717.50.10.20.30.40.50.60.70.80.91Frequency (GHz)G a i n (d B )202224262830323436384042444648500.10.20.30.40.50.60.70.80.91Frequency (GHz)O I P 3 (d B m )CMM6003-SC: 75 Ohm Board, OIP20.10.20.30.40.50.60.70.80.91Frequency (GHz)O I P 2 (d B m )Page 3 of 5Application Circuit: (50 )UnitsTypicalParameterFrequency Range 450 800 870 MHz Gain 17.2 16.5 16.25 dB Input Return Loss -12.0-11.5-10.5 dB Output Return Loss -16 -14 -13 dB Output IP3 +396 +41 +41 dBm Output P1dB 23.6 23.723.8dBm Noise Figure 1.6 1.9 2.0dBNotes:1. Typical values reflect performance in recommended application circuit.August 2007 - Rev 07-Aug-07Page 4 of 5S-Parameters vs. FrequencyAugust 2007 - Rev 07-Aug-07Page 5 of 5Physical DimensionsOrdering InformationPart Number for Ordering DescriptionCMM6003-SC-0G00CMM6003-SC-0G0T PB-CMM6003-SC-0000PB-CMM6003-SC-00A0Matte Tin plated RoHS compliant SOT-89 surface-mount power package in bulk quantityMatte Tin plated RoHS compliant SOT-89 surface-mount power package in tape and reel50 Ohm Evaluation Board 75 Ohm Evaluation BoardWe also offer the plastic package with SnPb (Tin-Lead) or NiPdAu plating. Please contact your regional sales manager for more information regarding different plating types.August 2007 - Rev 07-Aug-07。