3.31 UV 1
EP9351(B) UG_V06
User Guide — EP9351/EP9351B_UG V0.6Low Power HDMI 1.3 ReceiverEP9351/EP9351BUser GuideV0.6Revised Date: May. 11, 2011Original Release Date: Nov. 08, 2010ExploreExplore reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Explore does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Explore products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Explore product could create a situation where personal injury or death may occur. Should Buyer purchase or use Explore products for any such unintended or unauthorized application, Buyer shall indemnify and hold Explore and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Explore was negligent regarding the design or manufacture of the part.Explore Microelectronics Confidential Proprietary1Revision HistoryVersion Number RevisionDate Author Description of Changes0.0Nov/08/2010Jerry Chen Initial Version0.1Nov/12/2010Ether Lai Revise the Pin Diagram;0.2Nov/24/2010Ether Lai Revise the BGA Package Dimension; Add descriptions to Control Registers;0.3Jan/19/2011Ether Lai Revise the BGA Package ID Information;Revise descriptions in Section 1, Overview and Features; Remove the LQFP package;0.4Feb/17/2011Ether Lai & Kyle Kuo Change the name of the BGA to VFBGA;Update the Control Register Description (EDID_RAM & HDCP Keys); Add Power consumption at DC specifications0.5Feb/22/2011Kyle Kuo Revise some wordsAdd 3.3V power consumption at DC specifications Revise A_Mute description in General Control Register30.6May/11/2022Kyle Kuo intergate EP9351 information in this specificationExplore Microelectronics Confidential Proprietary2Section 1 Introduction1.1 OverviewEP9351/EP9351B is a low power HDMI receiver which is compliant with HDMI 1.4a and supports HD Audio and Video up to 1080p. The chip integrates Equalizer Switch, HDMI core, HDCP engine and EDID RAM in a single chip.1.2 Features•On-chip HDMI Receiver core which is compliant with HDMI 1.4a specification•On-chip HDCP Engine which is compliant with HDCP 1.4 specification•On-chip EDID RAM•Supports 24-bit color mode up to 1080p•On-chip Audio Decoder which support 8-channel IIS and S/PDIF audio outputs•Support Standard Audio and HD (HBR) Audio•Support audio soft mute•Support SPDIF Channel Status extraction•On-chip YCC422 to YCC444 conversion and YCC444 to YCC422 conversion•On-chip YCC to RGB and RGB to YCC conversion in ITU-R BT.601 and 709 color space•Support 24-bit RGB or 24-bit YCbCr 4:4:4 or 16-bit YCbCr 4:2:2 digital video output•Support Bit Sequence Reverse and Port Swapping in video output ports to ease PCB layout•Support DDR in digital video outputs•Register-programmable via slave IIC interface•Flexible interrupt registers with interrupt pin•Link On and Valid DE Detection•Controllable tri-state for output ports•Low Power operation•Low stand-by current (< 1mA) at power down mode•EP9351 is 80 pin LQFP and the EP9351B is 81-ball VFBGA package3Explore Microelectronics Confidential Proprietary4Explore Microelectronics Confidential ProprietaryUser Guide — EP9351/EP9351B_UG V0.6Explore Microelectronics Confidential Proprietary 5Section 2 Overview2.1 Block DiagramFigure 2-1 Block DiagramHDMI Registers andControl LogicHDCP EngineAudio DecodeIIS Audio OutSPDIF Audio OutHDCP KeysVideo DecodeRGB/YUV Digital OutIIS_SCK IIS_WS IIS_SD*SPDIFD0[7:0]D1[7:0]D2[7:0]F, H, V, DE DCLKPLLAudio BufferExternal EE_SCL InterfaceEEPROM MCLKHDMI Equalizer HDMI PortReceiverEDID RAMDDC PortSCLSDAEE_SDAINTbUser Guide — EP9351/EP9351B_UG V0.6Explore Microelectronics Confidential Proprietary 62.2 Pin Diagram2.2.1 LQFP Pin DiagramFigure 2-2 LQFP-80 Pin DiagramRX_VDD_PLL 80HDCP_SCL 79HDCP_SDA 78HDMI_MUTE 77IIS_WS 76IIS_SCK 75IIS_SD074IIS_SD173VSS 72VDD 71IIS_SD270IIS_SD369SPDIF 68MCLK 67VSS 66VDDE 65R X 2-16A V D D 15R X 1+14R X 1-13V S S 12A V D D 3311R X 0+10R X 0-9V S S 8R X C +7R X C -6A V D D 5P V D D 4V S S 3E E _W P 2P L L _X F C 1DDC_SDA21DDC_SCL 22MCU_SDA 23MCU_SCL 24INTb-25RSTb 26XI-27XO 28VDDE-29VSS 30DCLK_OUT 31FIELD32VSHYC 33HSYNC 34DE35D2_OUT[7]36D 2_O U T [1]45D 2_O U T [0]46D 1_O U T [7]47D 1_O U T [6]48V S S 49D 1_O U T [5]50D 1_O U T [4]51D 1_O U T [3]52D 1_O U T [2]53D 1_O U T [1]54V D D E 55D 1_O U T [0]56D 0_O U T [7]57D 0_O U T [6]58D 0_O U T [5]59D 0_O U T [4]60R e s e r v e d20E X T _R E S 19V S S 18R X 2+17D2_OUT[6]37VDD38VSS 39D2_OUT[5]40D 2_O U T [4]41D 2_O U T [3]42V D D E 43D 2_O U T [2]44D0_OUT[0]64D0_OUT[1]63D0_OUT[2]62D0_OUT[3]61User Guide — EP9351/EP9351B_UG V0.6Explore Microelectronics Confidential Proprietary 72.2.2 BGA Pin DiagramFigure 2-3 BGA-81 Pin Diagram654321ABCDEFG HJTop View789RX2+RX2-RX1+RX1-RX0+RX0-RXC+RXC-PVDDVSS AVDD EE_WP AVDD33VSS VSS AVDD EXT_RESVSS DDC_SDADDC_SCL MCU_SDA MCU_SCL A_MUTE EE_SCL EE_SDA VDD_PLL WS SCK VDD XO VSS SD1SD0XI RSTb INTbVDDE DCLKreserved VSS FIELD PLL_XFC VSYNCHSYNC VSS SD2SD3SPDIF D1[4]D1[7]VDDE D0[5]VSS MCLK D1[5]D1[1]D0[6]D0[0]VDDE D0[1]D0[3]D0[2]D0[4]D1[2]D2[4]D1[3]D0[7]D1[0]VSS D1[6]D2[0]D2[1]D2[2]VDDE D2[3]D2[7]D2[5]VSS VDDD2[6]DEUser Guide — EP9351/EP9351B_UG V0.6Explore Microelectronics Confidential Proprietary 82.3 Pin DescriptionUnless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.Table 2-1 HDMI ReceiverNameIn/OutDescriptionRXC-IN HDMI Receiver Differential Clock Input Pair RXC+IN HDMI Receiver Differential Clock Input Pair RX0-IN HDMI Receiver Differential Data Input Pair0 RX0+IN HDMI Receiver Differential Data Input Pair0 RX1-IN HDMI Receiver Differential Data Input Pair1 RX1+IN HDMI Receiver Differential Data Input Pair1 RX2-IN HDMI Receiver Differential Data Input Pair2 RX2+IN HDMI Receiver Differential Data Input Pair2 EXT_RESINHDMI External Termination ResistorTable 2-2 DDC/IIC/MCU/EEPROMNameIn/OutDescriptionRSTb IN Active Low Reset.INTb OUT Interrupt signal (Active Low). Asserted when Information packet is received. This pin is open drain output with internal weak pull-up.MCU_SCL IN SCL signal for HDMI slave IIC port MCU_SDA IO SDA signal for HDMI slave IIC port DDC_SCL IN IIC SCL signal for DDC Port DDC_SDA IO IIC SDA signal for DDC Port EE_SCL OUT SCL signal for EE IIC port EE_SDAIOSDA signal for EE IIC portTable 2-3 Video/Audio Output PinsNameIn/OutDescriptionA_MUTE OUT Audio Mute Output DCLK OUT Data Clock Output. VSYNC OUT Vertical Sync Output. HSYNC OUT Horizontal Sync Output.DE OUT Video Data Enable Output. When asserted, the data presents on D0, D1 and D2 pins is a valid video data.FIELD OUT Field Output to indicate 1st field or 2nd field in an interlace video output. The polarity is programmable by register.D0[7:0]OUT This 8-pin bus outputs port 0 digital Video Data. D1[7:0]OUT This 8-pin bus outputs port 1 digital Video Data. D2[7:0]OUTThis 8-pin bus outputs port 2 digital Video Data.User Guide — EP9351/EP9351B_UG V0.6Explore Microelectronics Confidential Proprietary 9Table 2-4 Audio PinsNameIn/OutDescriptionMCLK OUT System Clock output for audio DAC (128/256/384/512 * F Sampling_Clock )IIS_SCK OUT IIS SCK output for all IIS audio ports. Sampling clock output for DSD.IIS_WS/DSD0R OUT IIS WS output for all IIS audio ports. DSD audio output port 0 (Right Channel).IIS_SD0/DSD0L OUT IIS SD output for audio port 0. DSD audio output port 0 (Left Channel). IIS_SD1/DSD1R OUT IIS SD output for audio port 1. DSD audio output port 1 (Right Channel).IIS_SD2/DSD1L OUT IIS SD output for audio port 2. DSD audio output port 1 (Left Channel). IIS_SD3/DSD2R OUT IIS SD output for audio port 3. DSD audio output port 2 (Right Channel).SPDIF/DSD2LOUTSPDIF output. DSD audio output port 2 (Left Channel).Table 2-5 Misc. PinsNameIn/OutDescriptionXI Analog External Crystal Input, 18.432 Mhz XO Analog External Crystal Output, 18.432 MhzPLL_XFC Analog For connecting a R/C components to ground for on-chip PLL RESERVEDINMust be tied LOW for normal operation.Table 2-6 Power PinsNameIn/OutDescriptionVDD_PLL PWR PLL VDD (3.3V)AVDD33PWR HDMI Termination Power (3.3V)AVDD PWR HDMI Receiver Analog Power (1.8V)PVDD PWR HDMI Receiver PLL Analog Power (1.8V)VDDE PWR I/O VDD (1.8V)VDD PWR Internal Logic VDD (1.8V)VSSGNDGroundUser Guide — EP9351/EP9351B_UG V0.6Explore Microelectronics Confidential Proprietary 102.4 Video Data Output MappingTable 2-7 Data Output Mapping 1,2,3NOTES :1. In YCbCr444 output, if UVSW bit is set, Cb and Cr pin assignments are swapped.2. In YCbCr422 output, Cb data is output in first clock and Cr data is output in next clock. If UVSW bit is set, Cb/Cr data sequence is reversed.3. Bit significance in a pixel component: [7:0] = [MSB:LSB]4. Bit sequence in a port will be reversed if BIT_REV bit is set.5. D0 port and D2 port will be swapped if D02SW bit is set.Pin NameRGBYCbCr444YCbCr422D2[7]R[7]Cr[7]Cb/Cr[7]D2[6]R[6]Cr[6]Cb/Cr[6]D2[5]R[5]Cr[5]Cb/Cr[5]D2[4]R[4]Cr[4]Cb/Cr[4]D2[3]R[3]Cr[3]Cb/Cr[3]D2[2]R[2]Cr[2]Cb/Cr[2]D2[1]R[1]Cr[1]Cb/Cr[1]D2[0]R[0]Cr[0]Cb/Cr[0]D1[7]G[7]Y[7]Y[7]D1[6]G[6]Y[6]Y[6]D1[5]G[5]Y[5]Y[5]D1[4]G[4]Y[4]Y[4]D1[3]G[3]Y[3]Y[3]D1[2]G[2]Y[2]Y[2]D1[1]G[1]Y[1]Y[1]D1[0]G[0]Y[0]Y[0]D0[7]B[7]Cb[7]-D0[6]B[6]Cb[6]-D0[5]B[5]Cb[5]-D0[4]B[4]Cb[4]-D0[3]B[3]Cb[3]-D0[2]B[2]Cb[2]-D0[1]B[1]Cb[1]-D0[0]B[0]Cb[0]-Explore Microelectronics Confidential Proprietary 112.5 Electrical CharacteristicsAbsolute Maximum ConditionsNormal Operating ConditionsDC Digital I/O Specifications (under normal operating conditions unless otherwise specified )Symbol Parameter Min TypMax Units V cc 1NOTES :1. Permanent device damage may occur if absolute maximum conditions are exceeded.3.3V Supply Voltage -0.34.0V V DD 1 1.8V Supply Voltage -0.3 2.5V V I Input Voltage -0.3V cc + 0.3V V O 22. Functional operation should be restricted to the conditions described under Normal Operating Conditions.Output Voltage-0.3V cc + 0.3VT A Ambient Temperature (with power applied)125°C T STGStorage Temperature-55125°CSymbol Parameter Min Typ Max Units Vcc 3.3V Supply Voltage 3.0 3.3 3.6V V DD 1.8V Supply Voltage 1.621.81.98V V CCN Supply Voltage Noise100mV p-pT AAmbient Temperature (with power applied)2570°CSymbol Parameter ConditionsMin TypMaxUnits V IH High-level Input Voltage 1.4V V IL Low-level Input Voltage 0.6V V OH High-level Output Voltage 1.5V V OL Low-level Output Voltage 0.4V I OLOutput Leakage CurrentHigh Impedance-1010uAExplore Microelectronics Confidential Proprietary 12DC Specifications (under normal operating conditions unless otherwise specified )Video AC Specifications (under normal operating conditions unless otherwise specified )Symbol ParameterConditionsMin TypMax Units V ID Differential Input Voltage, Single EndedAmplitude1501000mV I PDPower-Down CurrentPWR_UP = LOW No RXC+/- input 1mA I CCR1.8V Operating Current (C LOAD = 10pF, R EXT_RES = 680 Ω)DCLK=74.25MHz,Typical Pattern 1NOTES :1. The typical Pattern contains a gray scale area, checkerboard area and text 120150mA DCLK=148.5MHz,Typical Pattern 170200mA 3.3V Operating Current (C LOAD = 10pF, R EXT_RES = 680 Ω)DCLK=74.25MHz,Typical Pattern 22. The typical Pattern contains a gray scale area, checkerboard area and text5070mA DCLK=148.5MHz,Typical Pattern 5070mASymbol ParameterConditionsMinTypMax Units T DPS Intra-Pair (+ to -) Differential Input Skew 0.4T bit T CCS Channel to Channel Differential Input Skew 1.0T pixel T IJIT Differential Input Clock Jitter Tolerance 0.3T bit D LH L-to-H Transition Time: CLK, Data and Controls C L = 10pF 3ns D HL H-to-L Transition Time: CLK, Data and Controls C L = 10pF 3ns T SETUP1D0, D1, D2, DE, VSYNC, HSYNC Setup Time to DCLKactive edge at 165MHz C L = 10pF 2.5ns T HOLD1D0, D1, D2, DE, VSYNC, HSYNC Hold Time fromDCLK active edge C L = 10pF 1.0ns T SETUP2D0, D1, D2, DE, VSYNC, HSYNC Setup Time to DCLKactive edge at 165MHz C L = 10pF 1.2ns T HOLD2D0, D1, D2, DE, VSYNC, HSYNC Hold Time fromDCLK active edgeC L = 10pF2.8ns T CIP DCLK Cycle Time 6.0640ns F CIP DCLK Frequency 25165MHz T CIH DCLK High Time C L = 10pF 2.0ns T CILDCLK Low TimeC L = 10pF 1.7nsI2S Audio AC Specifications (under normal operating conditions unless otherwise specified)Symbol Parameter Conditions Min Typ Max Units T sck SCK Clock Period C L = 10pF1T sck T sck_d SCK Clock Duty Cycle C L = 10pF40%60%T sck T sck_h SCK Clock High Time C L = 10pF40%60%T sck T sck_l SCK Clock LOW Time C L = 10pF40%60%T sck T iis_s SCK to SD and WS (Setup Time)C L = 10pF40%-T sck T iis_h SCK to SD and WS (Hold Time)C L = 10pF40%-T sckSPDIF Audio AC Specifications (under normal operating conditions unless otherwise specified)Symbol Parameter Conditions Min Typ Max Units T spdif SPDIF Cycle Time C L = 10pF1UI T spdif_d SPDIF Duty Cycle C L = 10pF90%110%UIExplore Microelectronics Confidential Proprietary13Explore Microelectronics Confidential Proprietary 142.6 Timing DiagramsFigure 2-4 Digital Output Transition Timing DefinitionFigure 2-5 Clock Cycle and High/Low Timing DefinitionFigure 2-6 Channel to Channel Skew Timing DefinitionD LH10pFD HLV OLV OLV OHV OHT CIPT CIHV IHV IHV ILV ILT CILT CCSRX0+/-RX1+/-RX2+/-V DIFF = 0V DIFF = 0Explore Microelectronics Confidential Proprietary 15Figure 2-7 Output to DCLK Timing DefinitionFigure 2-8 Output to DCLK Timing DefinitionDCLKV IH V ILT SETUP1T HOLD1Data, DE,HSYNC, VSYNCV IH V IH V ILV ILDCLK_POL = 1 DCLKV IHV ILT SETUP1T HOLD1Data, DE,HSYNC, VSYNCV IH V IH V ILV ILDCLK_POL = 0DCLK_DDR = 0DCLK_DDR = 0 DCLKV IHV ILT SETUP2T HOLD2Data, DE,HSYNC, VSYNCV IH V IH V ILV ILDCLK_POL = 1 DCLKDCLK_POL = 0T SETUP2T HOLD2Data, DE,HSYNC, VSYNCV IH V IH V ILV ILV IH V ILDCLK_DDR = 0DCLK_DDR = 0Explore Microelectronics Confidential Proprietary 16Figure 2-9 Output to DCLK Timing Definition2.7 Power Up SequenceFollowing figure shows the recommended power on sequence to EP9351/EP9351B:DCLKV IH V ILT SETUP1T HOLD1Data, DE,HSYNC, VSYNCV IH V IH V ILV ILDCLK_POL = 1DCLK_DDR = 1V IHV ILT HOLD1V IH V ILDCLKDCLK_POL = 0TSETUP2T HOLD2Data, DE,HSYNC, VSYNCV IH V IH V ILV ILV IH V ILDCLK_DDR = 1T SETUP2V IH V ILV IHV ILSection 3 Detail Functional Descriptions3.1 GeneralThe chip provides an IIC serial bus interface (SCL/SDA pins) for MCU to access the HDMI control/status registers. To access the HDMI control/status registers, the IIC address of 0x78should be given.Built-in control/status registers are organized by Register Sets. Each Register Set is comprised of one or more than one bytes of register. To address a register byte, a Word Address along with a Byte Address should be given. Word Address is used to address the register set and Byte Address is used to address the designated register byte within the addressed register set.3.2 IIC Interface for HDMI control/status registersOn-chip HDMI control/status registers can be accessed by main MCU and/or the on-chip HDMI MCU through an IIC bus interface. The IIC bus is a slave (IIC address = 0x78) which uses a Serial Data line (SDA) at SDA pin and a Serial Clock Line (SCL) at SCL pin for receiving and transmitting data. All devices connected to the IIC bus must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors, the value of these resistors is system dependent. When the serial interface is not active, the logic levels on SCL and SDA are pulled HIGH by external pull-up resistors. Data received or transmitted on the SDA line must be stable at the positive edge of SCL. If the SDA changes state while SCL is HIGH, the IIC interface interprets that action as a START or STOP sequence. Data on SDA must change only when SCL is LOW.The standard IIC traffic protocol is illustrated in the following Figure:Figure 3-1 IIC Bus Transmission ProtocolSCLSDAStart SignalAckBit12345678MSB LSB12345678MSB LSBStopSignalNoSCL SDA12345678MSB LSB125678MSB LSBRepeated349 9 AD7AD6AD5AD4AD3AD2AD1R/W XXX D7D6D5D4D3D2D1D0 Calling Address Read/Data ByteAD7AD6AD5AD4AD3AD2AD1R/W AD7AD6AD5AD4AD3AD2AD1R/WNew Calling Address99XXAckBitWriteStartSignalStart SignalAckBitCalling Address Read/WriteStopSignalNoAckBitRead/WriteExplore Microelectronics Confidential Proprietary173.2.1 Basic ProtocolThere are 5 components in serial bus protocol:•START Signal•Slave Address Byte•Word Address Byte for the Register Set•Data Bytes for Read/Write from/to the Register Set•STOP SignalWhen the serial interface is inactive (SCL and SDA are HIGH), communication are initiated by a START signal which is a HIGH-to-LOW transition on SDA while SCL is HIGH. The first eight bits of data transferred after a START signal comprising a seven bit slave address (the seven MSB bits) and a single R/W bit (the LSB bit). The R/W bit indicates the direction of data transfer, “1” means read from device and “0” means write to device. If the transmitted slave address matches the address of the device, the chip sends the acknowledge by asserting SDA Low on the ninth SCL pulse. Else, the chip does not acknowledge.On chip registers are organized by register set. Each register set is composed of single byte or multiple bytes. Each register set is assigned with a Word Address. Writing data to designated register set requires that the 8-bits Word Address of the register set is written after the slave address has been acknowledged. This Word Address selects the register set for the subsequent write operations. The write operation starts from byte 0 of the register set and continue write to the next byte of the register set if data presents. The acknowledge bit will be sent on the ninth SCL pulse after every 8-bits data received.Data are read from address register set in a similar manner. Reading requires two IIC transfer operations: The Word Address must be written with the R/W bit of the slave address byte being LOW to set up a sequential read operation.Reading (the R/W bit of the slave address byte HIGH) begins at the previously established Word Address. Data is read from byte 0 of the address register set and continue the next byte read ifacknowledge presents.To terminate a read/write sequence, a STOP signal must be sent. A STOP signal comprises aLOW-to-HIGH transition of SDA while SCL is HIGH.A repeated start signal occurs when the master device driving the serial interface generates a START signal without first generating a STOP signal to terminate the current read/write sequence. This can be used to change the mode of communication (read, write) between the slave and master without releasing the bus.3.2.2 Examples of the read/write sequenceWrite to a Register Set•START Signal18Explore Microelectronics Confidential Proprietary•Slave Address Byte (R/W bit = LOW)•Word Address Byte•Data Byte/Bytes to the register set starting from byte 0•STOP SignalRead from a Register Set•START Signal•Slave Address Byte (R/W bit = LOW)•Word Address Byte•STOP Signal (Optional)•START Signal•Slave Address Byte (R/W = HIGH)•Data Byte/Bytes from addressed register set starting from byte 0•STOP SignalExplore Microelectronics Confidential Proprietary19Explore Microelectronics Confidential Proprietary 203.3 HDMI Control/Status Registers3.3.1 Register Descriptions3.3.1.1 HDCP key Area (Word Address = $00 ~ $28)While the external EEPROM which store the encrypted HDCP Keys doesn’t exist, the HDCP keys can be programmed from MCU. Word Address from $00 to $28 are used for downloading the encrypted 40 56-bit HDCP keys and the 40-bit BKSV from an external MCU. These areas are write only. The 40 HDCP keys are stored from Word Address $00 to $27. The 40-bit BKSV is stored at Word Address $28. For each HDCP key, bit 7~0 is stored in Byte-0 and bit 55~48 is stored in Byte-6. For BKSV, bit 7~0 is stored in Byte-0 and bit 39~32 is stored in Byte-4. The control bit EE_DIS (0x48, bit 2) shall be set to 1 before the MCU starts to write the HDCP Keys to the Key Area through the IIC interface.3.3.1.2 Interrupt Flags (Word Address = $29)Table 3-1 Interrupt Flags RegisterThis register is Read Only. The lower 7 bits of this register (bit 6-0) are used as interrupt flags for InfoFrame and other packets. Whenever a designated packet is received, the corresponding interrupt flag bit will be set and the HDMI_INTb pin will be asserted, if the corresponding interrupt enable bit is set, to inform MCU to read this register and download the data if needed. After MCU read this register, all the flag bits will be cleared automatically. Special care is taken by the design to prevent accidentally loss of any flag bit.AVI_F — AVI InfoFrame Interrupt FlagThis bit is set when an AVI InfoFrame is received and is auto cleared when the register is read.ADO_F — Audio InfoFrame Interrupt FlagThis bit is set when an Audio InfoFrame is received and is auto cleared when the register is read.MS_F — MS InfoFrame Interrupt FlagThis bit is set when an MS InfoFrame is received and is auto cleared when the register is read.SEL1_F — 1st Selected Packet Interrupt FlagThis bit is set when the selected packet 1is received and is auto cleared when the register is read.SEL2_F — 2nd Selected Packet Interrupt FlagThis bit is set when the selected packet 2 is received and is auto cleared when the register is read.AVMS_F — AVMUTE Set Interrupt FlagWord Address =$2976543210RAVMC_FAVMS_FSEL2_FSEL1_FMS_FADO_FAVI_FPin Reset:00000000Explore Microelectronics Confidential Proprietary 21This bit is set when AVMUTE is set by General Control Packet and is auto cleared when the register is read.AVMC_F — AVMUTE Clear Interrupt FlagThis bit is set when AVMUTE is cleared by General Control Packet and is auto cleared when the register is read.3.3.1.3 Interrupt Enable Register (Word Address = $29)Table 3-2 Interrupt Enable RegisterThis register is Write Only. The lower 7 bits of this register (bit 0-6) are used as interrupt enable bits for Interrupt flags.INT_POL — HDMI_INTb pin polarity1 = HDMI_INTb pin is active high push pull.0 = HDMI_INTb pin is active low with weak pull-up.AVI_IEN — AVI_F interrupt enable1 = HDMI_INTb pin will be asserted if AVI_F is set.0 = HDMI_INTb pin is not affected by AVI_F.ADO_IEN — ADO_F interrupt enable1 = HDMI_INTb pin will be asserted if ADO_F is set.0 = HDMI_INTb pin is not affected by ADO_F.MS_IEN — MS_F interrupt enable1 = HDMI_INTb pin will be asserted if MS_F is set.0 = HDMI_INTb pin is not affected by MS_F.SEL1_IEN — SEL1_F interrupt enable1 = HDMI_INTb pin will be asserted if SEL1_F is set.0 = HDMI_INTb pin is not affected by SEL1_F.SEL2_IEN — SEL2_F interrupt enable1 = HDMI_INTb pin will be asserted if SEL2_F is set.0 = HDMI_INTb pin is not affected by SEL2_F.AVMS_IEN — AVMS_F interrupt enable1 = HDMI_INTb pin will be asserted if AVMS_F is set.0 = HDMI_INTb pin is not affected by AVMS_F.Word Address =$2976543210INT_POLAVMC_IENAVMS_IENSEL2_IENSEL1_IENMS_IENADO_IENAVI_IENWPin Reset:00000000AVMC_IEN — AVMC_F interrupt enable1 = HDMI_INTb pin will be asserted if AVMC_F is set.0 = HDMI_INTb pin is not affected by AVMC_F.3.3.1.4 AVI InfoFrame (Word Address = $2A)The 15-byte AVI InfoFrame content is stored in the register set with Word Address $2A with Byte-0 being the version number, Byte-1 being the packet check sum, Byte-2 corresponding to the 1st byte of the InfoFrame and Byte-14 corresponding to the last byte of the InfoFrame.Table 3-3 AVI InfoFrame RegistersWordAddress Byte #bit7bit6bit5bit4bit3bit2bit1bit00x2ARVersion Number1Checksum20Y1Y0A0B1B0S1S0 3C1C0M1M0R3R2R1R0 40EC2EC1EC000SC1SC0 50VIC6VIC5VIC4VIC3VIC2VIC1VIC0 60000PR3PR2PR1PR0 7Line Number of End of Top Bar (lower 8 bits)8Line Number of End of Top Bar (upper 8 bits)9Line Number of Start of Bottom Bar (lower 8 bits)10Line Number of Start of Bottom Bar (upper 8 bits)11Pixel Number of End of Left Bar (lower 8 bits)12Pixel Number of End of Left Bar (upper 8 bits)13Pixel Number of Start of Right Bar (lower 8 bits)14Pixel Number of Start of Right Bar (upper 8 bits)Explore Microelectronics Confidential Proprietary22Explore Microelectronics Confidential Proprietary 233.3.1.5 Audio InfoFrame (Word Address = $2B)The 7-byte Audio InfoFrame content is stored in the register set with Word Address $2B with Byte-0 being the version number, Byte-1 being the packet check sum, Byte-2 corresponding to the 1st byte of the InfoFrame and Byte-6 corresponding to the last byte of the InfoFrame.3.3.1.6 MS InfoFrame (Word Address = $2C)The 7-byte MS InfoFrame content is stored in the register set with Word Address $2C with Byte-0 being the version number, Byte-1 being the packet check sum, Byte-2 corresponding to the 1st byte of the InfoFrame and Byte-6 corresponding to the last byte of the InfoFrame.Table 3-4 ADO InfoFrame RegistersWord AddressByte #bit7bit6bit5bit4bit3bit2bit1bit00x2B0RVersion Number 1Checksum 2CT3CT2CT1CT00CC2CC1CC03000SF2SF1SF0SS1SS04000000005CA7CA6CA5CA4CA3CA2CA1CA06DM_INHLSV3LSV2LSV1LSV0Table 3-5 MS InfoFrame RegistersWord AddressByte #bit7bit6bit5bit4bit3bit2bit1bit00x2C0RVersion Number 1Checksum2MB#0 (MPEG Bit Rate: Hz Lower -> Upper)3MB#14MB#25MB#3 (Upper)6FR0MF1MF03.3.1.7 Selected Packet 1 (Word Address = $2D)Any other packet with specified packet type can be extracted and stored in this register set. The specified packet type needs to be written into Byte-0. If 0 value is written, no packet will be extracted. If a packet with matched packet type is received, the 3-byte Packet Header and the 28-byte Packet Content are stored in the register set in sequence starting from Byte-0 and end at Byte-30.3.3.1.8 Selected Packet 2 (Word Address = $2E)Any other packet with specified packet type can be extracted and stored in this register set. The specified packet type needs to be written into Byte-0. If 0 value is written, no packet will be extracted. If a packet with matched packet type is received, the 3-byte Packet Header and the 28-byte Packet Content are stored in the register set in sequence starting from Byte-0 and end at Byte-30.Table 3-6 Selected Packet Type 1/2 RegistersWordAddress Byte #bit7bit6bit5bit4bit3bit2bit1bit00x2D & 0x2E0R/W Packet Header 0 (HB0, Selected Packet Type) 1RPacket Header 1 (HB1)2Packet Header 2 (HB2)3Data Byte 0 (PB0 / SB0)4Data Byte 1 (PB1 / SB1)5Data Byte 2 (PB2 / SB2)6Data Byte 3 (PB3 / SB3)7Data Byte 4 (PB4 / SB4)8Data Byte 5 (PB5 / SB5)9Data Byte 6 (PB6 /SB6)10Data Byte 7 (PB7 / SB0)11Data Byte 8 (PB8 / SB1)12Data Byte 9 (PB9 / SB2)13Data Byte 10 (PB10 / SB3)14Data Byte 11 (PB11 / SB4)15Data Byte 12 (PB12 / SB5)16Data Byte 13 (PB13 / SB6)17Data Byte 14 (PB14 / SB0)18Data Byte 15 (PB15 / SB1)19Data Byte 16 (PB16 / SB2)20Data Byte 17 (PB17 / SB3)21Data Byte 18 (PB18 / SB4)22Data Byte 19 (PB19 / SB5)23Data Byte 20 (PB20 / SB6)24Data Byte 21 (PB21 / SB0)25Data Byte 22 (PB22 / SB1)26Data Byte 23 (PB23 / SB2)27Data Byte 24 (PB24 / SB3)28Data Byte 25 (PB25 / SB4)29Data Byte 26 (PB26 / SB5)30Data Byte 27 (PB27 / SB6)Explore Microelectronics Confidential Proprietary24。
CIP 案例
Y 值:預焊線所承受的拉力 因子A---time 水平 : 2S 3S 4S 因子B---temp 水平 : 360° 370 ° 380 ° 390°
(其中時間：1S、5S 溫度：330~350°、400~410 °未列入DOE驗証） 經分析﹕P<0.05,說明浸錫溫度 與時間對預焊線承受的拉力有 顯著影響! 用ANOVA分析,從time/temp交互作 用圖得知﹕預焊線拉力與time/temp 因素可能存在非線性關系! 此原始資料由RD 提供﹐附檔為﹕
W0640 100 244
W0641 0 0 0
W0641 100 0
targrt(ppm) 不良率(ppm)
周別 不良數(pcs) 生產數(pcs) 不良率(ppm)
W0633 2 3820 524
total 11 51385 214
備注: 以上target為ASUS制程要求.
執行力=速度+準度+精度
ww33 1246
ww34 1357
ww35 1024
ww36 1067
ww37 1218
ww38 1255
備注﹕Week 39 ~Week 42 未生產
執行力=速度+準度+精度
第5頁/共26頁
CID
現況分析/目標設定 TEAM構成/相關執掌
TEAM構成
姓名 高聲品 雷婷婷 郭愛華 宣萬立 盧桂明 白軍萍 牟星海 陳明 何賢金 單位 DQA CQA MQA 制工 MAG制工 測試 MQA VQA 裝配 擔當業務 Leader Member Member Member Member Member Member Member Member 相關執掌 領導CIP改善team, push改善進度 作為與客戶聯絡窗口(SJQE FOR ASUS) 對不良樣品進行分析,主持改善會議 主導擬定改善對策 主導擬定改善對策(mag部分) 負責與測試有關的工作項目 對不良樣品進行分析,主持改善會議 負責與來料段改善有關的工作項目 嚴格實施改善對策
ESP32-S3-WROOM-1、ESP32-S3-WROOM-1U 技术规格书说明书
ESP32-S3-WROOM-1ESP32-S3-WROOM-1U技术规格书2.4GHz Wi-Fi(802.11b/g/n)+Bluetooth®5(LE)模组内置ESP32-S3系列芯片，Xtensa®双核32位LX7处理器Flash最大可选16MB，PSRAM最大可选8MB36个GPIO，丰富的外设板载PCB天线或外部天线连接器ESP32-S3-WROOM-1ESP32-S3-WROOM-1U版本1.2乐鑫信息科技版权©20231模组概述1.1特性CPU 和片上存储器•内置ESP32-S3系列芯片，Xtensa ®双核32位LX7微处理器(支持单精度浮点运算单元)，支持高达240MHz 的时钟频率•384KB ROM •512KB SRAM •16KB RTC SRAM •最大8MB PSRAM Wi-Fi•802.11b/g/n•802.11n 模式下数据速率高达150Mbps •帧聚合(TX/RX A-MPDU,TX/RX A-MSDU)•0.4µs 保护间隔•工作信道中心频率范围：2412~2484MHz蓝牙•低功耗蓝牙(Bluetooth LE)：Bluetooth 5、Bluetooth mesh•速率支持125Kbps 、500Kbps 、1Mbps 、2Mbps •广播扩展(Advertising Extensions)•多广播(Multiple Advertisement Sets)•信道选择(Channel Selection Algorithm #2)•Wi-Fi 与蓝牙共存，共用同一个天线外设•GPIO 、SPI 、LCD 、Camera 接口、UART 、I2C 、I2S 、红外遥控、脉冲计数器、LED PWM 、USB 1.1OTG 、USB Serial/JTAG 控制器、MCPWM 、SDIO 主机接口、GDMA 、TWAI ®控制器（兼容ISO 11898-1）、ADC 、触摸传感器、温度传感器、定时器和看门狗模组集成元件•40MHz 集成晶振•最大16MB Quad SPI flash 天线选型•板载PCB 天线(ESP32-S3-WROOM-1)•通过连接器连接外部天线(ESP32-S3-WROOM-1U)工作条件•工作电压/供电电压：3.0~3.6V •工作环境温度：–65°C 版模组：–40~65°C –85°C 版模组：–40~85°C –105°C 版模组：–40~105°C认证•RF 认证：见证书•环保认证：RoHS/REACH 测试•HTOL/HTSL/uHAST/TCT/ESD1.2描述ESP32-S3-WROOM-1和ESP32-S3-WROOM-1U是两款通用型Wi-Fi+低功耗蓝牙MCU模组，搭载ESP32-S3系列芯片。
紫外线波长及分类
紫外线波长及分类
紫外线是阳光中波长为10～400纳米（nm）的光线，可以分为UVA（紫外线A，波长320～400纳米，长波）、UVB（波长280～320纳米，中波）、UVC（波长100～280纳米，短波）3种。
短波紫外线简称UVC，是波长200～280nm(纳米)的紫外光线。
短波紫外线在经过地球表面同温层时被臭氧层吸收，不能到达地球表面。
短波紫外线对人体可产生重要作用，因此，对短波紫外线应引起足够的重视。
中波紫外线简称UVB，是波长280～320nm的紫外线。
中波紫外线对人体皮肤有一定的生理作用。
此类紫外线的极大部分被皮肤表皮所吸收，不能渗入皮肤内部。
但由于其阶能较高，对皮肤可产生强烈的光损伤，被照射部位真皮血管扩张，皮肤可出现红肿、水泡等症状。
长久照射皮肤会出现红斑、炎症、皮肤老化，严重者可引起皮肤癌。
由此中波紫外线又被称作紫外线的晒伤(红)段，是应重点预防的紫外线波段。
长波紫外线UVA。
是波长315~400nm的紫外线。
长波紫外线对衣物和人体皮肤的穿透性远比中波紫外线要强，可达到真皮深处，并可对表皮部位的黑色素起作用，从而引起皮肤黑色素沉着，使皮肤变黑，起到了防御紫外线，保护皮肤的作用。
因而长波紫外线也被称做“晒黑段”。
长波紫外线虽不会引起皮肤急性炎症，但对皮肤的作用缓慢，可长期积累，是导致皮肤老化和严重损害的原因之一。
基恩士接近终极指南
节省 空间
有超小型的头部，仅为
10x10mm；FU-52TZ型，
180°
检测距离长达500mm。
侧视图
只需要给螺帽头预 留空间即可。
内部结构
专利申请中
光纤的顶端是由一 种不易破损的光 纤做成，因此可 以象潜望镜一样 弯曲成90°角， 从而不浪费空间。
规格
类型
尺寸(mm) 2 x 1.5 x 20
透过光束
FU-35FZ
35,30,25
ø0.05
F-4HA
F-35FA (Z)
15 ± 2
ø0.5
ø0.03
1. 当使用SUPER TURBO模式时/TURBO模式时/FINE模式时
9
节省空间型
有31款节省空间型光纤元件，有超细型的，也有超小型的，您可以根据 需要任意选择
FU-18M FU-58
FU-51TZ FU-32
用于目标精确识别的三色光源 SUPER RGB的三色光源分别来自三个独立的 LED，经过接收器转换成16-bit数据以便于色彩 识别，这样即便目标物体有振动也不影响识别 的精确度。
问题解答2
利用一个配备有一个聚集透镜 的反射传感器，实现光束变窄。
问题解答3
采用CZ系列光纤
见第13页
规格
类型 小光点（内置透镜）
型号 FU-20
透用的光纤元件 检测距离 (mm)1.
—
5
光点直径 (mm)
最小的可检测物体 (mm)
ø0.1
ø0.01
射束窄，检测距离长
FU-40
—
30至320
ø14至ø42
10至30mm
长检测距离
30至320mm
伦茨 8200 8210系列变频器 说明书
!!!!!!!!!!!!!!!! !! !!!!!!!!!!!! !! != !> !? =@ =@ =, =) =) =$ =( =( =( =( =* =*
:;< !<.:7" 0 1 !!!!!!!!!!!!! =>? @ !!!!!!!!!!!!!!!!! +,ABC D !!!!!!!!!!!!!!! E%(F G !!!!!!!!!!!!!!!! HIJF G !!!!!!!!!!!!!!!! M"NO 3 PQRM " !!!!!!!!!!! ST%9U * !!!!!!!!!!!!!!! %&;VF W !!!!!!!!!!!!!!!
( ( ! * * %# %# %%
%’% %’" %’) "’
&’( ) !!!!!!!!!!!!!!!!!!!!!! *+,-.#( ) !!!!!!!!!!!!!!!!!! /012 3 !!!!!!!!!!!!!!!!!!!!!
%’)’% "’% "’" )’
456 ’ !!!!!!!!!!!!!!!!!!!
u%vwxyz{| n !!!!!!!!!!!!!! }~y !!!!!!!!!!!!!!!! %& 3 !!!!!!!!!!!!!!!!!!!!
%&’ ( !!!!!!!!!!!!!!!!!!!!!!!!
BC9 !!!!!!!!!!!!!!!!!! >$ BC9 8 @+( 4 BC9 84 !!!!!!!!!!!!! >$ !!!!!!!!!!!!!! >$ >!!!! >$
%&‘a !!!!!!!!!!!!!!!!! %&%9 T !!!!!!!!!!!!!!!!!
Bridgelux SMD 3030 1W 9V 高功率 led 产品数据册 ds657 rev.
Product Data Sheet DS657The Bridgelux SMD 3030 high power LED is hot-color targeted, which ensures that the LEDs fall within their specified color bin at the typical application conditions of 85°C. With its broad lumen coverage and wide range of CCT options, the SMD 3030 provides unparalleled design-in flexibility for indoor and outdoor lighting applications. The SMD 3030 is ideal as a drop-in replacement for emitters with an industry standard 3.0mm x 3.0mm footprint.Features• Industry-standard 3030 footprint• 5 bin color control• Hot-color targeting ensures that color is within the ANSI bin at the typical application conditions of 85°C • Enables 3- and 6-step MacAdam ellipse custom binning kits• RoHS compliant and lead free• Multiple CCT configurations for a wide range of lighting applicationsBenefits• Lower operating and manufacturing cost • Ease of design and rapid go-to-market • Uniform, consistent white light• Reliable and constant white point• Compliant with environmental standards • Design flexibilityContentsProduct Feature Map2 Product Nomenclature2 Product Test Conditions2 Product Selection Guide3 Electrical Characteristics4 Absolute Maximum Ratings5 Product Bin Definitions6 Performance Curves9 Typical Radiation Pattern12 Typical Color Spectrum 13 Mechanical Dimensions14 Reliability 15 Reflow Characteristics16 Packaging17 Design Resources19 Precautions19 Disclaimers19 About Bridgelux20Product Feature MapCathode MarkYellow phosphor Light Emitting Surface (LES)Product NomenclatureThe part number designation for Bridgelux SMD 3030 is explained as follows:Product Test ConditionsBridgelux SMD 3030 LEDs are tested and binned with a 10ms pulse of 100mA at T j (junction temperature)=T sp (solder point temperature) =25°C. Forward voltage and luminous flux are binned at a T j =T sp =25°C.while color is hot targeted at a T sp of 85°C.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Product FamilyColor Bin OptionsFlux Bins Minimum CRIC= 70 CRIForward Voltage Bins Nominal CCT27 = 2,700K 30 = 3,000K 35 = 3,500K 40 = 4,000K 50 = 5,000K 57 = 5,700K 65 = 6,500KBXEM – 30 C – 1 3 H – 9 C – 00 – 0 – 0Product Version High PowerDie count in parallelTypical Forward VoltageDie count in series Bridgelux SMD LED products come in industry standard package sizes and follow ANSI binning standards. These LEDs are optimized for cost and performance, helping to ensure highly competitive system lumen per dollar performance while addressing the stringent efficacy and reliability standards required for modern lighting applications.Product Selection GuideThe following product configurations are available:Table 1: Selection Guide, Pulsed Measurement Data at 100mA (T j =T sp =25°C)Notes for Tables 1 & 2:1. The last 6 characters (including hyphens ‘-’) refer to flux bins, forward voltage bins, and color bin options, respectively. “00-0-0” denotes the full distribution of flux, forward voltage, and 6 SDCM color.Example: BXEM-30C-13H-9C-00-0-0 refers to the full distribution of flux, forward voltage, and color within a 3000K 6-step ANSI standard chromaticity region with a minimum of 70CRI, 1x3 die configuration, 8.9V typical forward voltage.2. Product CCT is the nominal CCT at Tsp = 85°C as defined by ANSI C78.377-2011.3. Listed CRIs are minimum values at Tsp = 85°C and include test tolerance.4. Products tested under pulsed condition (10ms pulse width) at nominal drive current where Tj=Tsp=25°C.5. Bridgelux maintains a ±7.5% tolerance on luminous flux measurements, ±0.1V tolerance on forward voltage measurements, and ±2 tolerance on CRI measurements for the SMD 3030.6. Refer to Table 5 and Table 6 for Bridgelux SMD 3030 Luminous Flux Binning and Forward Voltage Binning information.7. Typical pulsed test performance values are provided as reference only and are not a guarantee of performance.8. Typical performance is estimated based on operation under pulsed current with LED emitter mounted onto a heat sink with thermal interfacematerial and the solder point temperature maintained at 85°C. Based on Bridgelux test setup, values may vary depending on the thermal design of the luminaire and/or the exposed environment to which the product is subjected.spElectrical CharacteristicsTable 3: Electrical CharacteristicsNotes for Table 3:1. The last 6 characters (including hyphens ‘-’) refer to flux bins, forward voltage bins, and color bin options, respectively. “00-0-0” denotes the full distribution of flux, forward voltage, and 6 SDCM color.Example: BXEM-30C-13H-9C-00-0-0 refers to the full distribution of flux, forward voltage, and color within a 3000K 6-step ANSI standardchromaticity region with a minimum of 70CRI, 1x3 die configuration, high power, 8..9V typical forward voltage.2. Bridgelux maintains a tolerance of ± 0.1V on forward voltage measurements. Voltage minimum and maximum values at the nominal drive current are guaranteed by 100% test.3. Products tested under pulsed condition (10ms pulse width) at nominal drive current where Tsp = 25°C.4. Thermal resistance value was calculated using total electrical input power; optical power was not subtracted from input power.Absolute Maximum RatingsTable 4: Maximum RatingsNotes for Table 4:1. Bridgelux recommends a maximum duty cycle of 10% and pulse width of 10 ms when operating LED SMD at maximum peak pulsed current specified.Maximum peak pulsed current indicate values where LED SMD can be driven without catastrophic failures.2. Light emitting diodes are not designed to be driven in reverse voltage and will not produce light under this condition. no rating is providedProduct Bin DefinitionsTable 5:Luminous flux Bin Definitions at 100mA, T sp =25°CTable 5 lists the standard photometric luminous flux bins for Bridgelux SMD 3030 LEDs. Although several bins are listed, product availability in a particular bin varies by production run and by product performance. Not all bins are available in all CCTs.Table 6: Forward Voltage Bin Definition at 100mA, T sp=25°CNote for Table 6:1. Bridgelux maintains a tolerance of ± 0.1V on forward voltage measurements.Note for Table 5:1.Bridgelux maintains a tolerance of ± 7.5% on luminous flux measurements.Product Bin DefinitionsTable 7: 3- and 6-step MacAdam Ellipse Color Bin DefinitionsNotes for Table 7:1. Color binning at T=85°C unless otherwise specifiedsp2. Bridgelux maintains a tolerance of ± 0.007 on x and y color coordinates in the CIE 1931 color space.Product Bin DefinitionsFigure 1: C.I.E. 1931 Chromaticity Diagram (5 Color Bin Structure, Hot-color Targeted at T=85°C)spNote for Figure 3:1. Pulse width modulation (PWM) is recommended for dimming effects.Figure 2: Drive Current vs. Voltage (T sp =25°C)Figure 3: Typical Relative Luminous Flux vs. Drive Current 1 (T sp =25°C)Figure 4: Typical Relative Flux vs. Solder Point TemperatureFigure 5: Typical ccx Shift vs. Solder Point TemperatureNotes for Figures 4 & 5:1. Characteristics shown for warm white based on 3000K and 70 CRI.2. Characteristics shown for neutral white based on 4000K and 70 CRI.3. For other color SKUs, the shift in color will vary. Please contact your Bridgelux Sales Representative for more information.Figure 6: Typical ccy Shift vs. Solder Point TemperatureD r a f1. Characteristics shown for warm white based on 3000K and 70 CRI.2. Characteristics shown for neutral white based on 4000K and 70 CRI.3. For other color SKUs, the shift in color will vary. Please contact your Bridgelux Sales Representative for more information.Typical Radiation PatternFigure 7: Typical Spatial Radiation Pattern at 100mA, T sp =25°CFigure 8: Typical Polar Radiation Pattern at 100mA, T sp =25°CNotes for Figure 7:1. Typical viewing angle is 120⁰.2. The viewing angle is defined as the off axis angle from the centerline where luminous intensity (Iv) is ½ of the peak value.Typical Color Spectrum Figure 9: Typical Color SpectrumNotes for Figure 9:1. Color spectra measured at nominal current for Tsp = 25°C2. Color spectra shown for 70 CRI products.Mechanical Dimensions Figure 10: Drawing for SMD 3030Notes for Figure 10:1. Drawings are not to scale.2. Drawing dimensions are in millimeters.3. Unless otherwise specified, tolerances are ± 0.10mm. Recommended PCB Soldering Pad PatternReliabilityTable 8: Reliability Test Items and ConditionsNotes for Table 8:1. Measurements are performed after allowing the LEDs to return to room temperature2. T sld : reflow soldering temperature; T a: ambient temperaturePassing CriteriaFigure 11 : Reflow ProfileReflow CharacteristicsFigure 12 : Pick and PlaceNote for Figure 12:1. When using a pick and place machine, choose a nozzle that has a larger diameter than the LED’s emitting surface. Using a Pick-and-Place nozzle witha smaller diameter than the size of the LEDs emitting surface will cause damage and may also cause the LED to not illuminate.Is greater than LEDsemitting surfacePackagingFigure 13: Emitter Reel DrawingsNote for Figure 13:1. Drawings are not to scale. Drawing dimensions are in millimeters. Figure 14: Emitter Tape DrawingsNote for Figure 14:1. Drawings are not to scale. Drawing dimensions are in millimeters.PackagingFigure 15: Emitter Reel Packaging DrawingsNote for Figure 15:1.Drawings are not to scale.5 k10 kDesign ResourcesDisclaimersPrecautionsPlease contact your Bridgelux sales representative for assistance.MINOR PRODUCT CHANGE POLICYThe rigorous qualification testing on products offered by Bridgelux provides performance assurance. Slight cosmetic changes that do not affect form, fit, or function may occur as Bridgelux continues product optimization.CAUTION: CHEMICAL EXPOSURE HAZARDExposure to some chemicals commonly used in luminaire manufacturing and assembly can cause damage to the LED emitter. Please consult Bridgelux Application Note AN51 for additional information.CAUTION: EYE SAFETYEye safety classification for the use of Bridgelux SMD LED emitter is in accordance with IECspecification EN62471: Photobiological Safety of Lamps and Lamp Systems. SMD LED emitters are classified as Risk Group 1 when operated at or belowthe maximum drive current. Please use appropriate precautions. It is important that employees working with LEDs are trained to use them safely.CAUTION: RISK OF BURNDo not touch the SMD LED emitter during operation. Allow the emitter to cool for a sufficient period of time before handling. The SMD LED emitter may reachelevated temperatures such that could burn skin when touched.CAUTIONCONTACT WITH LIGHT EMITTING SURFACE (LES) Avoid any contact with the LES. Do not touch the LES of the emitter or apply stress to the LES (yellow phosphor resin area). Contact may cause damage to the emitterOptics and reflectors must not be mounted in contact with the LES (yellow phosphor resin area).STANDARD TEST CONDITIONSUnless otherwise stated, LED emitter testing is performed at the nominal drive current.About Bridgelux: Bridging Light and Life™© 2021 Bridgelux, Inc. All rights reserved 2021. Product specifications are subject to change without notice. Bridgelux and the Bridgelux stylized logo design are registered trademarks of Bridgelux, Inc. All other trademarks are the property of their respective owners.46410 Fremont Boulevard Fremont, CA 94538 USA Tel (925) 583-8400Fax (925) At Bridgelux, we help companies, industries and people experience the power and possibility of light. Since 2002, we’ve designed LED solutions that are high performing, energy efficient, cost effective and easy to integrate. Our focus is on light’s impact on human behavior, delivering products that create better environments, experiences and returns—both experiential and financial. And our patented technology drives new platforms for commercial and industrial luminaires.For more information about the company, please visit /Bridgelux /Bridgelux/user/Bridgelux WeChat ID: BridgeluxInChina https:///company/bridgelux-inc-_2。
《周髀算经》与阳城
;Z V:# _‘G7$ :bv&c+C4jR ;1Y=1k@V05&.tX‘ Q F R "+&"*’ G F R "+$""% :Rw w Q& V } X= 4!z5S9! m % " &1V5@(n&4.tRJ_$ #"" &67G J_ $ "(% &67fm % ,@z5S9Z<&( YZ { [ ) , l g t " @ no |b 6 E m % H& f g t " G ww#$t"@no|b; % H67- JHB3b&F R "+&"*’ @z5S9OpP}.89( YZ{[) |8@( n & 4 z J_ $ "(% &67& & 1 k $ 0& g \kG m @ #* bOH1k#]"%@ab ! ’(4 ’+ # c$dW% J^1\&K|8z5@]Fab ’#4 b" E X0- & " U " 9 R q\ 0 Q @ & 4 TU’ J_ $ %(" g $ %$ && & P - p g1 k&cLjZE-#~mab ’#4 #* b+gx- %#V}yt@(n]6zJA $ &&1 ]FabR ’#4 $+ b((‘Q F R "+&"*’ :RwwQ&0Q@(n & 4;J_ $ #"" &67&" 9 R q\ @&4TURJ_$ #&& g$ ((# &&&67,0=P-$05P"h78 ( YZ{[ ) ,a.agcdI;d&&6.;’$lg;Aa$ 7.; >$fg;)p&XQo6<@(n&4RJ_$ #&$ g$ (#" & / (0 - E{A 2 +’ T\} x / &0 Gf}(Qm / $ 0 v!vyyz{&XQo6<@(n&4RJ_$ ##* g$ ’(’ &p\E{At"XQ@(n&4zJ6@3V&E{m<m}R( YZ { [ ) t " @ ( n & 4RJ_ $ #"" &67& I A@w wQR F R "+&"*’ - \V&(n]6@]FabR ’#4 %+ b67J67,0gP-$0@m-#]& } ’ - # ] # 5 % B R 5 !&# 5 % & nJA F ] (Js~3]&]FabR ’#4 %& b- ( 652/Jb S & ) 7 +& J_ $ $"# & # ’ /J #Lm5% &\H-R"- 3^)L( YZ{ [ ) ’ # f 5$ @ : R Y J D t L % & V 5 @ : zH-L&=’-R1# #] , % - V Y& 5 -u Z @ # ]% * ! nJ1 l O ) 3]& ] F ab ’#4 "* b" !V5z( YZ{[) @(n]6-
手持式 LCR 仪表 (U1731C、U1732C 和 U1733C)
8
Keysight U1731C/U1732C/U1733C 用户指南
目录
安全标志
. . . . . . . . . . . . . . . . . . . . . . . . .3
安全注意事项
. . . . . . . . . . . . . . . . . . . . . . .4
环境条件
. . . . . . . . . . . . . . . . . . . . . . . . .6
Keysight U1731C/U1732C/U1733C 用户指南
5
环境条件
此仪器设计为仅允许在室内以及低凝结区域使用。下表显示了此仪器的一般环境 要求。
环境条件 操作温度
操作湿度
存放温度 存放湿度 海拔高度 污染度
要求 在 –10 °C 至 55 °C 时为完全精度 在 RH ( 相对湿度 ) 不超过 80% 的范围内可达到 完全精度 –20 °C 至 70 °C 0% 至 80% RH （无凝结） 最高 2000 米 污染等级 II
符合性声明
可以从 Web 上下载本产品以及其他 Keysight 产品的符合性声明。请访问 /go/conformity。 然后，可以按产品编号进行搜索，查找 最新的符合性声明。
美国政府权利
本软件属于联邦政府采购法规 （“FAR”）2.101 定义的 “ 商用计算机 软件 ”。按照 FAR 12.212 和 27.405-3 以及国防部 FAR 补充条款（“DFARS”） 227.7202，美国政府根据向公众提供商 用计算机软件的一般条款获得本软件。 同样， Keysight 根据其标准商业许可证 向美国政府客户提供本软件，该许可证 包含在其最终用户许可协议 (EULA) 中， 可以在以下位置找到该许可协议的副本： /find/sweula。 EULA中所述的许可证阐述了美国政府在 使用、修改、分发或披露本软件方面的 专属权利。除了其他事项之外，EULA 及 其所述的许可证不要求或不允许 Keysight：(1) 提供通常不会向公众提供 的与商用计算机软件或商用计算机软件 文档相关的技术信息；或者 (2) 让与或 以其他方式提供的政府权利超过通常向 公众提供的有关使用、修改、复制、发 布、执行、显示或披露商用计算机软件 或 商 用 计 算 机 软 件 文 档 方 面 的 权 利。 EULA 中未涉及的其他政府要求不适用， 除非按照 FAR 和 DFARS 的规定明确要 求所有商用计算机软件提供商提供这些 条款、权利或许可证，并且 EULA 中的 其他地方有专门的书面说明。 Keysight 不 承 担 更 新、修 订 或 修 改 本 软 件 的 责 任。关于FAR 2.101所定义的技术数据， 根据FAR 12.211和27.404.2以及 DFARS 227.7102，美国政府获得的权利不超过 FAR 27.401 或 DFAR 227.7103-5 (c) 中 定义的有限权利，这适用于任何技术 数据。
HCPL-3150中文资料
N/C 1 ANODE 2 CATHODE 3
SHIELD
16 VCC 15 VO 14 VEE
CATHODE 3
N/C 4
SHIELD HCPL-3150
TRUTH TABLE
6 VO 5 VEE
ANODE 6 CATHODE 7
N/C 8
SHIELD HCPL-315J
11 VCC 10 VO 9 VEE
10 kV/µs
Yes
No
No
Widebody (400 mil) HCNW-3120
1
VIORM 1414 Vpeak
5000 Vrms/1min.
2A
Small Outline SO-16
HCPL-315J HCPL-316J HCPL-314J
2
1
2
0.5A
VIORM 891 Vpeak
3750 Vrms/1 min.
Standard DIP Package
9.40 (0.370) 9.90 (0.390)
87
6
A 3150 Z YYWW
PIN ONE 1
2
3
1.19 (0.047) MAX.
5 OPTION CODE* DATE CODE
6.10 (0.240) 6.60 (0.260)
7.36 (0.290) 7.88 (0.310)
2A
0.4A
15 kV/µs
10 kV/µs
Yes
No
Yes
No
Ordering Information
Specify Part Number followed by Option Number (if desired)