东南大学 数电实验报告 时序逻辑电路
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3
0
1
2
3
3
2
1
0
1
0
0
0
1
Fra Baidu bibliotek
0
0
0
0
0
0
00
1
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1
0
0
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1
0
04
1
0
0
0
0
0
1
0
1
0
0
08
1
0
0
0
0
0
0
1
1
1
0
0C
0
1
0
0
1
0
0
0
0
0
0
11
0
1
0
0
0
1
0
0
0
1
0
15
0
1
0
0
0
0
1
0
1
0
0
19
0
1
0
0
0
0
0
1
1
1
0
1d
0
0
1
0
1
0
0
0
0
0
1
02
0
0
1
0
0
1
0
0
0
1
1
06
0
0
1
0
0
0
1
D14
D2 D13
② B
D) 4 32768Hz
FPGA
32768Hz
CLK CLK
32.768Hz “
16 D
500 1000
50kHz
50MHz ②
1000
E)
5
FPGA
4×4
②
4×4
“ CLK CLK
2
2-4
1
1000 – 0100 – 0010 – 0001 ②
4D
COL COL COL COL ROW ROW ROW ROW NUM NUM NUM NUM
0
1
1
1
1
1
1
1
EW_SR_YELLOW
1
0
1
1
1
1
1
1
SN_L_RED
0
0
0
0
0
0
1
1
SN_L_GREEN
1
1
1
1
1
1
0
1
SN_L_YELLOW
1
1
1
1
1
1
1
0
SN_SR_RED
0
0
0
0
1
1
0
0
SN_SR_GREEN
1
1
1
1
0
1
1
1
SN_SR_YELLOW
1
1
1
1
1
0
1
1
“0” ②
“1” ②
B
①
——
D1 = D 3
D0 = 0
⑤
Q2
Q1
Q0 EW_L_RED EW_L_GREEN EW_L_YELLOW EW_SR_RED EW_SR_GREEN EW_SR_YELLOW SN_L_RED SN_L_GREEN SN_L_YELLOW SN_SR_RED SN_SR_GREEN SN_SR_YELLOW
01
11
10
Q2n
0
001
010
100
011
1
101
110
000
111
Q Q Q n+1 n+1 n+1
21
0
Q2n+1 = Q2n ⊕ Q1nQ0n Q1n+1 = Q1n ⊕ Q0n Q0n+1 = Q0n
L1 L8
8
1
2
Q2
Q1
Q0
L1
L2
L3
L4
L5
L6
L7
L8
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0A
0
0
1
0
0
0
0
1
1
1
1
0E
0
0
0
1
1
0
0
0
0
0
1
13
0
0
0
1
0
1
0
0
0
1
1
17
0
0
0
1
0
0
1
0
1
0
1
1b
0
0
0
1
0
0
0
1
1
1
1
1F
COL0
1 1 1 1 1 0
COL1
0 0 0 0 0 1
COL2
0 0 0 0 0 0
COL3
0 0 0 0 0 0
ROW0
1 0 0 0 0 1
ROW1
Q n+1 1
Q n+1 0
Y
0
0
0
0
0
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1
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1
1
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1
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1
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0
Q1nQ0n Q3nQ2n
00 01 11 10
00
01
11
0001 0101 1101 1001
0010 0000 0000 1010
0100 1000 0000 1100
Q Q Q Q n+1 n+1 n+1 n+1
3
21
0
10
0011 0111 1111 1011
∑ Y (Q2Q1Q0 ) = m(1,3,4)
0
X
0
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
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1
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X
1
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1
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1
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1
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1
1
1
0
DSL = Q3 + Q0Q1
0000
12
Y 0 0 0 1 0 1 1 0 1 0 1 1
01011
③
② ”
FPGA Multisim
FPGA
D6
D10
01011
C
3
11
80%
20%
② A (1) (2)
(s)
40 40 40 40
(s)
40 4 40 4 40 4 40 4
②
LED
②
A
A
B
74HC138
74HC161
LED
74HC138
40 ④
4④
74HC161 D
QCC
Q1
0
X
1
0
1
1
1
1
Q0
Q0’
D3
D2
D1
D0
X
X
X
X
X
X
X
X
⑤
3
⑤
1 2
3
4
5
FPGA
1 2
3
② ③
A 4.4 2.
a.
17
TTL CLK b
② Q2 Q1 Q0 8 LED
8 LED
Q2n
Q1n
Q
n 0
Q n+1 2
Q n+1 1
Q n+1 0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
Q1nQ0n
00
0
1
1
0
0
X
0
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
0
0
Q0 Q0’ QCC Q1
00 01 11 10
00
01
11
XXXX XXXX XXXX
XXXX XXXX XXXX
0110 0110
0110 0110
1100 0110
D3D2D1D0
10
XXXX XXXX 0110 0110
D3 = QCC Q1 Q0 Q0’ D2 = 1
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
0
1
0
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0
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1
1
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1
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0
1
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1
1
1
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1
1
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1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
ROW0 ~ ROW3
①
COL0 ~ COL3
12
12
0 1 0 0 0 0
ROW2
0 0 1 0 0 0
ROW3
0 0 0 1 0 0
NUM3
0 0 1 1 0 0
NUM2
0 1 0 1 0 0
NUM1
0 0 0 0 0 0
NUM0
0 0 0 0 0 1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
0
1
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1
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1
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1
0
0
0
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0
0
0
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0
0
0
40
640
1
4
64
2
40
640
3
4
64
4
40
640
5
4
64
6
40
640
7
4
64
0
1
2
3
4
5
6
7
⑤
Q2
0
0
0
0
1
1
1
1
Q1
0
0
1
1
0
0
1
1
Q0
0
1
0
1
0
1
0
1
EW_L_RED
0
0
1
1
0
0
0
0
EW_L_GREEN
1
1
0
1
1
1
1
1
EW_L_YELLOW
1
1
1
0
1
1
1
1
EW_SR_RED
1
1
0
0
0
0
0
0
EW_SR_GREEN
0
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
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1
1
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1
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1
0
1
1
1
1
1
1
1
1
1
1
1
0
8
17
D3
D4 D11
8
8
17
B 4.6 2.
a. MSI
TTL
②
b. MSI
②
01011 CLK
Q3n
Q2n
Q1n
Q
n 0
Q n +1 3
Q n+1 2
0000
12
Y 0 1 0 1 1 0 1 0
1 1 0 1
01011
D6
D8
01011 c.
4 DSL
②
Q0 ②
① /
Q 0n
Q1n
Q2n
Q3n
DSL
Q n+1 0
Q n+1 1
Q n+1 2
Q n +1 3
0
0
0
0
1
0
0
0
1
0
0
0
1
X
0
0
1
X
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
0
X
1
0