数字音频接口数据记录系统中英文对照外文翻译文献

中英文资料外文翻译文献

微型计算机的数字音频接口PROCESSOR-BASED数据记录系统

摘要：

提出了一种廉价的接口实现了数字化数据直接转移,从数字音频处理器和视频盒式录音机的基础数据采集系统设计和Bezanilla(1985年。j .47:437 - 441)给一个IBM的PC / XT微型计算机。FORTRAN语言的可收回软件驱动接口很能干控制的录音机和视频数据采集后,立即开始承认的一个环节之前收集的数据。这使得分段分析数据的长的时间间隔,否则将超过记忆能力的微型计算机。

高容量的数据记录系统所设计的F。Bezanilla(1985)是很有价值的从业人员记录单通道,因为它可以存储为二通道的非常精确的数据(16位分辨率)、采样在一个流畅的速度增长(44100个样本/秒)、延长一段时间(3 h).我们有,不过,遇到限制电脑技术问题进行了分析这样的数据记录。尤其是当数据播放时是很难精确或可以吗选择一个数值的数据存储在计算机记忆。这个困难促使我们开发一个接口Bezanilla之间的数据记录系统和PC / XT微型计算机模型(IBM 仪器有限公司,IBM公司,Danbury,CT)。文中介绍了界面能够获取的数据重复同样的间隔内吗和检索连续间隔。后者能力允许单通道记录分析有很大的影响在持续时间超过的数据存储容量的电脑(< 6 s数据每512 k,宽带下载1秒钟的记忆)。

我们由一个开关盒接口选择左边或者右通道采样、一个插件电脑板那multiplexes 16位数据转移的8位元计算机数据总线,和一个汇编语言程序控制视频录音机(VCR)和指导在时序存放数据的内存位置。两功能模式是可得到的。在这个互动的模式录像机和数据数组开始重复,直到充满了一个键被按下。录像,然后当场-20年代的位置开始之前收集到的数据。在自动模式调用程序提供了一个标记42岁的顺序,以前采样数据点。VCR开始时,输入的数据进行了比较,结果表明该标记物的一部分。如果找到匹配的阵列的数据都被填满立即与数

据跟踪标记。充满立即与数据跟踪标记。这然后当场录像-20年后,一个位置开始的数据和控制返回到调用程序。如果没有找到匹配的在一个可调的时期回放的(1分钟0.5 h),录影带是当场60年代和子程序返回一个国旗表示这些数据收集并不成功。如果最后的42数据每一个记录点作为标记为下一个记录,序贯子功能调用在自动模式将产量检索的连续数据块。

虽然我们是硬件接口描述特定对我们的仪器和计算机,适应设备应直截了当。然而,速度8255接口芯片的限制,以防止出现利用这个特别的接口AT-type IBM电脑那操作的6 - 8兆赫的钟速度。我们接口硬件中所示图1。总成本电脑板和其它部件——150美元。这所设计的数字输出阶段Bezanilla提供的话时钟左眼和右眼的数据通道和16个平行数据线路。在我们的数字音频处理器(阶级501;Unitrade公司、费城、PA)这些信号是可得到的在一个25-pin连接器在后方的底盘。一个带状电缆分机号是用来连接这些线条类似的接头安装在一边,5”×2.5 " x 1.5”塑料盒。点对点的线路连接在盒子里一个37-pin数据线路接头安装在对面盒,连接到一个时钟线渠道的选择开关、控制线路和线路从37-pin录像机连接器连接到一个六角五接头。第二个带状电缆连接37-pin延伸连接件的开关盒的匹配连接器插件电脑板。

图1的电子线路数字接口。并行数字输出的数字音频处理器被A和B的港口8255可编程外围接口芯片P1012计算机板上。8255年设定每一个16位数据转换成词两个8字在电脑上转移公共汽车。电线连接器,DB-25之间DC-37连接器在开关盒便利数字音频处理器连接到P1012计算机卡。选择数字音频处理器数据信道是由开关选择时钟信号的输入连接到8255端口的握手c 成分添加到PI012卡激活玩,重新再来,让停止功能的视频录音机的控制下,通过optoisolators 6和7位港口C。

MetraByte公司、Taunton,马02780)修改允许由电脑控制录放影机。该板包含一位8255可编程外围接口芯片(英特尔公司、圣克拉拉、CA),一个数据总线缓冲区,和一个地址译码器。未使用的区域在顶部的电路板提供充足的房间一根电线包裹集成电路哪幢房子的其它部件的插座中显示图1 .从添加组件连接现有板可以改变,以适应焊接到短距离跳投电路一侧的板。唯一的其他修改需要的是去除的电源电压从针12、14、16和18 37-pin连接的,所以这些线可以用于录像机控制。5 V - 12 V,和+ 12 V线路,最好是不需要被中断割下了3电路板靠近他们接触痕迹计算机总线。切除+ 5 V远销18的要求两个边路的切割痕迹顶部和方法37-pin底部连接组件的一面板和安装一个跳投,把比分重新这些两个+ 5 V痕迹。

这运行,停止,后退、我们的录像机功能(模型SL-HF450;索尼公司,美国长岛的城市,纽约通常是由沮丧SPST触发开关位于前面板。修改这个录像机仅含安装了一个六角五连接器。背面板及连接杆地面和。没有根植,双方的运行,停止,后退、开关。这些线是相连的,通过开关盒,到三个人4 N36 optoisolators 安装在P1012电路板。激活的optoisolators相当于沉闷相应的开关,录放影机。

宏汇编源代码图2为控制界面。这个子程序可以对计划8255年为数据传输、存储数据微电脑记忆,和控制视频盒式录音机。致电本程序指令,描述了它的算法给出了评论。

软件驱动数据传输正在写的宏汇编,是微软打算联系微软FORTRAN调用程序。一个简要介绍了算法也紧随其后。细节算法和指令致电本程序在备注中提供的源代码列在图2。8255年是程序为输入,接二连三的港口b .在这个配置中,0 - 5位用于港口C握手。单词是搭成的数据端口A和B时钟信号通过直接选择比特2和4港口0 C点微机样品港口C(INTR B)当数据来确定词被抓住了。这然后输入一个字,微机登记储存在记忆中。记忆是寄款8每一个点(16个字节)。每一个段落之间的部分增加和偏移登记注册减少16岁。当所需资料收集停止数量的段落的数据已经存储。检测键盘条目是经由函数调用磁盘的时间操作系统(DOS操作系统)。

在自动模式下,提供一个程序标记组成的采样点42之前。一个32位的模板是由第一个最低有效位32分的标记。最重要的每一个采样点的观点是旋转成一

个32位的一对寄存器和对比模板。这在比较了两个阶段。仅当第一个16位比

赛,其他的16位比较。因为,因为真实的数据,最低有效位基本上是随机的,一个16位比赛时发生的频率大约在216年一次每1.5秒。如果一个特定数目的一半比赛发生在总找到匹配的子程序中流产返回一个错误代码。如果一个总找到匹配的数据收藏是开始。前两个点(对应这33rd和34th分漏掉标记)。这未来的

8点是:以一个数组的形式存储在马上preceeds阵列的数据在内存中。我们建

议调用程序确认这些8点都是相同的到最后的8分42-point标记。此后,点中存储的数据的数组。完成的控制,通过使用录像机的位元第六条、第七条的规定的港口C 8255。这些都是没有要求握手,编程为输出。7442BCD-to-Decimal转换器是用来demultiplex这些两位。代码C6 C7 = 00,03,和10个激活玩,停止,收、功能,分别。位C6、C7通常设定,导致任何行动。当一方或两位被复位,适当的输出的7442驱使低,激活相应的4 N36 optoisolator。一个软件定时器是用来控制的时间optoisolator激活与时间之间录像机的命令。我们也观察到的唯一缺陷测试接口调用子程序偶尔的失败来侦测标记。这发生< 1%的时间。通常,一个第二给同一标记子程序执行正确的。我们相信这次失败源于误读录像。作者将很高兴提供感兴趣的读者与磁盘拷贝的列在图二子程序和它的组装目标代码。有这样要的的朋友在邮寄是请在邮件里放上格式化好的软盘。

A MICROCOMPUTER INTERFACE FOR A DIGITAL AUDIO

PROCESSOR-BASED DATA RECORDING SYSTEM

ABSTRACT An inexpensive interface is described that performs direct transfer of digitized data from the digital audioprocessor and video cassette recorder based data acquisition system designed by Bezanilla (1985, Biophys. J.,47:437-441) to an IBM PC/XT microcomputer. The FORTRAN callable software that drives this interface is capableof controlling the video cassette recorder and starting data collection immediately after recognition of a segment ofpreviously collected data. This permits piecewise analysis of long intervals of data that would otherwise exceed thememory capability of themicrocomputer.

The high capacity data recording system designed by F.Bezanilla (1985) is of great value to practitioners ofsingle-channel recording since it allows storage of two channels of very precise data (16 bit resolution), sampled at an

acceptably fast rate (44,100 samples/s), for extended periods of time (up to 3 h). We have, however, encountered technical problems which limit the computerized analysis of data recorded in this way. In particular, when the data are played back it is difficult to accurately or reproducibly select a given interval of data for storage in computer memory. This difficulty prompted us to develop an interface between Bezanilla's data recording system and the model PC/XT microcomputer (IBM Instruments Inc., IBM Corp., Danbury, CT). The interface described herein is capable of retrieving the same interval of data repeatedly and of retrieving contiguous intervals. The latter capability allows analysis of single channel records which greatly exceed in duration the data storage capacity of the computer(<6 s data per 512 kbytes memory).

Our interface consists of a switch box that selects the left or right channel for sampling, a plug-in computer board that multiplexes the 16-bit data for transfer on the 8-bit computer data bus, and an assembly language subroutine that controls the video cassette recorder (VCR) and directs storage of data in sequential memory locations. Two functional modes are available. In the interactive mode the VCR is started and the data array is filled repetitively until a key is pressed. The video tape is then rewound to a position -20 s before the beginning of the collected data. In the automatic mode the calling program provides a marker of 42 sequential, previously sampled data points. The VCR is started and incoming data are compared with a portion of this marker. If a match is found the data array is filled with the data that immediately follow the marker. The video tape is then rewound to a position -20 s before the beginning of the data and control returns to the calling program. If no match is found within an adjustable period of playback (-1 min to 0.5 h), the video tape is rewound-60 s and the subroutine returns a flag

which indicates that data collection was not successful. If the last 42 data points of each record are used as the marker for the next record, sequential subroutine calls in the automatic mode will yield retrieval of contiguous blocks of data.

Although the interface we describe is hardware specific to our instruments and computer, adaptation to other equipment should be straightforward. However, speed limitations of the 8255 interface chip appear to preclude use of this particular interface with IBM AT-type computers that operate at a 6-8 MHz clock speed. Our interface hardware is depicted in Fig.

1. Total cost for the computer board and additional components is -$150. The digital output stage designed by Bezanilla provides word clocks for the right and left data channels and 16 parallel data lines. In our digital audio processor (DASS 501; Unitrade Inc., Philadelphia, PA) these signals are available on a 25-pin connector at the rear of the chassis. A ribbon cable extension is used to connect these lines to a similar connector mounted on one side of a 5" x

2.5" x 1.5" plastic box. Point-to-point wiring within the box connects the data lines to a 37-pin connector mounted on the opposite side of the box, connects the clock lines to a channel selector switch, and routes control lines for the VCR from the 37-pin connector to a 5-pin hex connector. A second ribbon cable extension connects the 37-pin connector of the switch box to the matching connector of a plug-in computer board.

FIGURE 1 Electronic circuitry of digital interface. The parallel digital output of the digital audio processor is routed to ports A and B of an 8255 programmable peripheral interface chip on a P1012 computer board. The 8255 is programmed to convert each 16-bit data word to two 8-bit words for transfer on the computer bus. Wiring between a DB-25 connector and a DC-37 connector in the switch box facilitates connection of the digital audio processor to the P1012 computer card. Choice of digital audio processor data channel is made by switch selection of the clock signal to be connected to handshaking inputs of the 8255 port C. Components added to the PI012 card activate the play, rewind, and stop functions of the video cassette recorder via optoisolators under the control of bits 6 and 7 of port C.

The computer board we now employ (model PIO12,MetraByte Corp., Taunton, MA 02780) was modified to allow computerized control of the VCR. This board contains an 8255 programmable peripheral interface chip (Intel Corp., Santa Clara, CA), a data bus buffer, and an address decoder. An unused area at the top of the circuit board provides ample room for wire wrap integrated circuit sockets which house the additional components shown in

Fig. 1. Connections from the added components to the existing board may be

made with short jumpers soldered to the circuit side of the board. The only other modification required is the removal of power supply voltages from pins 12, 14, 16, and 18 of the 37-pin connector so that these lines may be used for VCR control. The -5 V, - 12 V, and + 12 V lines are not required and are best interrupted by cutting three circuit board traces near their contacts with the computer bus. Removal of + 5 V from pin 18 requires cutting of two wide traces which approach the top and bottom of the 37-pin connector on the component side of the board and installation of a jumper to reconnect these two + 5 V traces.

The play, stop, and rewind functions of our VCR (model SL-HF450; Sony Corp. of America, Long Island City,NY) are normally triggered by depressing SPST switches located on the front panel. Modification of this VCR consists simply of mounting a 5-pin hex connector to the back panel and connecting pins to ground and to the ungrounded sides of the play, stop, and rewind switches. These lines are connected, via the switch box, to three 4N36 optoisolators mounted on the P1012 circuit board. Activating one of the optoisolators is equivalent to depressing the corresponding switch of the VCR.

The software that drives the data transfer is written for the Microsoft MACRO ASSEMBLER and is intended to be linked with a Microsoft FORTRAN calling program. A brief overview of the algorithm follows. Details of the algorithm and instructions for calling the subroutine are provided in the remarks of the source code listed in Fig. 2. The 8255 is programmed for strobed input of ports A and B. In this configuration, bits 0-5 of port C are used for handshaking. The data word is latched into ports A and B by directing the selected clock signal to bits 2 and 4 of port C. The microcomputer samples bit 0 of port C (INTR B) to determine when the data word has been latched. The