ISPLSI2032-150LT48I中文资料

ispLSI ?

2032/A

In-System Programmable High Density PLD

S E i s

p L S

I 2032

E F O R

Features

?ENHANCEMENTS

—ispLSI 2032A is Fully Form and Function Compatible

to the ispLSI 2032, with Identical Timing Specifcations and Packaging

—ispLSI 2032A is Built on an Advanced 0.35 Micron

E 2CMOS ? Technology ?HIGH DENSITY PROGRAMMABLE LOGIC

—1000 PLD Gates

—32 I/O Pins, Two Dedicated Inputs —32 Registers

—High Speed Global Interconnect

—

Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

—Small Logic Block Size for Random Logic

?HIGH PERFORMANCE E 2CMOS ? TECHNOLOGY —f max = 180 MHz Maximum Operating Frequency —t pd = 5.0 ns Propagation Delay

—TTL Compatible Inputs and Outputs

—Electrically Erasable and Reprogrammable —Non-Volatile

—100% Tested at Time of Manufacture

—

Unused Product Term Shutdown Saves Power

?IN-SYSTEM PROGRAMMABLE

—In-System Programmable (ISP?) 5V Only

—Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality

—Reprogram Soldered Devices for Faster Prototyping

?OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

—Complete Programmable Device Can Combine Glue

Logic and Structured Designs —Enhanced Pin Locking Capability —Three Dedicated Clock Input Pins

—Synchronous and Asynchronous Clocks —Programmable Output Slew Rate Control to

Minimize Switching Noise —Flexible Pin Placement

—Optimized Global Routing Pool Provides Global Interconnectivity

Description

The ispLSI 2032 and 2032A are High Density Program-mable Logic Devices. The devices contain 32 Registers,32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032 and 2032A feature 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2032 and 2032A offer non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.The basic unit of logic on these devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. A7(Figure 1). There are a total of eight GLBs in the ispLSI 2032 and 2032A devices. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.

Functional Block Diagram

Copyright ? 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

LATTICE SEMICONDUCTOR CORP ., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; https://www.360docs.net/doc/1117153668.html,

January 2002

Specifications ispLSI 2032/A

S E

i s

p L

S I

2032E

F O

E W

E S I G N

Absolute Maximum Ratings 1

Supply Voltage V cc ...................................-0.5 to +7.0V Input Voltage Applied........................-2.5 to V CC +1.0V Off-State Output Voltage Applied .....-2.5 to V CC +1.0V

Storage Temperature................................-65 to 150°C

Case Temp. with Power Applied ..............-55 to 125°C

Max. Junction Temp. (T J ) with Power Applied ...150°C

1.Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

T A = 0°C to + 70°C

T A = -40°C to + 85°C

SYMBOL Table 2 - 0005/2032

V CC

V IH

V IL PARAMETER

Supply Voltage Input High Voltage

Input Low Voltage MIN.MAX.UNITS 4.75 4.5

2.0

5.25 5.5V cc +1

0.8V V V

V Commercial Industrial

Capacitance (T A =25°C, f=1.0 MHz)

C SYMBOL

Table 2-0006/2032

C PARAMETER I/O Capacitance 7UNITS TYPICAL

TEST CONDITIONS 126Dedicated Input Capacitance pf pf V = 5.0V, V = 2.0V V = 5.0V, V = 2.0V CC CC I/O IN C Clock Capacitance

V = 5.0V, V = 2.0V CC Y

Data Retention Specifications

Table 2-0008A-isp

PARAMETER Data Retention

MINIMUM

MAXIMUM

UNITS Erase/Reprogram Cycles

2010000

– –

Years Cycles

Specifications ispLSI 2032/A

S E

i s

p L S I

032E

F O

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E S I G N

External Timing Parameters

Over Recommended Operating Conditions

t pd1UNITS -150MIN.TEST COND.1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section.

Table 2-0030B-180/2032

3 1

tsu2 + tco1

( )-135

MIN.MAX.MAX.

DESCRIPTION #

PARAMETER

A 1Data Prop. Delay, 4PT Bypass, ORP Bypass – 5.5–7.5ns t pd2A 2Data Prop. Delay

––

ns f max

A 3Clk Frequency with Internal Feedback 154–137–MHz f max (Ext.)–4Clk Frequency with Ext. Feedback ––MHz f max (Tog.)–5Clk Frequency, Max. Toggle

–

MHz t su1–6GLB Reg Setup Time before Clk, 4 PT Bypass –

–

ns t co1A 7GLB Reg. Clk to Output Delay, ORP Bypass –

–ns t h1–8GLB Reg. Hold Time after Clk, 4 PT Bypass 0.0–ns t su2–9GLB Reg. Setup Time before Clk 4.5

–

ns t co2–10GLB Reg. Clk to Output Delay ––ns t h2–11GLB Reg. Hold Time after Clk 0.0–ns t r1A 12Ext. Reset Pin to Output Delay ––ns t rw1–13Ext. Reset Pulse Duration 4.5–ns t ptoeen B 14Input to Output Enable ––ns t ptoedis C 15Input to Output Disable ––ns t goeen B 16Global OE Output Enable ––ns t goedis C 17Global OE Output Disable

––ns t wh –18Ext. Synchronous Clk Pulse Duration, High 3.0––ns t wl

–

19Ext. Synchronous Clk Pulse Duration, Low

3.0

–

1111673.0 4.5––5.0

–8.0–11.011.05.05.08.0-180MIN.MAX.– 5.0–180–––––0.04.0–0.0–4.0

––––2.5–2.5–

1252003.0 4.0––4.5–7.0

–10.010.05.05.07.51001674.00.05.50.05.03.03.0

10.04.55.510.012.012.06.06.0

Specifications ispLSI 2032/A

S E

i s

p L S I

2032E

F O

E W

D E S I G N

External Timing Parameters

Over Recommended Operating Conditions

t pd1UNITS -110MIN.TEST COND.1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section.

Table 2-0030B-110/2032

1 tsu

2 + tco1

( )-80MIN.MAX.MAX.

DESCRIPTION #

PARAMETER

A 1Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0– 15.0ns t pd2A 2Data Propagation Delay

– – ns f max

A 3Clock Frequency with Internal Feedback 111– 84.0– MHz f max (Ext.)– 4Clock Frequency with External Feedback – –

MHz f max (Tog.)– 5Clock Frequency, Max. Toggle

– – MHz t su1– 6GLB Reg. Setup Time before Clock, 4 PT Bypass –

–

ns t co1A 7GLB Reg. Clock to Output Delay, ORP Bypass –

–

ns t h1– 8GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0

–

ns t su2– 9

GLB Reg. Setup Time before Clock

7.5

–

ns t co2– 10GLB Reg. Clock to Output Delay –

–

ns t h2– 11GLB Reg. Hold Time after Clock 0.0– ns t r1A 12Ext. Reset Pin to Output Delay – – ns t rw1– 13Ext. Reset Pulse Duration 6.5

–

ns t ptoeen B 14Input to Output Enable – – ns t ptoedis C 15Input to Output Disable – – ns t goeen B 16Global OE Output Enable – – ns t goedis C 17Global OE Output Disable

– – ns t wh – 18External Synchronous Clock Pulse Duration, High 4.0– – ns t wl

–

19External Synchronous Clock Pulse Duration, Low

4.0

–

77.01255.5

5.5

– – 6.5

–

13.5– 14.514.57.07.013.057.083.07.50.09.50.0

10.0

6.06.0

18.5

8.0

9.519.524.024.012.012.0

Specifications ispLSI 2032/A

S E

i s

p L S I

2032E

F O

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E S I G N

Over Recommended Operating Conditions

Internal Timing Parameters 1

t io 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.

Table 2-0036C-180/2032

Inputs

UNITS

-150MIN.-135

MIN.MAX.MAX.DESCRIPTION

PARAMETER 20Input Buffer Delay –– 1.1ns t din

21Dedicated Input Delay –– 2.4

ns t grp

22GRP Delay

–

1.3

ns GLB

t 1ptxor 25 1 Product Term/XOR Path Delay –

–

5.0

ns t 20ptxor 2620 Product Term/XOR Path Delay –

– 5.1ns t xoradj 27XOR Adjacent Path Delay –– 5.6ns t gbp 28GLB Register Bypass Delay

––0.0ns t gsu 29GLB Register Setup Time before Clock –0.3–ns t gh 30GLB Register Hold Time after Clock – 3.0–ns t gco 31GLB Register Clock to Output Delay ––0.7ns 3t gro 32GLB Register Reset to Output Delay

–– 1.1ns t ptre 33GLB Product Term Reset to Register Delay –– 4.4ns t ptoe 34GLB Product Term Output Enable to I/O Cell Delay

–– 6.4ns t ptck

35GLB Product Term Clock Delay

2.9 5.2ns ORP

t ob 38Output Buffer Delay

–– 1.2ns t sl 39Output Slew Limited Delay Adder ––10.0ns 0.61.3GRP

0.7

t 4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial)–

–

3.6

ns t 4ptbpr 24 4 Product Term Bypass Path Delay (Registered)–

–

3.6

ns 4.34.65.00.02.63.10.71.80.81.22.96.92.5 4.1t orp 36ORP Delay

–– 1.3ns t orpbp

37ORP Bypass Delay

––0.3ns 0.80.3Outputs

1.310.0t oen 40I/O Cell OE to Output Enabled –– 3.2ns t odis 41I/O Cell OE to Output Disabled –– 3.2ns

2.82.8t goe

42Global Output Enable

–– 2.8ns 2.2t gy043Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.1 2.3 2.3ns t gy1/244Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.1 2.3 2.3ns Clocks

2.12.1t gr

45Global Reset to GLB

–

6.4

Global Reset

4.7

-180MIN.MAX.–––––––

––––––––0.61.10.7–– 3.64.14.80.22.33.10.51.80.71.02.85.92.5 3.8––0.70.21.210.0–– 2.82.8–

2.21.91.9 1.91.9–

4.1

Specifications ispLSI 2032/A

S E

i s

p L S I

2032E

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E S I G N

Internal Timing Parameters 1

Over Recommended Operating Conditions

Table 2-0036C-110/2032

Inputs

UNITS

-110

MIN.-80

MIN.MAX.MAX.DESCRIPTION

PARAMETER 20Input Buffer Delay –

–

2.2ns t din

21Dedicated Input Delay –– 4.8

ns t grp

22GRP Delay

–

2.6

ns GLB

t 1ptxor 25 1 Product Term/XOR Path Delay ––

8.8ns t 20ptxor 2620 Product Term/XOR Path Delay ––9.2ns t xoradj 27XOR Adjacent Path Delay ––10.2ns t gbp 28GLB Register Bypass Delay

––0.0ns t gsu 29GLB Register Setup Time befor Clock –0.1–ns t gh 30GLB Register Hold Time after Clock – 6.0–ns t gco 31GLB Register Clock to Output Delay ––0.4ns 3t gro 32GLB Register Reset to Output Delay

–– 2.2ns t ptre 33GLB Product Term Reset to Register Delay ––8.8ns t ptoe 34GLB Product Term Output Enable to I/O Cell Delay

––12.8ns t ptck

35GLB Product Term Clock Delay

5.59.5ns ORP

t ob 38Output Buffer Delay

–– 2.4ns t sl 39Output Slew Limited Delay Adder ––10.0ns 1.7

3.4GRP

1.7

t 4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial)–

–

7.2

ns t 4ptbpr 24 4 Product Term Bypass Path Delay (Registered)–

–

7.2

ns 6.26.87.50.14.94.80.54.00.61.85.97.14.07.0t orp 36ORP Delay

–– 2.1ns t orpbp

37ORP Bypass Delay

––0.6ns 1.50.5Outputs

1.210.0t oen 40I/O Cell OE to Output Enabled –– 6.4ns t odis 41I/O Cell OE to Output Disabled –– 6.4ns 4.04.0t goe

42Global Output Enable

–– 5.6ns 3.0t gy043Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 3.2 4.6 4.6ns t gy1/244Clock Delay, Y1 or Y2 to Global GLB Clock Line 3.2 4.6 4.6ns Clocks

3.23.2t gr

45Global Reset to GLB

–

12.8

Global Reset

9.0

Specifications ispLSI 2032/A

S E

i s

p L S I

2032E

F O

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E S I G N

Power consumption in the ispLSI 2032 and 2032A de-vices depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 4 shows the relationship between power and operating speed.

Figure 4. Typical Device Power Consumption vs fmax

6080100

100120140160180

f max (MHz)

I C C (m A )

Notes: Configuration of Two 16-bit Counters

Typical Current at 5V, 25° C

ispLSI 2032/A (-150, -180)

ispLSI 2032/A (-80, -110, -135)

907040500127A/2032A

I CC can be estimated for the ispLSI 2032/A using the following equation:

For 2032/A -150, -180: I CC (mA) = 30 + (# of PTs * 0.46) + (# of nets * Max freq * 0.012) For 2032/A -135, -110, -80: I CC (mA) = 21 + (# of PTs * 0.30) + (# of nets * Max freq * 0.012)

Where:

# of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device

Max freq = Highest Clock Frequency to the device (in MHz)

The I CC estimate is based on typical conditions (V CC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions and the program in the device, the actual I CC should be verified.

110120Power Consumption

Specifications ispLSI 2032/A

S E

i s

p L S I

2032E

F O

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E S I G N

ispLSI 2032/A Ordering Information

Part Number Description

Device Number ispLSI XXXX XXX X XXX Grade

Blank = Commercial I = Industrial X

Speed

180 = 180 MHz f max 150 = 154 MHz f max 135 = 137 MHz f max 110 = 111 MHz f max 80 = 84 MHz f max

20322032A

Power L = Low

Package J = PLCC T44 = TQFP T48 = TQFP —Device Family

0212A/2032

INDUSTRIAL

COMMERCIAL

Y L I M A F f )

z H M (x a m t )s n (d p R E B M U N G N I R E D R O E G A K C A P I

S L p s i 4851C C L P n i P -444851P F Q T n i P -444

F Q T n i P -84Table 2-0041B/2032A

ispLSI 2032A-80LJ44I ispLSI 2032A-80LT44I ispLSI 2032A-80LT48I

L I M A F f )

z H M (x a m t )s n (d p R

E B M U N G N I R E D R O E G A K C A P I

S L p s i 0810.5C C L P n i P -440810.5P F Q T n i P -440810.5P F Q T n i P -844515.5C C L P n i P -444515.5P F Q T n i P -444515.5P F Q T n i P -847315.7C C L P n i P -447315.7P F Q T n i P -447315.7P F Q T n i P -8411101C C L P n i P -4411101P F Q T n i P -4411101P F Q T n i P -844851C C L P n i P -444851P F Q T n i P -444

F Q T n i P -842A

302/A 1400-2e l b a T ispLSI 2032A-180LJ44

ispLSI 2032A-180LT44ispLSI 2032A-180LT48ispLSI 2032A-150LJ44ispLSI 2032A-150LT44ispLSI 2032A-150LT48ispLSI 2032A-135LJ44ispLSI 2032A-135LT44ispLSI 2032A-135LT48ispLSI 2032A-110LJ44ispLSI 2032A-110LT44ispLSI 2032A-110LT48ispLSI 2032A-80LJ44ispLSI 2032A-80LT44ispLSI 2032A-80LT48

Specifications ispLSI 2032/A

S E

i s

p L S I

2032E

F O

E W

E S I G N

INDUSTRIAL

COMMERCIAL

f )

z H M (x a m t )s n (d p PACKAGE ORDERING NUMBER FAMIL Y

ispLSI

0810.50810.50810.54515.54515.54515.57315.77315.77315.7111011110111101485148514

302/A 1400-2e l b a T ispLSI 2032-180LJ ispLSI 2032-135LJ ispLSI 2032-110LJ ispLSI 2032-80LJ ispLSI 2032-150LJ ispLSI 2032-180LT44ispLSI 2032-110LT44ispLSI 2032-80LT44ispLSI 2032-110LT48ispLSI 2032-80LT48

ispLSI 2032-135LT44ispLSI 2032-135LT48ispLSI 2032-150LT44ispLSI 2032-180LT48ispLSI 2032-150LT4844-Pin PLCC 44-Pin PLCC 44-Pin PLCC 44-Pin PLCC 44-Pin PLCC 44-Pin TQFP 44-Pin TQFP 44-Pin TQFP 48-Pin TQFP 48-Pin TQFP

44-Pin TQFP 48-Pin TQFP 44-Pin TQFP 48-Pin TQFP 48-Pin TQFP Y L I M A F f )

z H M (x a m t )s n (d p R E B M U N G N I R E D R O E G A K C A P I

S L p s i 4851C C L P n i P -444851P F Q T n i P -444

F Q T n i P -84Table 2-0041C/2032

ispLSI 2032-80LJI ispLSI 2032-80LT44I ispLSI 2032-80LT48I