fpga 拨码开关控制流水灯方向

module LED

(

CLK_50M,RST_N,SW1,

LED

);

input CLK_50M;

input RST_N;

input SW1;

output LED;

reg [26:0] time_cnt;

reg [26:0] time_cnt_n;

reg [ 7:0] led_out;

reg [ 7:0] led_out_n;

wire[ 7:0] LED;

parameter SET_TIME = 27'd25_000_000;

always @ (posedge CLK_50M or negedge RST_N) begin

if(!RST_N)

time_cnt <= 27'b0;

else

time_cnt <= time_cnt_n;

end

always @ (*)

begin

if(time_cnt == SET_TIME)

time_cnt_n = 27'b0;

else

time_cnt_n = time_cnt + 1'b1;

end

always @ (posedge CLK_50M or negedge RST_N) begin

if(!RST_N)

led_out <= 8'b10000000;

else

led_out <= led_out_n;

end

always @ (*)

begin

if((time_cnt == SET_TIME) & SW1 == 1'b1)

led_out_n = {led_out[6:0],led_out[7]};

else if((time_cnt == SET_TIME) & SW1 == 1'b0) led_out_n = {led_out[0],led_out[7:1]};

else

led_out_n = led_out;

end

assign LED = ~led_out;

endmodule