caputer生成网表报错原因解析#(精选.)

（1）Warning "No_connect"

#1 Warning [ALG0047] "No_connect" property on Pin "P1.8" ignored forP1: SCHEMATIC1, 13)URAT (7.90, 1.20). Connecting pin to net "N16811229".&H)K]-hwM

$k3D3pd-T$W7he

ALG0047，这个警告基本可以忽略；造成这个问题的原因是，设计之初先对器件相关的管脚上加上'X'(也就是NC符号)，更新设计的过程又对管脚做了连接处理；但是后面的连接处理没有去掉管脚的NC 属性，不信的话把那个管脚上的net删掉看看。 RG9f

解决办法很简单，对这些管脚再做一次NC

（2）Warning Part Name

#5 Warning [ALG0016] Part Name "CAP PN_C100UP-6.3V-SMT-

S_100UF/6.3V" is renamed to "CAP PN_C100UP-6.3V-SMT-

S_100UF/"

这个警告不可避免，allegro对相关的属性名称进行合并，超过一

定数量的字符就截掉；在命名规范的前提下就不考虑这个警告了。无法根治

这个#2 Warning [ALG0016] Part Name "?j#w?rm

之类的错误在于你建立元件原理图的时候你的原件Value值太长了超过32个字符,从而使系统在进行命名规范的时候溢出,而出错,很简单的,只写关键元件名,比如 A2541P10_HDR2X5-100MIL_2X5 HEADER" is renamed to "A2541P10_HDR2X5-100MIL_2X5 HEAD错误只需要

把2X5 HEADER更改为A2541P10,去除中间的空格即可.

Allegro对一些字符[例如"空格","小数点"等等]很在意,可以参阅相关文档的描述.

（3）Error Illegal character "Dot(.)" found in "PCB Footprint"

#1 Error [ALG0081] Illegal character "Dot(.)" found in "PCB Footprint" property for component instance C255:

PG16_AC97, PG16_AC97 (226.06, 132.08) .

封装命名不能包含“.”

（4）Error Illegal character "Forward Slash(/)" found in "PCB Footprint" property

#1 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance

C255: PG16_AC97, PG16_AC97 (226.06, 132.08) .

#2 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance D3: PG01_LED&Switch&7-Segment Disp, PG01_LED&Switch&7-Segment Disp (93.98, 33.02) .

#3 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance

C245: PG16_AC97, PG16_AC97 (205.74, 35.56) .

封装命名不能包含“/”

（5）比较隐藏的排除法

Loading... E:\FPGA\SCH\allegro/pstchip.dat

#34 WARNING(SPCODD-34): Expected ';' character on line 5308. Check the name and value syntax for invalid characters in the

primitive definition before the line number.

ERROR(SPCODD-47): File ./allegro/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing

this situation and package the design again.

#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schematic and rerun packaging.

#187 Error [ALG0036] Unable to read logical netlist data.

Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\motherboard.dsn" -n

"E:\FPGA\SCH\allegro" -c

"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"

*** Done*******

掌握排错方法，查找文件pstchip.dat，第on line 5308 看看错误，便可以解决

（6）封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决

*********************************************************** *********************

** Netlisting the design

*********************************************************** **********************

Design Name:

E:\FPGA\SCH\basicboard.dsn

Netlist Directory:

E:\FPGA\SCH\allegro

Configuration File:

D:\Cadence\SPB_16.2\tools\capture\allegro.cfg

Spawning... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n

"E:\FPGA\SCH\allegro" -c

"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"

#1 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance MG2: Basic, PG06_Stepmotor (180.34, 83.82) .

#2 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance ISO1: Basic, PG05_DC Motor (134.62, 40.64) .

#3 Info: PCB Editor does not support Dots(.), Forward Slash(/) and White space in footprint names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-).

#4 Aborting Netlisting... Please correct the above errors and retry.

Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n

"E:\FPGA\SCH\allegro" -c

"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"

*** Done ***

封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决

（7）Warning

#11 Warning [ALG0051] Pin "GND" is renamed to "GND#A6" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,

3.10).

#12 Warning [ALG0051] Pin "GND" is renamed to "GND#A11" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,

3.10).

#13 Warning [ALG0051] Pin "GND" is renamed to "GND#A1" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,

3.10).

#14 Warning [ALG0051] Pin "GND" is renamed to "GND#W8" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,

3.10).

这条警告信息，在命名规范的前提下就不考虑这个警告了。

无法根治，除非去除检测

（8）

#60 Warning [ALG0016] Part Name

"COM_17×2_SIP17X2_COM_17×2" is renamed to

"COM_172_SIP17X2_COM_172".

#61 Warning [ALG0060] No pins are present in J53. Ignoring this component in netlist.

#62 Warning [ALG0016] Part Name

"1X3P,MALE,DIP_2.0_SIP3_1X3P_2.54MM" is renamed to

"1X3P,MALE,DIP_2.0_SIP3_1X3P_2.5".

器件管脚不存在，有的器件做了但没放管脚，正常

(9) error: Same Pin Number connected to more than one net.

请检查这个器件的位号是否有重复。一般是重复了才会出现这种情况。

Checking Pins and Pin Connections

ERROR: [DRC0031] Same Pin Number connected to more than one net. LED&Switch&7-Segment Disp/U17/3 Nets: '3V3' and '485_RE/DE'.

PG01_LED&Switch&7-Segment Disp,

PG01_LED&Switch&7-Segment Disp (101.85, 73.66)

上面的问题是器件位号重复

（10）

WARNING: [DRC0008] Two nets in same schematic have the same name, but there is no off-page connector

这个问题是信号同名，到没有用OFF-PAGE连接起来生成网表会自动重新命名一个名字

（11）1. Unable to open

c:\Cadence\PSD_14.2\tools\capture\allegro.cfg for reading. Please correct the above error(s) to proceed 错误解释：

allegro.cfg文件找不到或allegro.cfg文件不能打开，这个问题的根源是，有可能每台电脑上安装Allegro的的位置不一样，allegro.cfg文件找不到是理所当然的。

处理办法：

点生成netlist，点setup，修改路径为capture\allegro.cfg所在路径，把allegro.cfg文件的位置选择你现在安装目录的文件位置。

（12）Spawning...

"C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "F:\gcht\CC2430\Projects\mysch.dsn" -n

"C:\CADENCE\PSD_15.1\TOOLS\PROJECTS" -c

"C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "CC2430_DEMO"

#1 Error [ALG0012] Property "PCB Footprint" missing from instance U3: SCHEMATIC1, PAGE1 (2.00, 2.10).

#2 Error [ALG0012] Property "PCB Footprint" missing from instance C2: SCHEMATIC1, PAGE1 (2.30, 0.30).

#17 Aborting Netlisting... Please correct the above errors and retry.

错误解释：

Error [ALG0012] Property "PCB Footprint" missing from part : , ( ,

A PC

B Footprint (JEDEC_TYPE in Allegro) is required for all parts in Allegro. Therefore all parts without this property are listed before aborting the netlisting. You can add the PCB Footprint property by selecting the part listed, then choosing Edit Properties from the pop-up menu and placing a value, such as dip14_3, on the part.

在Allegro中，每个器件都需要一个PCB封装。所以在取消列出网表之前，软件会列出所有没有此项的器件。你可以选择列出的器件添加PCB封装，然后选择Edit Properties来编辑器件的值。

处理办法：

在导出Netlist 之前，只需要保证每个器件都是有封装的，且器件PCB Footprint值与对应的.dra封装文件名一致。

（13）. [DRC0011] Reference is invalid for this part

The reference for the part is invalid. For example, this occurs when a part reference like U?A has not been updated. Update the part reference。

Reference项不可随意修改。

（14） Pin numbers do not match. Check device file.

原因：原理图中的晶振给了两个管脚，而其封装却是四个管脚。原理图与PCB封装对应原则：

除了PCB Footprint的名字要写对以外，还有一点，就是原理图的元件的管脚数目一定要和封装的管脚数目必须一样。这里说的管脚，包括了原理图中可能没有现实的Power Pins,不包括封装中的machanical pins；另外，原理图和封装的对应关系是依靠pin number来建立的，所以两者的相应的pin number一定要一样，而pin number是不是数字并没有关系。

（15）. ERROR(SPMHNI-191): Device/Symbol check error detected.

WARNING(SPMHNI-337): Unable to load symbol 'HDR1X2' for device

'B2S_HDR1X2_B2S': WARNING(SPMHUT-127): Could not find padstack 57S40DP.

due to ERROR(SPMHDB-274): Unable to load flash symbol

THS79X59X45X4X15 (Check PSMPATH setting for this symbol)." 原因：花焊盘Flash没有创建.fsm的symbol文件，或是该文件保存路径与.psm文件不一致。

二、Allegro导入netlist的时候报错can not find symbol：

出现Netrev succeeded即可，说明已没有error了，可以直接打开自动生成的.brd文件了。但此时Updating Allegro PCB Editor Board仍然会有红叉，貌似还有问题。果然，在QuickPlace的时候，有一些器件的Footprint无法Place，提示的错误原因是can not find symbol，不知所云。

有一种可能就是Allegro工作区的面积不够大，而QuickPlace放置的Footprint都位于Outline范围之外，因而如果工作区面积设置的不够大的话，会导致有一些器件的Footprint无法Place。

还有一种可能就是元件在原理图中的引脚数目与Footprint中的引脚数目不一致。这是也会出现Netrev succeeded，同时有警告，但是同样会导致这些器件的Footprint无法Place。

第三种可能：在导入Netlist时会产生如下警告：

WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol

'8P4R_0402_CN_42' for device

'RESARR_IS_4/SM_8P4R_0402_CN_4_1': WARNING(SPMHUT-127): Could not find padstack 8P4R-0402_CN-42_BIGPAD.

即找不到PAD文件。如果本身就没有PAD文件，则按照Datasheet 上面引脚大小自己画一个；若有PAD文件，则应设置好路径：在PCB Editor中Setup→User Preferences→Design_paths，设置padpath和psmpath；若对PAD文件进行过修改（包括重命名），则应在PCB Editor中Tools→Padstack，Replace或Refresh。

第四种可能：.dra封装文件有DRC错误。此时在生成网表时，在Capture的Session Log中只会有Warning而无Error，但QuickPlace仍无法放置该Footprint。如何修改DRC错误。

最新文件仅供参考已改成word文本。方便更改