txs0102 电平转换芯片

FEATURES

DCT OR DCU PACKAGE

(TOP VIEW)1B1827V CCB 36OE 45B2GND V CCA

A2A1YZP PACKAGE (BOTTOM VIEW)A254A136OE V CCA 27V CCB GND 8B1

1B2A1B1C1D1A2B2C2D2DESCRIPTION/ORDERING

INFORMATION https://www.360docs.net/doc/6611045413.html, .......................................................................................................................................................SCES640A–JANUARY 2007–REVISED MAY 2008

2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR

FOR OPEN-DRAIN AND PUSH-PULL APPLICATIONS

?No Direction-Control Signal Needed ?ESD Protection Exceeds JESD 22

?Max Data Rates –A Port

–24Mbps (Push Pull)–2500-V Human-Body Model (A114-B)

–2Mbps (Open Drain)–250-V Machine Model (A115-A)

?Available in the Texas Instruments NanoFree?–1500-V Charged-Device Model (C101)

Package –B Port

? 1.65V to 3.6V on A port and 2.3V to 5.5V on –8-kV Human-Body Model (A114-B)

B port (V CCA ≤V CCB )–250-V Machine Model (A115-A)

?V CC Isolation Feature –If Either V CC Input Is at –1500-V Charged-Device Model (C101)

GND,Both Ports Are in the High-Impedance State ?No Power-Supply Sequencing Required –

Either V CCA or V CCB Can Be Ramped First

?I off Supports Partial-Power-Down Mode

Operation

?Latch-Up Performance Exceeds 100mA Per

JESD 78,Class II This two-bit noninverting translator uses two separate configurable power-supply rails.The A port is designed to track V CCA .V CCA accepts any supply voltage from 1.65V to 3.6V.The B port is designed to track V CCB .V CCA must be less than or equal to V CCB .V CCB accepts any supply voltage from 2.3V to 5.5V.This allows for low-voltage bidirectional translation between any of the 1.8-V,2.5-V,3.3-V,and 5-V voltage nodes.

When the output-enable (OE)input is low,all outputs are placed in the high-impedance state.

To ensure the high-impedance state during power up or power down,OE should be tied to GND through a pulldown resistor;the minimum value of the resistor is determined by the current-sourcing capability of the driver.

ORDERING INFORMATION

T A PACKAGE (1)(2)

ORDERABLE PART NUMBER TOP-SIDE MARKING (3)NanoStar?–WCSP (DSBGA)

Reel of 3000TXS0102YZPR 2H_0.23-mm Large Bump –YZP

Reel of 3000TXS0102DCTR NFEZ___–40°C to 85°C SSOP –DCT

Tube of 250TXS0102DCTT NFEZ ___VSSOP –DCU

Reel of 3000TXS0102DCUR NFE_(1)

Package drawings,thermal data,and symbolization are available at https://www.360docs.net/doc/6611045413.html,/packaging .(2)

For the most current package and ordering information,see the at the end of this document,or see the TI website at https://www.360docs.net/doc/6611045413.html, .(3)DCT:The marking has three additional characters that designate the year,month,and assembly/test site.

DCU:The actual top-side marking has one additional character that designates the assembly/test site.

YZP:The actual top-side marking has three preceding characters to denote year,month,and sequence code,and one following

character to designate the assembly/test site.Pin 1identifier indicates solder-bump composition (1=SnPb,?=Pb-free).

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

3.3 V

1.8 V

TXS0102SCES640A–JANUARY 2007–REVISED MAY https://www.360docs.net/doc/6611045413.html,

PIN DESCRIPTION (DCT AND DCU PACKAGES)

NO.

NAME FUNCTION

B2Input/output B.Referenced to V CCB .2

GND Ground 3

V CCA A-port supply voltage.1.65V ≤V CCA ≤3.6V and V CCA ≤V CCB 4

A2Input/output A.Referenced to V CCA .5

A1Input/output A.Referenced to V CCA .3-state output mode enable.Pull OE low to place all outputs in 3-state mode.6

OE Referenced to V CCA .7

V CCB B-port supply voltage.2.3V ≤V CCB ≤5.5V 8B1Input/output B.Referenced to V CCB .TYPICAL OPERATING CIRCUIT

ABSOLUTE MAXIMUM RATINGS (1)

RECOMMENDED OPERATING CONDITIONS (1)(2)https://www.360docs.net/doc/6611045413.html, .......................................................................................................................................................SCES640A–JANUARY 2007–REVISED MAY 2008over recommended operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT V CCA

Supply voltage range –0.5 4.6V V CCB

Supply voltage range –0.5 6.5V A port –0.5 4.6V I

Input voltage range (2)V B port –0.5 6.5A port –0.5 4.6Voltage range applied to any output V O

V in the high-impedance or power-off state (2)B port –0.5 6.5A port –0.5V CCA +0.5V O

Voltage range applied to any output in the high or low state (2)(3)V B port –0.5V CCB +0.5I IK

Input clamp current V I <0–50mA I OK

Output clamp current V O <0–50mA I O Continuous output current

±50mA Continuous current through V CCA ,V CCB ,or GND

±100mA DCT package

220θJA

Package thermal impedance (4)DCU package 227°C/W YZP package 102T stg

Storage temperature range –65150°C (1)

Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)

The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3)

The value of V CCA and V CCB are provided in the recommended operating conditions table.

(4)The package thermal impedance is calculated in accordance with JESD 51-7.

V CCA

V CCB MIN MAX UNIT V CCA

1.65 3.6Supply V

voltage (3)

V CCB 2.3 5.51.65V to 1.95V V CCI –0.2V CCI A-port I/Os

2.3V to 5.5V 2.3V to

3.6V V CCI –0.4V CCI High-level V IH V input voltage B-port I/Os

V CCI –0.4V CCI 1.65V to 3.6V 2.3V to 5.5V OE input

V CCA ×0.65 5.5A-port I/Os

00.15Low-level V IL B-port I/Os

1.65V to 3.6V

2.3V to 5.5V 00.15V input voltage OE input

0V CCA ×0.35A-port I/Os,push-pull driving 10Input transition Δt/Δv

B-port I/Os,push-pull driving 1.65V to 3.6V 2.3V to 5.5V 10ns/V rise or fall rate Control input 10T A

Operating free-air temperature –4085°C (1)

V CCI is the supply voltage associated with the input port.(2)

V CCO is the supply voltage associated with the output port.

(3)V CCA must be less than or equal to V CCB ,and V CCA must not exceed 3.6V.

ELECTRICAL CHARACTERISTICS (1)(2)(3)TXS0102SCES640A–JANUARY 2007–REVISED MAY https://www.360docs.net/doc/6611045413.html, over recommended operating free-air temperature range (unless otherwise noted)

T A =25°C –40°C to 85°C TEST PARAMETER

V CCA V CCB UNIT CONDITIONS MIN TYP MAX MIN MAX I OH =–20μA,V OHA

1.65V to 3.6V

2.3V to 5.5V V CCA ×0.67V V IB ≥V CCB –0.4V I OL =1mA,V OLA

1.65V to 3.6V

2.3V to 5.5V 0.4V V IB ≤0.15V I OH =–20μA,V OHB

1.65V to 3.6V

2.3V to 5.5V V CCB ×0.67V V IA ≥V CCA –0.2V I OL =1mA,V OLB

1.65V to 3.6V

2.3V to 5.5V 0.4V V IA ≤0.15V I I

OE 1.65V to 3.6V 2.3V to 5.5V ±1±2μA A port 0V 0to 5.5V ±1±2μA I off

B port 0to 3.6V 0V ±1±2μA I OZ

A or

B port 1.65V to 3.6V 2.3V to 5.5V ±1±2μA 1.65V to V CCB 2.3V to 5.5V 2.4V I =V O =open,

I CCA 3.6V

0V 2.2μA I O =00V

5.5V –11.65V to V CCB

2.3V to 5.5V 12V I =V O =open,I CCB

3.6V

0V –1μA I O =00V

5.5V 1V I =V CCI or GND,I CCA +I CCB 1.65V to V CCB

2.3V to 5.5V 14.4μA I O =0C I OE

3.3V

3.3V 2.5 3.5pF A or B port 3.3V 3.3V 10

C io A port 5

6pF B port

67.5(1)

V CCI is the V CC associated with the input port.(2)

V CCO is the V CC associated with the output port.

(3)V CCA must be less than or equal to V CCB ,and V CCA must not exceed 3.6V.

TIMING REQUIREMENTS TIMING REQUIREMENTS TIMING REQUIREMENTS TXS0102

over recommended operating free-air temperature range,V CCA=1.8V±0.15V(unless otherwise noted)

V CCB=2.5V V CC=3.3V V CC=5V

±0.2V±0.3V±0.5V UNIT

MIN MAX MIN MAX MIN MAX

Push-pull driving212224 Data rate Mbp Open-drain driving222

t w Push-pull driving474541 Pulse

Data inputs ns duration Open-drain driving500500500

over recommended operating free-air temperature range,V CCA=2.5V±0.2V(unless otherwise noted)

V CCB=2.5V V CC=3.3V V CC=5V

±0.2V±0.3V±0.5V UNIT

MIN MAX MIN MAX MIN MAX

Push-pull driving202224 Data rate Mbp Open-drain driving222

t w Push-pull driving504541 Pulse

Data inputs ns duration Open-drain driving500500500

over recommended operating free-air temperature range,V CCA=3.3V±0.3V(unless otherwise noted)

V CC=3.3V V CC=5V

±0.3V±0.5V UNIT

MIN MAX MIN MAX

Push-pull driving2324 Data rate Mbps Open-drain driving22

t w Push-pull driving4341 Pulse duration Data inputs ns Open-drain driving500500

SWITCHING CHARACTERISTICS TXS0102SCES640A–JANUARY 2007–REVISED MAY https://www.360docs.net/doc/6611045413.html, over recommended operating free-air temperature range,V CCA =1.8V ±0.15V (unless otherwise noted)

V CCB =2.5V V CCB =3.3V CCB =5V ±0.2V V FROM

TO TEST ±0.5V PARAMETER UNIT ±0.3V (INPUT)(OUTPUT)CONDITIONS

MIN MAX MIN MAX MIN MAX Push-pull driving

5.3 5.4

6.8t PHL Open-drain driving 2.38.8 2.49.6 2.610A

B ns Push-pull driving 6.87.17.5t PLH

Open-drain driving 452603*********Push-pull driving 4.4 4.5 4.7t PHL

Open-drain driving 1.9 5.3 1.1 4.4 1.24B

A ns Push-pull driving 5.3 4.50.5t PLH

Open-drain driving 451753614027102t en

OE A or B 200200200ns t dis

OE A or B 504035ns Push-pull driving 3.29.5 2.39.327.6t rA

A-port rise time ns Open-drain driving 38165301322295Push-pull driving 410.8 2.79.1 2.77.6t rB

B-port rise time ns Open-drain driving 34145231061058Push-pull driving 2 5.9 1.96 1.713.3t fA

A-port fall time Open-drain driving 4.4 6.9 4.3 6.4 4.2 6.1ns Push-pull driving 2.913.8 2.816.2 2.816.2t fB

B-port fall time Open-drain driving 6.913.87.516.2716.2t SK(O)

Channel-to-channel skew

0.70.70.7ns Push-pull driving

212224Max data rate Mbps Open-drain driving 222

SWITCHING CHARACTERISTICS TXS0102

over recommended operating free-air temperature range,V CCA=2.5V±0.2V(unless otherwise noted)

V CCB=2.5

V CCB=3.3V V CCB=5V

FROM TO TEST±0.3V±0.5V PARAMETER UNIT

±0.2V

(INPUT)(OUTPUT)CONDITIONS

MIN MAX MIN MAX MIN MAX

Push-pull driving 3.2 3.7 3.8 t PHL

Open-drain driving 1.7 6.326 2.1 5.8

A B ns

Push-pull driving 3.5 4.1 4.4 t PLH

Open-drain driving432503*********

Push-pull driving3 3.6 4.3 t PHL

Open-drain driving 1.8 4.7 2.6 4.2 1.24

B A ns

Push-pull driving 2.5 1.61 t PLH

Open-drain driving441703714027103 t en OE A or B200200200ns t dis OE A or B504035ns

Push-pull driving 2.87.4 2.6 6.6 1.8 5.6 t rA A-port rise time ns

Open-drain driving34149281212489

Push-pull driving 3.28.3 2.97.2 2.4 6.1 t rB B-port rise time ns

Open-drain driving35151241121264

Push-pull driving 1.9 5.7 1.9 5.5 1.8 5.3 t fA A-port fall time ns

Open-drain driving 4.4 6.9 4.3 6.2 4.2 5.8

Push-pull driving 2.27.8 2.4 6.7 2.6 6.6 t fB B-port fall time ns

Open-drain driving 5.18.8 5.49.4 5.410.4 t SK(O)Channel-to-channel skew0.70.70.7ns

Push-pull driving202224

Max data rate Mbps

Open-drain driving222

V CCB =3.3V V CCB =5V FROM

TO TEST ±0.3V ±0.5V PARAMETER UNIT (INPUT)(OUTPUT)CONDITIONS

MIN MAX MIN MAX Push-pull driving

2.4

3.1t PHL

Open-drain driving 1.3 4.2 1.4 4.6A

B ns Push-pull driving 4.2 4.4t PLH

Open-drain driving 3620428165Push-pull driving 2.5 3.3t PHL

Open-drain driving 1124197B

A ns Push-pull driving 2.5 2.6t PLH

Open-drain driving 31393105t en

OE A or B 200200ns t dis

OE A or B 4035ns Push-pull driving 2.3 5.6 1.9 4.8t rA

A-port rise time ns Open-drain driving 251161985Push-pull driving 2.5 6.4 2.17.4t rB

B-port rise time ns Open-drain driving 261161472Push-pull driving 2 5.4 1.95t fA

A-port fall time ns Open-drain driving 4.3 6.1 4.2 5.7Push-pull driving 2.37.4 2.47.6t fB

B-port fall time ns Open-drain driving 57.6 4.88.3t SK(O)

Channel-to-channel skew 0.70.7ns Push-pull driving

2324Max data rate Mbps Open-drain driving 22

PRINCIPLES OF OPERATION Applications

Architecture

CCA V

CCB

Input Driver Requirements Power Up

Enable and Disable TXS0102

https://www.360docs.net/doc/6611045413.html,.......................................................................................................................................................SCES640A–JANUARY2007–REVISED MAY2008 The TXS0102can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another.The TXS0102is ideal for use in applications where an open-drain driver is connected to the data I/Os.The TXS0102can also be used in applications where a push-pull driver is connected to the data I/Os,but the TXB0102might be a better option for such push-pull applications.

The TXS0102architecture(see Figure1)does not require a direction-control signal to control the direction of data flow from A to B or from B

Figure1.Architecture of a TXS01xx Cell

Each A-port I/O has an internal10-k?pullup resistor to V CCA,and each B-port I/O has an internal10-k?pullup resistor to V CCB.The output one-shots detect rising edges on the A or B ports.During a rising edge,the one-shot turns on the PMOS transistors(T1,T2)for a short duration,which speeds up the low-to-high transition.

The fall time(t fA,t fB)of a signal depends on the output impedance of the external device driving the data I/Os of the TXS0102.Similarly,the t PHL and max data rates also depend on the output impedance of the external driver. The values for t fA,t fB,t PHL,and maximum data rates in the data sheet assume that the output impedance of the external driver is less than50?.

During operation,ensure that V CCA≤V CCB at all times.During power-up sequencing,V CCA≥V CCB does not damage the device,so any power supply can be ramped up first.

The TXS0102has an OE input that is used to disable the device by setting OE low,which places all I/Os in the Hi-Z state.The disable time(t dis)indicates the delay between the time when OE goes low and when the outputs actually get disabled(Hi-Z).The enable time(t en)indicates the amount of time the user must allow for the one-shot circuitry to become operational after OE is taken high.

TXS0102

SCES640A–JANUARY2007–REVISED https://www.360docs.net/doc/6611045413.html, Pullup or Pulldown Resistors on I/O Lines

Each A-port I/O has an internal10-k?pullup resistor to V CCA,and each B-port I/O has an internal10-k?pullup resistor to V CCB.If a smaller value of pullup resistor is required,an external resistor must be added from the I/O to V CCA or V CCB(in parallel with the internal10-k?resistors).

PARAMETER MEASUREMENT INFORMATION

V OH V OL

Output Control (low-level enabling)Output Waveform 1S1 at 2 × V CCO (see Note B)Output Waveform 2S1 at GND (see Note B)0 V

0 V V CCI

0 V

V CCA V CCO VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS

PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES

Input A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, Z O = 50 ?, dv/dt ≥ 1 V/ns.

D.The outputs are measured one at a time, with one transition per measurement.

E.t PLZ and t PHZ are the same as t dis .

F.t PZL and t PZH are the same as t en .

G.t PLH and t PHL are the same as t pd .

H.V CCI is the V CC associated with the input port.

I.V CCO is the V CC associated with the output port.

J.All parameters and waveforms are not applicable to all devices.

W DATA RATE, PULSE DURATION, PROPAGATION DELAY ,

OUTPUT RISE AND FALL TIME MEASUREMENT USING

A PUSH-PULL DRIVER W DATA RATE, PULSE DURATION, PROPAGATION DELAY ,OUTPUT RISE AND FALL TIME MEASUREMENT USING AN OPEN-DRAIN DRIVER

TXS0102

Figure 2.Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status(1)Package

Type Package

Drawing

Pins Package

Qty

Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)

TXS0102DCTR ACTIVE SM8DCT83000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TXS0102DCTRE4ACTIVE SM8DCT83000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TXS0102DCTT ACTIVE SM8DCT8250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TXS0102DCTTE4ACTIVE SM8DCT8250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TXS0102DCTTG4ACTIVE SM8DCT8250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TXS0102DCUR ACTIVE US8DCU83000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TXS0102DCURG4ACTIVE US8DCU83000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TXS0102DCUT ACTIVE US8DCU8250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TXS0102DCUTG4ACTIVE US8DCU8250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TXS0102YZPR ACTIVE DSBGA YZP83000Green(RoHS&

no Sb/Br)

SNAGCU Level-1-260C-UNLIM

TXS0102YZTR ACTIVE DSBGA YZT83000Green(RoHS&

no Sb/Br)

SNAGCU Level-1-260C-UNLIM

(1)The marketing status values are defined as follows:

ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.

OBSOLETE:TI has discontinued the production of the device.

(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check https://www.360docs.net/doc/6611045413.html,/productcontent for the latest availability information and additional product content details.

TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.

Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)

(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI

to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal Device Package Type Package Drawing

Pins

SPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant TXS0102DCUR US8

DCU 83000180.09.2 2.25 3.35 1.05 4.08.0Q3TXS0102YZPR DSBGA

YZP 83000180.08.4 1.1 2.10.56 4.08.0Q1TXS0102YZTR DSBGA YZT 83000180.08.4 1.02 2.020.75

4.08.0Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) TXS0102DCUR US8DCU83000202.0201.028.0 TXS0102YZPR DSBGA YZP83000220.0220.034.0 TXS0102YZTR DSBGA YZT83000220.0220.034.0

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MAX232芯片可以完成TTL与EIA双向电平转换

TTL/CMOS INPUTS 端.这个端口是的作用是输入TLL或CMOS信号的...一般为0-5V... 低电平为零,高电平为VCC. TTL/CMOS OUTPUTS端,这个端口的作用是输出TLL或CMOS信号...输出电压一般为0-5V...低电平为零..高电平为VCC. RS232 OUTPUTS 这端口是把TTL或CMOS的信号转为RS232的信号输出...输出为正负12V...到电脑.... RS232 INPUTS 这个端口是接收到电脑发出的正负12伏...由232输出转为TTL或CMOS信号...这个信号也为正负12V... MAX232内部有二组232转换电路... 使用的时候...一般是11------ 14 13----12为一组. 10-----7 8----9为一组... 51单片机要与PC机进行串口通信，通常使用MAX232芯片来作电平转换。下面把MAX232与51单片机的接口电路贴出来供大家参考。（此电路图已经过实际验证） MAX232芯片可以完成TTL与EIA双向电平转换，MAX232提供两路串口电平转换，现在只用一路串口，所以另一路悬空不使用，MAX232与51单片机接口电路如下图所示。（单击图片可放大）

图中DB9为串口的插头(母接头)，插座共有9个引线. MAX232的12脚接单片机的P3.0(RXD) MAX232的12脚接单片机的P3.1(TXD) MAX232还带有4个电容，都是容量都是104，为了减少电路板体积，可以用无极电容代替极性电容。 VCC 是5V DC 提示：串口插座有公母两种类型其中公的串口插座是带有插针的(有针) 母的串口插座是不带有插针的(有洞) 如下图所示由以上分析可知，DB9为母接头，而电脑PC的串口接头一般是分接头。所以此电路与PC相连时，所用的串口线应该是一公一母的串口线。TTL电平信号被利用的最多是因为通常数据表示采用二进制规定，+5V等价于逻辑"1"，0V等价于逻辑"0"，这被称做TTL（晶体管-晶体管逻辑电平）信号系统，这是计算机处理器控制的设备内部各部分之间通信的标准技术。 TTL电平信号对于计算机处理器控制的设备内部的数据传输是很理想的，首先计算机处理器控制的设备内部的数据传输对于电源的要求不高以及热损耗也较低，另外TTL 电平信号直接与集成电路连接而不需要价格昂贵的线路驱动器以及接收器电路；再者，计算机处理器控制的设备内部的数据传输是在高速下进行的，而TTL接口的操作恰能满足这个要求。TTL型通信大多数情况下，是采用并行数据传输方式，而并行数据传输对于超过10英尺的距离就不适合了。这是由于可靠性和成本两面的原因。因为在并行接口中存在着偏相和不对称的问题，这些问题对可靠性均有影响；另外对于并行数据传输，电缆以及连接器的费用比起串行通信方式来也要高一些。

详解电平种类与电平转换

详解电平种类与电平转换 1. 常用的电平转换方案 (1) 晶体管+上拉电阻法就是一个双极型三极管或 MOSFET，C/D极接一个上拉电阻到正电源，输入电平很灵活，输出电平大致就是正电源电平。 (2) OC/OD 器件+上拉电阻法跟 1) 类似。适用于器件输出刚好为 OC/OD 的场合。 (3) 74xHCT系列芯片升压(3.3V→5V) 凡是输入与 5V TTL 电平兼容的 5V CMOS 器件都可以用作3.3V→5V电平转换。 ——这是由于 3.3V CMOS 的电平刚好和5V TTL电平兼容（巧合），而 CMOS 的输出电平总是接近电源电平的。廉价的选择如 74xHCT(HCT/AHCT/VHCT/AHCT1G/VHCT1G/...) 系列 (那个字母 T 就表示 TTL 兼容)。 (4) 超限输入降压法(5V→3.3V,3.3V→1.8V, ...) 凡是允许输入电平超过电源的逻辑器件，都可以用作降低电平。这里的"超限"是指超过电源，许多较古老的器件都不允许输入电压超过电源，但越来越多的新器件取消了这个限制 (改变了输入级保护电路)。例如，74AHC/VHC 系列芯片，其 datasheets 明确注明"输入电压范围为0~5.5V"，如果采用 3.3V 供电，就可以实现5V→3.3V电平转换。 (5) 专用电平转换芯片最著名的就是 164245，不仅可以用作升压/降压，而且允许两边电源不同步。这是最通用的电平转换方案，但是也是很昂贵的 (俺前不久买还是￥45/片，虽是零售，也贵的吓人)，因此若非必要，最好用前两个方案。 (6) 电阻分压法最简单的降低电平的方法。5V电平，经1.6k+3.3k电阻分压，就是3.3V。 (7) 限流电阻法如果嫌上面的两个电阻太多，有时还可以只串联一个限流电阻。某些芯片虽然原则上不允许输入电平超过电源，但只要串联一个限流电阻，保证输入保护电流不超过极限(如 74HC 系列为 20mA)，仍然是安全的。 (8) 无为而无不为法只要掌握了电平兼容的规律。某些场合，根本就不需要特别的转换。例如，电路中用到了某种 5V 逻辑器件，其输入是 3.3V 电平，只要在选择器件时选择输入为 TTL 兼容的，就不需要任何转换，这相当于隐含适用了方法3)。

串口电平转换芯片数据手册SP3222_3232E

DESCRIPTION s Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply s 235KBps Transmission Rate Under Load s 1μA Low-Power Shutdown with Receivers Active (SP3222E ) s Interoperable with RS-232 down to +2.7V power source s Enhanced ESD Specifications: ±15kV Human Body Model ±15kV IEC1000-4-2 Air Discharge ±8kV IEC1000-4-2 Contact Discharge The SP3222E/3232E series is an RS-232 transceiver solution intended for portable or hand-held applications such as notebook or palmtop computers. The SP3222E/3232E series has a high-efficiency, charge-pump power supply that requires only 0.1μF capacitors in 3.3V operation. This charge pump allows the SP3222E/3232E series to deliver true RS-232performance from a single power supply ranging from +3.3V to +5.0V. The SP3222E/3232E are 2-driver/2-receiver devices. This series is ideal for portable or hand-held applications such as notebook or palmtop computers. The ESD tolerance of the SP3222E/3232E devices are over ±15kV for both Human Body Model and IEC1000-4-2 Air discharge test methods. The SP3222E device has a low-power shutdown mode where the devices' driver outputs and charge pumps are disabled. During shutdown, the supply current falls to less than 1μA. SELECTION TABLE L E D O M s e i l p p u S r e w o P 232-S R s r D e v i r 232-S R s r e v i e c e R l a n r e t x E s t n e n o p m o C n w o d t u h S L T T a S -3e t t f o .o N s n i P 2223P S V 5.5+o t V 0.3+224s e Y s e Y 02,812 323P S V 5.5+o t V 0.3+2 2 4 o N o N 6 1

电平转换方法

5V-3.3V电平转换方法在实际电路设计中，一个电路中会有不同的电平信号。方案一：使用光耦进行电平转换首先要根据要处理的信号的频率来选择合适的光耦。高频(20K~1MHz)可以用高速带放大整形的光藕，如6N137/TLP113/TLP2630/4N25等。如果是20KHz以下可用TLP521。然后搭建转换电路。如将3.3V信号转换为5V信号。电路如下图： CP是3.3V的高速信号，通过高速光耦6N137转换成5V信号。如果CP接入的是5V 的信号VCC=3.3V，则该电路是将5V信号转换成3.3V信号。优点：电路搭建简单，可以调制出良好的波形，另外光耦还有隔离作用。缺点：对输入信号的频率有一定的限制。方案二：使用三极管搭建转换电路三极管的开关频率很高，一般都是几百兆赫兹，但是与方案一相比，电路搭建相对麻烦，而且输出的波形也没有方案一的好。电路如下图：其中C1为加速电容，R1为基极限流电阻，R2为集电极上拉电阻，R3将输入端下拉到地，保证在没有输入的情况下，输出端能稳定输出高电平。同时在三极管截止时给基区过量的电荷提供泄放回路缩短三极管的退饱和时间。优点：开关频率高，在不要求隔离，考虑性价比的情况下，此电路是很好的选择。缺点：输出波形不是很良好。方案三：电阻分压这里分析TTL电平和COMS电平的转换。首先看一下TTL电平和CMOS电平的区别。 TTL电平：输出高电平>2.4V,输出低电平<0.4V。在室温下，一般输出高电平是3.5V，输出低电平是0.2。最小输入高电平>=2.0V,输入低电平<=0.8,噪声容限是0.4V。 CMOS电平：1逻辑电平电压接近于电源电压，0逻辑电平接近于0V。而且有很宽的噪声容限。下面的电路是将5V的TTL电平转换成3V的TTL电平

不同逻辑电平器件的互连问题分析

不同逻辑电平器件的互连问题分析 1：逻辑器件的互连总则在不同逻辑电平器件之间进行互连时主要考虑以下几点： ?电平关系，必须保证在各自的电平范围内工作，否则，不能满足正常逻辑功能，严重时会烧毁芯片。 ?驱动能力，必须根据器件的特性参数仔细考虑，计算和试验，否则很可能造成隐患，在电源波动，受到干扰时系统就会崩溃。 ?时延特性，在高速信号进行逻辑电平转换时，会带来较大的延时，设计时一定要充分考虑其容限。选用电平转换逻辑芯片时应慎重考虑，反复对比。通常逻辑电平转换芯片为通用转换芯片，可靠性高，设计方便，简化了电路，但对于具体的设计电路一定要考虑以上三种情况，合理选用。对于数字电路来说，各种器件所需的输入电流、输出驱动电流不同，为了驱动大电流器件、远距离传输、同时驱动多个器件，都需要审查电流驱动能力：输出电流应大于负载所需输入电流；另一方面，TTL、CMOS、ECL等输入、输出电平标准不一致，同时采用上述多种器件时应考虑电平之间的转换问题。我们在电路设计中经常遇到不同的逻辑电平之间的互连，不同的互连方法对电路造成以下影响： ?对逻辑电平的影响。应保证合格的噪声容限（Vohmin－Vihmin≥0.4V，Vilmax－Volmax ≥0.4V)，并且输出电压不超过输入电压允许范围。 ?对上升/下降时间的影响。应保证Tplh和Tphl满足电路时序关系的要求和EMC的要求。 ?对电压过冲的影响。过冲不应超出器件允许电压绝对最大值，否则有可能导致器件损坏。

TTL和CMOS的逻辑电平关系如下图所示：图1： TTL和CMOS的逻辑电平关系图图2：低电压逻辑电平标准 3.3V的逻辑电平标准如前面所述有三种，实际的3.3V TTL/CMOS逻辑器件的输入电平参数一般都使用LVTTL或3.3V逻辑电平标准（一般很少使用LVCMOS输入电平），输出电平参数在

常见TTL电平转换电路

常见TTL电平转换电路 ------设计参考 1.二、三级管组成的TTL/CMOS电平转换电路，优点是价格非常低，缺点是要求使用在信号频率较低的条件下。建议上拉电阻为10K时，可使用在信号频率为几百Khz以下的环境中，曾经在960Khz 的串口通信中做过测试。上拉电阻越小，速率越高，但是电路的功耗也越高，在低功耗要求高的电路中需要慎重考虑。在选择二、三极管时，尽量选用结电容小，开关速率高的。 A ) 图1所示电路，仅能使用在输入信号电平大于输出信号电平的转换上，例如3.3V转2.8V。二极管选用高速肖特基二极管，并且V F尽量小，例如RB521S。图1 B ) 图2电路，仅能使用在输入信号电平大于输出信号电平的转换上，例如3.3V转2.8V，否则PNP管可能关不断。如果对输出低电平电压幅度有较严格的要求，PNP管则选用饱和压降小些的管子。PNP管也不如NPN的通用。VCC_OUT是输出信号的电源电压。图2

C ) 图3是NPN管组成的转换电路，对输入和输出电平的谁高谁低没有要求，适用性很好。其中VCC_IN是输入信号的电源电压，VCC_OUT是输出信号的电源电压。转换后输出的低电平VOL=Vin_Lmax+Vsat，Vin_Lmax为输入信号低电平的最高幅值，Vsat为NPN管的饱和压降，如果对输出低电平电压幅度有较严格的要求，NPN管则选用饱和压降小些的管子，以满足一般电路中VOL<0.8V的要求。图3 2.OC/OD输出的反相器组成的电平转换电路。图4，由2级反相器组成，反相器必须是OC/OD输出的。反相器的电源与输入信号的电平相同或者相匹配，最后的输出电平由上拉电阻上拉到输出信号的目标电平上。上拉电阻的取值直接影响功耗和可适用的信号频率。图4

RS232接口芯片双电荷泵电平转换器原理

RS232接口芯片双电荷泵电平转换器原理电子工业协会Electronic Industries Association Electronic Industries Association(EIA)电子工业协会(EIA) 1924年成立的EIA是美国的一个电子制造商组织。 EIA-232，就是众所周知的RS-232，它定义了数据终端设备(DTE)和数据通信设备(DCE)之间的串行连结。这个标准被广泛采用。 EIA-RS-232C电气特性: 在TxD和RxD上：逻辑1=-3V～-15V 逻辑0=+3～＋15V 在RTS、CTS、DSR、DTR和DCD等控制线上：信号有效（接通，ON状态，正电压）＝+3V～+15V 信号无效（断开，OFF状态，负电压)=-3V～-15V RS-232-C电平采用负逻辑，即逻辑1：-3~-15V，逻辑0：+3~+15V。注意，单片机使用的CMOS电平中，高电平（3.5~5V）为逻辑1，低电平（0~0.8V）为逻辑0。单片机的SCI口要外接电平转换电路芯片把与TTL兼容的CMOS高电平表示的1转换成RS-232的负电压信号，把低电平转换成RS-232的正电压信号。典型的转换电路给出-9V和+9V。

典型的电平转换电路MAXx2xx系列芯片因单电源+5V供电，均有电荷泵电平转换器产生±10V电源，以供RS232电平所需。一般是接4个泵电容，采用双电荷泵进行电平转换。标准接法如下图。图1 芯片内带振荡器驱动双电荷泵，分双相四步工作，如下图。图2电荷泵框图

第一步：S1、S3闭合，电源+5V向C1充电（图3）。C1电压最高可至5V。图3 第二步：S2、S4闭合，C1所储电荷经S2、S4转移至C3，C3电压最高也可至5V。 C1电荷转移充电途径如红色虚线所示。 C3电压和电源+5V迭加起来提供10V的V+电源。这时C1负端电位应等于电源+5V，所以C1负端电压波形应是0-+5V 的方波。第三步：S5、S7闭合，C3所储电荷和电源+5V迭加经S5、S7向C2充电。 C2电压最高可至10V。充电途径如棕色虚线所示。第二、三步实际同时进行（图4）。

3.3V转5V的双向电平转换电路

3.3V转5V的双向电平转换电路说说所有的电平转换方法，你自己参考～ (1) 晶体管+上拉电阻法就是一个双极型三极管或MOSFET，C/D极接一个上拉电阻到正电源，输入电平很灵活，输出电平大致就是正电源电平。 (2) OC/OD 器件+上拉电阻法跟1) 类似。适用于器件输出刚好为OC/OD 的场合。 (3) 74xHCT系列芯片升压(3.3V→5V) 凡是输入与5V TTL 电平兼容的5V CMOS 器件都可以用作3.3V→5V 电平转换。 ——这是由于3.3V CMOS 的电平刚好和5V TTL电平兼容（巧合），而CMOS 的输出电平总是接近电源电平的。廉价的选择如74xHCT(HCT/AHCT/VHCT/AHCT1G/VHCT1G/...) 系列(那个字母 T 就表示TTL 兼容)。 (4) 超限输入降压法(5V→3.3V, 3.3V→1.8V, ...) 凡是允许输入电平超过电源的逻辑器件，都可以用作降低电平。这里的"超限"是指超过电源，许多较古老的器件都不允许输入电压超过电源，但越来越多的新器件取消了这个限制(改变了输入级保护电路)。例如，74AHC/VHC 系列芯片，其datasheets 明确注明"输入电压范围为0~5.5V"，如果采用3.3V 供电，就可以实现5V→3.3V 电平转换。 (5) 专用电平转换芯片最著名的就是164245，不仅可以用作升压/降压，而且允许两边电源不同步。这是最通用的电平转换方案，但是也是很昂贵的(俺前不久买还是￥45/片，虽是零售，也贵的吓人)，因此若非必要，最好用前两个方案。 (6) 电阻分压法最简单的降低电平的方法。5V电平，经1.6k+3.3k电阻分压，就是3.3V。 (7) 限流电阻法如果嫌上面的两个电阻太多，有时还可以只串联一个限流电阻。某些芯片虽然原则上不允许输入电平超过电源，但只要串联一个限流电阻，保证输入保护电流不超过极限(如74HC 系列为20mA)，仍然是安全的。 (8) 无为而无不为法只要掌握了电平兼容的规律。某些场合，根本就不需要特别的转换。例如，电路中用到了某种5V 逻辑器件，其输入是3.3V 电平，只要在选择器件时选择输入为TTL 兼容的，就不需要任何转换，这相当于隐含适用了方法3)。 (9) 比较器法算是凑数，有人提出用这个而已，还有什么运放法就太恶搞了。那位说的可以～但我分析你也不是非要芯片不可吧？尽量节约成本啊～ 3.3V转5V 电平转换方法参考电平转换

3.3v和5v双向电平转换芯片

3.3v和5v双向电平转换芯片 74LVC4245，8位电平转换 74LVC4245A,8位双向 NLSX4373，2位电平转换 NLSX4014，4位电平转换 NLSX4378，4位电平转换 NLSX3018，8位电平转换 max3002，8路双向 TXB0104?(她好像有一个系列?0102?0104?0106?0108)， ADG3308 74HCT245：三态输出的八路总线收发器 SN74AVCH2T45 SN74AVC16T245：具有可配置电压转换和3 态输出的16 位双电源总线收发器 SN74LVC2T45DCT：双位双电源总线收发器可配置电压转换和三态输出 SN74LVC4245A：8位德州仪器宣布推出SN74LVC1T45、SN74LVC2T45、SN74AVC8T245及SN74AVC20T245四款新型双电源电平转换收发器。该新品能够在 1.5V、1.8V、2.5V、3.3V 与5V 电压节点之间进行灵活的双向电平转换，而且可提供全面的可配置性。如果采用AVC 技术，则每条轨可从 1.4V 配置为 3.6V；而采用LVC 技术时则可从1.65V 配置为5.5V。适用于便携式消费类电子产品、网络、数据通信以及计算应用领域。日前，德州仪器(TI)宣布推出四款新型的双电源电平转换器--AVC1T45、AVC2T45、AVC16T245及AVC32T245，从而进一步扩展其电平转换产品系列。这些转换器能够在互不兼容的I/O之间进行通信。这四款器件均支持1.2V、1.5V、1.8V、2.5V与3.3V节点之间的双向电平转换。在混合信号环境中，可以使用这些电压电平的任意组合，从而提高这些器件的灵活性。 1位AVC1T45与2位AVC2T45可根据需要在电路板上集成单或双转换器功能，而不是通过较高位宽的器件进行路由，这有助于简化电路板布线作业(board routing)，可适用于便携式手持应用的转换要求。AVC16T245与AVC32T245是TI当前16位与32位双电源转换功能的改进版本。这些器件能够提供较低的功耗(AVC16T245的功耗为25μA，而AVCA164245的功耗则为40μA)。该类器件的总线控制选件无需外部上拉/下拉电阻器。TI还提供全面的IBIS模型支持。 SN74AVC1T45与SN74AVC2T45以及总线控制版本SN74AVCH1T45与SN74AVCH2T45均采用NanoStar 与NanoFree芯片级封装。这些器件现已推出，并可提供样片。批量为千套时，预计1T45器件的最低零售单价为0.24美元，而2T45器件的最低零售单价为0.35美元。 SN74AVC16T245和总线控制版本SN74AVCH16T245采用56球栅VFBGA封装。该器件现已推出，并可提

逻辑电平转换器

逻辑电平转换器在新一代电子产品设计中，TTL或5V CMOS电平已不再占据逻辑电路统治地位。随着低电压逻辑的引入，系统内部常常出现输入/输出逻辑不协调的问题，从而提高了系统设计的复杂性。例如，当1.8V的数字电路与工作在3.3V的模拟电路进行通信时，需要首先解决两种电平转换问题，本文介绍了不同逻辑电平之间的转换方法。 1 逻辑电平转换的必要性型号I/O通道数单向/双向 Rx/Tx V L范围Vcc范围独立使能速率 MAX3001 8 双向，8/8 1.2V～5.5V 1.65V～5.5V Yes 4Mbps MAX3370 1 双向，1/1 1.65V～ 5.5V 2.5V～5.5V No 2Mbps MAX3371 1 双向，1/1 1.65V～ 5.5V 2.5V～5.5V Yes 2Mbps MAX3372/3 2 双向，2/2 1.2～5.5V 1.65V～5.5V Yes 230kbps MAX3374 MAX3375 MAX3376 2 单向，2/0 单向，1/1 单向，0/2 1.2～5.5V 1.65V～5.5V Yes 16Mbps MAX3377 MAX3378 4 双向，4/4 1.2～5.5V 1.65V～5.5V Yes 230kbps MAX3379 4 单向，4/0 1.2～5.5V 1.65V～5.5V Yes 16Mbps MAX3390 4 单向，3/1 1.2～5.5V 1.65V～5.5V Yes 16Mbps MAX3391 4 单向，2/2 1.2～5.5V 1.65V～5.5V Yes 16Mbps MAX3392 4 单向，1/3 1.2～5.5V 1.65V～5.5V Yes 16Mbps MAX3393 4 单向，0/4 1.2～5.5V 1.65V～5.5V Yes 16Mbps 随着不同工作电压的数字IC的不断涌现，逻辑电平转换的必要性更加突出，电平转换方式也将随逻辑电压、数据总线的形式(例如4线SPI、32位并行数据总线等)以及数据传输速率的不同而改变。现在虽然许多逻辑芯片都能实现较高的逻辑电平至较低逻辑电平的转换(如将5V电平转换至3V电平)，但极少有逻辑电路芯片能够较低的逻辑电平转换成较高的逻辑电平(如将3V逻辑转换至5V逻辑)。另外，电平转换器虽然也可以用晶体管甚至电阻——二极管的组合来实现，但因受寄生电容的影响，这些方法大大限制了数据的传输速率。

电平转换资料

74AVC1T145 1、概述 74AVC1T145是一款具有双向电压转换和3态输出的单位双电源收发器。它的功能端口有1位输入输出端口（A和B），一个方向控制输入（DIR）和双电源引脚（V CC(A)和V CC(B)）。同时V CC(A)和V CC(B)可以输入介于0.8 V 到3.6 V的电压实现器件在任意低电压节点之间的转换（0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V 和3.3 V）。引脚A和DIR由V CC(A)供电，引脚B由V CC(B)供电。在DIR上的高电平允许从A传输到B，也允许在DIR上的低电平从B传输到A。该器件明确规定在局部省电模式时使用I OFF。I OFF将使输出失能，防止在电源关闭时破坏性的回路电流通过器件。当VCC(A)或VCC(B)处于地电平电压时处于挂起模式，同时A和B 将处于高阻态。 2、功能与优点 ?电源电压范围宽： ◆ ◆ ?噪声抑制能力强 ?符合JEDEC标准： ◆-12 (0.8 V to 1.3 V) ◆-11 (0.9 V to 1.65 V) ◆-7 (1.2 V to 1.95 V) ◆-5 (1.8 V to 2.7 V) ◆-B (2.7 V to 3.6 V) ?静电保护： ◆HBM JESD22-A114E类3 b超过8000 V ◆MM JESD22-A115-A超过200 V ◆CDM JESD22-C101C超过1000 V ?最大数据速率： ◆500 Mbit / s(1.8 V至3.3 V的转换) ◆320 Mbit / s(< 1.8 V至3.3 V转换) ◆320 Mbit / s(转换为2.5 V和2.5 V) ◆280 Mbit / s(转换到1.5 V) ◆240 Mbit / s(转换到1.2 V) 挂起模式或睡眠模式； ?锁存性能超过100 mA / JESD 100 II级 ?输入接受电压最高达3.6 V ?低噪声时过冲和欠冲小于VCC的10% ?I OFF电流提供部分省电模式操作 ?多种封装选择 ?指定使用温度范围从-40°C到+ 85°C和?40°C到+ 125°C 3、订购信息（略） 4、标记（略） 5、逻辑图

CMOS电平转换电路详解

CMOS电平转换电路详解 COMS集成电路是互补对称金属氧化物半导体（Compiementary symmetry metal oxide semicoductor）集成电路的英文缩写，电路的许多基本逻辑单元都是用增强型PMOS晶体管和增强型NMOS管按照互补对称形式连接的，静态功耗很小。 COMS电路的供电电压VDD范围比较广在+5~+15V均能正常工作，电压波动允许10，当输出电压高于VDD-0.5V时为逻辑1，输出电压低于VSS+0.5V（VSS为数字地）为逻辑0。CMOS电路输出高电平约为0.9Vcc，而输出低电平约为0.1Vcc.当输入电压高于VDD-1.5V时为逻辑1，输入电压低于VSS+1.5V（VSS为数字地）为逻辑0。 TTL电平信号被利用的最多是因为通常数据表示采用二进制规定，+5V等价于逻辑1，0V 等价于逻辑0，这被称做TTL（晶体管-晶体管逻辑电平）信号系统，这是计算机处理器控制的设备内部各部分之间通信的标准技术。标准TTL输入高电平最小2V，输出高电平最小2.4V，典型值3.4V，输入低电平最大0.8V，输出低电平最大0.4V，典型值0.2V（输入H》2V，输入L《0.8V;输出H 》2.4V（3.4V），输出L《0.4V（0.2V）。 CMOS电平是数字信号还是模拟信号？CMOS电平是数字信号，COMS电路的供电电压VDD范围比较广在+5--+15V均能正常工作，电压波动允许10，当输出电压高于VDD-0.5V 时为逻辑1，输出电压低于VSS+0.5V（VSS为数字地）为逻辑0，一般数字信号才是0和1 。 cmos电平转换电路1、TTL电路和CMOS电路的逻辑电平 VOH：逻辑电平1 的输出电压 VOL：逻辑电平0 的输出电压 VIH ：逻辑电平1 的输入电压 VIH ：逻辑电平0 的输入电压 TTL电路临界值：

5V到3V3的电平转换-串口通信

5V到3V3的电平转换-串口通信一、电平转换电路下面来分析一下电路的设计思路： https://www.360docs.net/doc/6611045413.html,/BLOG_ARTICLE_244240.HTM 首先声明一下：这个电路是从3V3的角度考虑的！ 1、接收通道我们首先来明确一下数据流向（其实就是电平驱动方向），接收通道是由5V方驱动的（Source），3V3方只是取电平（Sink），因此TXD5V作为此通道的输入方，RXD3V3作为通道的输出方。我们知道，三极管（开关型）集电极输出驱动能力不错，我们就设计为集电极输出；但是，只有一个三极管是不行的，因为集电极输出的时候，基极电平和集电极逻辑是相反的；那么，加一个反相器？没必要，那是另外一种电平转换的方法了，我们只需要再使用一个三极管，基极接前级输出就可以了。这样，逻辑转换就完成了，当输入低电平时，Q1截止，集电极输出高电平，Q2导通，集电极输出低电平。同理，高电平分析是一样的。逻辑转换完成了，那么就是电平的问题了。这很好解决，输入方为5V逻辑，那么就给它一个VCC5，3V3逻辑高电平需要一个3V3，那么就给一个VCC3V3；OK！ 2、发送通道分析完接收通道，发送通道的原理其实也是一样的，就不详细介绍了。 3、结论其实如果稍微熟悉电子电路知识的人看来，这个电路实在太简单，正因为如此，我才要强调，基础很重要！否则，一个系统的设计会在这些小地方卡住。二、电平问题：单片机手册————电气特性常用逻辑电平：12V，5V，3.3V； 1.TTL电平：输出高电平>2.4V,输出低电平<0.4V。在室温下，一般输出高电平是3.5V，输出低电平是0.2V。最小输入高电平和低电平：输入高电平>=2.0V，输入低电平<=0.8V，噪声容限是0.4V。

电平转换方法

常用的电平转换方案 (1) 晶体管+上拉电阻法就是一个双极型三极管或 MOSFET，C/D极接一个上拉电阻到正电源，输入电平很灵活，输出电平大致就是正电源电平。 (2) OC/OD 器件+上拉电阻法跟 1) 类似。适用于器件输出刚好为 OC/OD 的场合。 (3) 74xHCT系列芯片升压 (3.3V→5V) 凡是输入与 5V TTL 电平兼容的 5V CMOS 器件都可以用作 3.3V→5V 电平转换。 ——这是由于 3.3V CMOS 的电平刚好和5V TTL电平兼容（巧合），而 CMOS 的输出电平总是接近电源电平的。廉价的选择如 74xHCT(HCT/AHCT/VHCT/AHCT1G/VHCT1G/...) 系列 (那个字母 T 就表示 TTL 兼容)。 (4) 超限输入降压法 (5V→3.3V, 3.3V→1.8V, ...) 凡是允许输入电平超过电源的逻辑器件，都可以用作降低电平。这里的"超限"是指超过电源，许多较古老的器件都不允许输入电压超过电源，但越来越多的新器件取消了这个限制 (改变了输入级保护电路)。例如，74AHC/VHC 系列芯片，其 datasheets 明确注明"输入电压范围为0~5.5V"，如果采用 3.3V 供电，就可以实现 5V→3.3V 电平转换。 (5) 专用电平转换芯片最著名的就是 164245，不仅可以用作升压/降压，而且允许两边电源不同步。这是最通用的电平转换方案，但是也是很昂贵的 (俺前不久买还是￥45/片，虽是零售，也贵的吓人)，因此若非必要，最好用前两个方案。 (6) 电阻分压法最简单的降低电平的方法。5V电平，经1.6k+3.3k电阻分压，就是3.3V。 (7) 限流电阻法如果嫌上面的两个电阻太多，有时还可以只串联一个限流电阻。某些芯片虽然原则上不允许输入电平超过电源，但只要串联一个限流电阻，保证输入保护电流不超过极限(如 74HC 系列为 20mA)，仍然是安全的。 (8) 无为而无不为法只要掌握了电平兼容的规律。某些场合，根本就不需要特别的转换。例如，电路中用到了某种 5V 逻辑器件，其输入是 3.3V 电平，只要在选择器件时选择输入为 TTL 兼容的，就不需要任何转换，这相当于隐含适用了方法3)。 (9) 比较器法

常用数字芯片大全

产品型号规格性能说明型号规格性能说明名称 74LS SN74LSOO四2输入与非门SN74LSO1四2输入与非门 SN74LSO2四2输入与非门SN74LS03四2输入与非门 SN74LS04六反相器SN74LS05六反相器 SN74LS06六反相缓冲器/驱动器SN74LS07六缓冲器/驱动器 SN74LS08四2输入与非门SN74LS09四2输入与非门 SN74LS10三3输入与非门SN74LS11三3输入与非门 SN74LS12三3输入与非门SN74LS13三3输入与非门 SN74LS14六反相器.斯密特触发SN74LS15三3输入与非门 SN74LS16六反相缓冲器/驱动器SN74LS17六反相缓冲器/驱动器 SN74LS20双4输入与门SN74LS21双4输入与门 SN74LS22双4输入与门SN74LS25双4输入与门 SN74LS26四2输入与非门SN74LS27三3输入与非门 SN74LS28四输入端或非缓冲器SN74LS30八输入端与非门 SN74LS32四2输入或门SN74LS33四2输入或门 SN74LS37四输入端与非缓冲器SN74LS38双2输入与非缓冲器 SN74LS40四输入端与非缓冲器SN74LS42BCD－十进制译码器 SN74LS47BCD－七段译码驱动器SN74LS48BCD－七段译码驱动器SN74LS49BCD－七段译码驱动器SN74LS51三3输入双与或非门 SN74LS54四输入与或非门SN74LS55四4输入与或非门 SN74LS63六电流读出接口门SN74LS73双J－K触发器 SN74LS74双D触发器SN74LS754位双稳锁存器 SN74LS76双J－K触发器SN74LS78双J－K触发器 SN74LS83双J－K触发器SN74LS854位幅度比较器 SN74LS86四2输入异或门SN74LS884位全加器 SN74LS904位十进制波动计数器SN74LS918位移位寄存器 SN74LS9212分频计数器SN74LS93二进制计数器 SN74LS965位移位寄存器SN74LS954位并入并出寄存器 SN74LS109正沿触发双J－K触发器SN74LS107双J－K触发器 SN74LS113双J－K负沿触发器SN74LS112双J－K负沿触发器 SN74LS121单稳态多谐振荡器SN74LS114双J－K负沿触发器 SN74LS123双稳态多谐振荡器SN74LS122单稳态多谐振荡器 SN74LS125三态缓冲器SN74LS124双压控振荡器 SN74LS1313－8线译码器SN74LS126四3态总线缓冲器 SN74LS13313输入与非门SN74LS132二输入与非触发器 SN74LS137地址锁存3－8线译码器SN74LS136四异或门 SN74LS139双2－4线译码－转换器SN74LS1383－8线译码/转换器 SN74LS14710－4线优先编码器SN74LS145BCD十进制译码/驱动器SN74LS153双4选1数据选择器SN74LS1488－3线优先编码器 SN74LS155双2－4线多路分配器SN74LS1518选1数据选择器 SN74LS157四2选1数据选择器SN74LS1544－16线多路分配器 SN74LS160同步BDC十进制计数器SN74LS156双2－4线多路分配器

【CN109687862A】一种双向电平转换电路和双向电平转换芯片【专利】

(19)中华人民共和国国家知识产权局 (12)发明专利申请 (10)申请公布号 (43)申请公布日 (21)申请号 201910115541.1 (22)申请日 2019.02.14 (71)申请人上海艾为电子技术股份有限公司地址 201199 上海市闵行区秀文路908弄2 号1201室 (72)发明人董渊　王云松　黄建刚　程剑涛　孙洪军　 (74)专利代理机构北京集佳知识产权代理有限公司 11227 代理人王宝筠 (51)Int.Cl. H03K 19/0175(2006.01) (54)发明名称一种双向电平转换电路和双向电平转换芯片 (57)摘要本发明提供了一种双向电平转换电路和双向电平转换芯片，包括信号传输管、第一上拉管、第二上拉管和上拉控制模块；第一上拉管的第一端与第一电压端电连接、第二端与信号传输管的第一端电连接，第二上拉管的第一端与第二电压端电连接、第二端与信号传输管的第二端电连接；上拉控制模块的第一信号输入端与信号传输管的第一端电连接、第二信号输入端与信号传输管的第二端电连接、输出端与第一上拉管和第二上拉管的栅极电连接，用于在信号传输管的第一端和第二端中任一端由第一电平翻转为第二电平时，输出第一电平脉冲。本发明中两个上拉管由一个上拉控制模块控制，从而不仅可以减少模块数量和设计复杂度，而且可以减小芯片面积和成本。权利要求书2页说明书7页附图3页CN 109687862 A 2019.04.26 C N 109687862 A

权　利　要　求　书1/2页CN 109687862 A 1.一种双向电平转换电路，其特征在于，包括信号传输管、第一上拉管、第二上拉管和上拉控制模块；所述第一上拉管的第一端与第一电压端电连接，所述第一上拉管的第二端与所述信号传输管的第一端电连接，所述第二上拉管的第一端与第二电压端电连接，所述第二上拉管的第二端与所述信号传输管的第二端电连接；所述上拉控制模块的第一信号输入端与所述信号传输管的第一端电连接，所述上拉控制模块的第二信号输入端与所述信号传输管的第二端电连接，所述上拉控制模块的输出端与所述第一上拉管和所述第二上拉管的栅极电连接；所述上拉控制模块用于在所述信号传输管的第一端和第二端中任一端由第一电平翻转为第二电平时，输出第一电平脉冲，控制所述第一上拉管和所述第二上拉管导通，将所述第一端和第二端中另一端由第一电平拉为第二电平。 2.根据权利要求1所述的电路，其特征在于，所述上拉控制模块包括第一信号输入端、第二信号输入端、端口检测模块、双向检测触发模块和单脉冲产生模块；所述端口检测模块与所述第一信号输入端和所述第二信号输入端电连接，用于在所述第一信号输入端和所述第二信号输入端都为第二电平时，输出第一电平，在所述第一信号输入端和所述第二信号输入端中至少一端为第一电平时，输出第二电平；所述双向检测触发模块与所述第一信号输入端和所述第二信号输入端电连接，用于在所述第一信号输入端和所述第二信号输入端都为第一电平时，输出第二电平，在所述第一信号输入端和所述第二信号输入端中至少一端为第二电平时，输出第一电平；所述单脉冲产生模块与所述端口检测模块和所述双向检测触发模块电连接，用于在所述端口检测模块输出第二电平、所述双向检测触发模块的输出由第二电平转换为第一电平时，输出第一电平脉冲，在其他时段输出第二电平。 3.根据权利要求2所述的电路，其特征在于，所述端口检测模块包括与非门和第一反相器至第四反相器；所述第一反相器的输入端与所述第一信号输入端电连接，所述第二反相器的输入端与所述第一反相器的输出端电连接，所述第二反相器的输出端与所述与非门的一个输入端电连接；所述第三反相器的输入端与所述第二信号输入端电连接，所述第四反相器的输入端与所述第三反相器的输出端电连接，所述第四反相器的输出端与所述与非门的另一个输入端电连接；所述与非门的输出端与所述端口检测模块的输出端电连接。 4.根据权利要求3所述的电路，其特征在于，所述双向检测触发模块包括或门、第一晶体管至第五晶体管、第五反相器和第六反相器；所述或门的一个输入端与所述第一信号输入端电连接，所述或门的另一个输入端与所述第二信号输入端电连接，所述或门的输出端与所述第一晶体管的栅极电连接；所述第一晶体管的第一端与所述第二晶体管的第二端电连接，所述第二晶体管的第一端与电源端电连接，所述第一晶体管的第二端与第三晶体管的第二端电连接，所述第三晶体管的栅极与所述第一信号输入端电连接，所述第三晶体管的第一端与接地端电连接；所述第一晶体管的第二端与第四晶体管的第二端电连接，所述第四晶体管的第二端通 2

txs0102 电平转换芯片

FEATURES DCT OR DCU PACKAGE (TOP VIEW)1B1827V CCB 36OE 45B2GND V CCA A2A1YZP PACKAGE (BOTTOM VIEW)A254A136OE V CCA 27V CCB GND 8B1 1B2A1B1C1D1A2B2C2D2DESCRIPTION/ORDERING INFORMATION https://www.360docs.net/doc/6611045413.html, .......................................................................................................................................................SCES640A–JANUARY 2007–REVISED MAY 2008 2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN AND PUSH-PULL APPLICATIONS ?No Direction-Control Signal Needed ?ESD Protection Exceeds JESD 22 ?Max Data Rates –A Port –24Mbps (Push Pull)–2500-V Human-Body Model (A114-B) –2Mbps (Open Drain)–250-V Machine Model (A115-A) ?Available in the Texas Instruments NanoFree?–1500-V Charged-Device Model (C101) Package –B Port ? 1.65V to 3.6V on A port and 2.3V to 5.5V on –8-kV Human-Body Model (A114-B) B port (V CCA ≤V CCB )–250-V Machine Model (A115-A) ?V CC Isolation Feature –If Either V CC Input Is at –1500-V Charged-Device Model (C101) GND,Both Ports Are in the High-Impedance State ?No Power-Supply Sequencing Required – Either V CCA or V CCB Can Be Ramped First ?I off Supports Partial-Power-Down Mode Operation ?Latch-Up Performance Exceeds 100mA Per JESD 78,Class II This two-bit noninverting translator uses two separate configurable power-supply rails.The A port is designed to track V CCA .V CCA accepts any supply voltage from 1.65V to 3.6V.The B port is designed to track V CCB .V CCA must be less than or equal to V CCB .V CCB accepts any supply voltage from 2.3V to 5.5V.This allows for low-voltage bidirectional translation between any of the 1.8-V,2.5-V,3.3-V,and 5-V voltage nodes. When the output-enable (OE)input is low,all outputs are placed in the high-impedance state. To ensure the high-impedance state during power up or power down,OE should be tied to GND through a pulldown resistor;the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INFORMATION T A PACKAGE (1)(2) ORDERABLE PART NUMBER TOP-SIDE MARKING (3)NanoStar?–WCSP (DSBGA) Reel of 3000TXS0102YZPR 2H_0.23-mm Large Bump –YZP Reel of 3000TXS0102DCTR NFEZ___–40°C to 85°C SSOP –DCT Tube of 250TXS0102DCTT NFEZ ___VSSOP –DCU Reel of 3000TXS0102DCUR NFE_(1) Package drawings,thermal data,and symbolization are available at https://www.360docs.net/doc/6611045413.html,/packaging .(2) For the most current package and ordering information,see the at the end of this document,or see the TI website at https://www.360docs.net/doc/6611045413.html, .(3)DCT:The marking has three additional characters that designate the year,month,and assembly/test site. DCU:The actual top-side marking has one additional character that designates the assembly/test site. YZP:The actual top-side marking has three preceding characters to denote year,month,and sequence code,and one following character to designate the assembly/test site.Pin 1identifier indicates solder-bump composition (1=SnPb,?=Pb-free). Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.