用VHDL设计奇偶校验器

本例为对八位输入数据和其奇偶校验位进行校验，输出正确的奇偶校验位。

IN_READY输入表示输入已准备好；OUT_REQ输入表示输出请求；CLK输入表示输入时钟；

当OUT_READY输出表示输出准备好，可以为下级电路使用；

源代码如下：

package types is

subtype short is integer range0 to255;

end types;

use work.types.all;

entity parity is

port(

CLK:in bit;

IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7:in bit;

EVEN_IN,ODD_IN:in bit;

IN_READY:in bit;

OUT_REQ:in bit;

OUT_READY:out bit;

EVEN_OUT:out bit;

ODD_OUT:out bit;

);

end parity;

architecture algorithm of parity is

begin

process

variable cond:boolean:=true;

variable count:short;

begin

wait until(CLK'event and CLK='1' and IN_READY='1');

if(EVEN_IN=ODD_IN) then --奇偶校验预判断

cond:=false;

end if;

count:=0;

if IN0='1' then

count:=count+1;

end if;

if IN1='1' then

count:=count+1;

end if;

if IN2='1' then

count:=count+1;

end if;

if IN3='1' then

count:=count+1;

end if;

if IN4='1' then

count:=count+1;

end if;

if IN5='1' then

count:=count+1;

end if;

if IN6='1' then

count:=count+1;

end if;

if IN7='1' then

count:=count+1;

end if;

--判断输入数据中1的个数的奇偶

while count>1 loop

count:=count-2;

end loop;

--判断奇偶校验位的正确性

if count=1 and ODD_IN='0' then

cond:=false;

end if;

if count=0 and EVEN_IN='0' then

cond:=false;

end if;

--输出奇偶校验位

if count=1 then

EVEN_OUT<='0';

ODD_OUT<='1';

else

EVEN_OUT<='1';

ODD_OUT<='0';

end if;

--同步控制，设置输出控制信息

wait until CLK'event and CLK='1' and OUT_REQ='1'; OUT_READY<='1';

wait until CLK'event and CLK='1' and OUT_REQ='0'; OUT_READY<='0';

--提示出错信息

assert cond

report"EVEN_IN ODD_IN error"

severity warning;

end process;

end algorithm;