Verilog音乐播放器

Verilog 音乐播放器

1、音符对照表

https://www.360docs.net/doc/66549933.html,/link?url=Oax-aXOjWdo-tES0iGNkpxGpVP0OhEL-Xm42W IvqvUhQ6NNAs96MmOyANcHu6FzUhDCWZ1jyBtk2yDCxPSPID750t4zb3JR4Uq htWebECOS

2、顶层结构

3、代码

3.1、顶层代码：

module musicplayer_1 (clk,reset,Q);

input clk;

input reset;

output Q;

//----------------------------------------

wire clk_MHz;

wire clk_4Hz;

wire [5:0]Index;//64ge yinfu

wire [10:0]Tone;//2048

//----------------------------------------

clkMHz u1 (clk,reset,clk_MHz);//bao chi qian hou shun xu yi zhi

clk4Hz u2 (clk,reset,clk_4Hz);

notetab u3 (clk_4Hz,reset,Index);

rom u4 (Index,clk,Tone);

singout u5 (clk_MHz,reset,Tone,Q);

endmodule

3.2、U1代码

module clkMHz (clk,reset,clk_MHz);//bao chi qian hou shun xu yi zhi input clk;

input reset;

output clk_MHz;

//----------------------------------------------

reg [5:0]Q1;

reg clk_MHz_1;

always @ (posedge clk or negedge reset)

begin

if (!reset) Q1<=6'd0;//Asy_rst

else if (Q1<6'd63) Q1<=Q1+1'b1;//0~63 64 circle

else Q1<=5'd0;

end

//------------------------------------------------------------------------ always @ (posedge clk or negedge reset)

begin

if (!reset) clk_MHz_1<=1'b1;//zhi ning

else if (Q1 == 6'd63) clk_MHz_1<=~clk_MHz_1;

end

//------------------------------------------------------------------------- assign clk_MHz=clk_MHz_1;

endmodule

3.3、U2代码

module clk4Hz (clk,reset,clk_4Hz);

input clk;

input reset;

output clk_4Hz;

//--------------------------------------

reg [21:0]Q2;

reg clk_4Hz_1;

always @ (posedge clk or negedge reset)

begin

if (!reset) Q2<=22'd0;//Asy_rst

else if (Q2<22'd2499999) Q2<=Q2+1'b1;//0~9999999 circle

else Q2<=22'd0;

end

//------------------------------------------------------------------------

always @ (posedge clk or negedge reset)

begin

if (!reset) clk_4Hz_1<=1'b1;//zhi ning

else if (Q2 == 22'd2499999) clk_4Hz_1<=~clk_4Hz_1;

end

//-------------------------------------------------------------------------

assign clk_4Hz=clk_4Hz_1;

endmodule

3.4、U3代码module notetab (clk_4Hz,reset,Index);

input clk_4Hz;

input reset;

output [5:0]Index;

//--------------------------------------------

reg [5:0]W;

always @ (posedge clk_4Hz or negedge reset)//sixteen circle

begin

if (!reset) W<=6'd0;

else if (W<6'd63) W<=W+1'b1;//[0-63] sum 64

else W<=6'd0;

end

assign Index = W;

endmodule

3.5、U4代码（通过ROM自动生成，其中标红的部分需要根据自己的实际情况更改）

// megafunction wizard: %ROM: 1-PORT%

// GENERATION: STANDARD

// VERSION: WM1.0

// MODULE: altsyncram

//

============================================================ // File Name: rom.v

// Megafunction Name(s):

// altsyncram

//

// Simulation Library Files(s):

// altera_mf

//

============================================================ // ************************************************************

// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

//

// 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition

// ************************************************************

//Copyright (C) 1991-2011 Altera Corporation

//Your use of Altera Corporation's design tools, logic functions

//and other software and tools, and its AMPP partner logic

//functions, and any output files from any of the foregoing

//(including device programming or simulation files), and any

//associated documentation or information are expressly subject

//to the terms and conditions of the Altera Program License

//Subscription Agreement, Altera MegaCore Function License

//Agreement, or other applicable license agreement, including,

//without limitation, that your use is for the sole purpose of

//programming logic devices manufactured by Altera and sold by

//Altera or its authorized distributors. Please refer to the

//applicable agreement for further details.

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module rom (

Index,

clk,

Tone);

input [5:0] Index;

input clk;

output [10:0] Tone;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_off

`endif

tri1 clk;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_on

`endif

wire [10:0] sub_wire0;

wire [10:0] Tone = sub_wire0[10:0];

altsyncram altsyncram_component (

.address_a (Index),

.clock0 (clk),

.q_a (sub_wire0),

.aclr0 (1'b0),

.aclr1 (1'b0),

.address_b (1'b1),

.addressstall_a (1'b0),

.addressstall_b (1'b0),

.byteena_a (1'b1),

.byteena_b (1'b1),

.clock1 (1'b1),

.clocken0 (1'b1),

.clocken1 (1'b1),

.clocken2 (1'b1),

.clocken3 (1'b1),

.data_a ({11{1'b1}}),

.data_b (1'b1),

.eccstatus (),

.q_b (),

.rden_a (1'b1),

.rden_b (1'b1),

.wren_a (1'b0),

.wren_b (1'b0));

defparam

altsyncram_component.clock_enable_input_a = "BYPASS",

altsyncram_component.clock_enable_output_a = "BYPASS",

altsyncram_component.init_file = "rom.mif",

altsyncram_component.intended_device_family = "Cyclone II",

altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",

altsyncram_component.lpm_type = "altsyncram",

altsyncram_component.numwords_a = 64,

altsyncram_component.operation_mode = "ROM",

altsyncram_component.outdata_aclr_a = "NONE",

altsyncram_component.outdata_reg_a = "CLOCK0",

altsyncram_component.widthad_a = 6,

altsyncram_component.width_a = 11,

altsyncram_component.width_byteena_a = 1;

endmodule

//

============================================================ // CNX file retrieval info

//

============================================================ // Retrieval info: PRIV ATE: ADDRESSSTALL_A NUMERIC "0"

// Retrieval info: PRIV ATE: AclrAddr NUMERIC "0"

// Retrieval info: PRIV ATE: AclrByte NUMERIC "0"

// Retrieval info: PRIV ATE: AclrOutput NUMERIC "0"

// Retrieval info: PRIV ATE: BYTE_ENABLE NUMERIC "0"

// Retrieval info: PRIV ATE: BYTE_SIZE NUMERIC "8"

// Retrieval info: PRIV ATE: BlankMemory NUMERIC "0"

// Retrieval info: PRIV ATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"

// Retrieval info: PRIV ATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"

// Retrieval info: PRIV ATE: Clken NUMERIC "0"

// Retrieval info: PRIV ATE: IMPLEMENT_IN_LES NUMERIC "0"

// Retrieval info: PRIV ATE: INIT_FILE_LAYOUT STRING "PORT_A"

// Retrieval info: PRIV ATE: INIT_TO_SIM_X NUMERIC "0"

// Retrieval info: PRIV ATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: PRIV ATE: JTAG_ENABLED NUMERIC "0"

// Retrieval info: PRIV ATE: JTAG_ID STRING "NONE"

// Retrieval info: PRIV ATE: MAXIMUM_DEPTH NUMERIC "0"

// Retrieval info: PRIV ATE: MIFfilename STRING "rom.mif"

// Retrieval info: PRIV ATE: NUMWORDS_A NUMERIC "64"

// Retrieval info: PRIV ATE: RAM_BLOCK_TYPE NUMERIC "0"

// Retrieval info: PRIV ATE: RegAddr NUMERIC "1"

// Retrieval info: PRIV ATE: RegOutput NUMERIC "1"

// Retrieval info: PRIV ATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

// Retrieval info: PRIV ATE: SingleClock NUMERIC "1"

// Retrieval info: PRIV ATE: UseDQRAM NUMERIC "0"

// Retrieval info: PRIV ATE: WidthAddr NUMERIC "6"

// Retrieval info: PRIV ATE: WidthData NUMERIC "11"

// Retrieval info: PRIV ATE: rden NUMERIC "0"

// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"

// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"

// Retrieval info: CONSTANT: INIT_FILE STRING "rom.mif"

// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

// Retrieval info: CONSTANT: LPM_HINT STRING

"ENABLE_RUNTIME_MOD=NO"

// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"

// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"

// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"

// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"

// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"

// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"

// Retrieval info: CONSTANT: WIDTH_A NUMERIC "11"

// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"

// Retrieval info: USED_PORT: address 0 0 6 0 INPUT NODEFV AL "address[5..0]" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"

// Retrieval info: USED_PORT: q 0 0 11 0 OUTPUT NODEFV AL "q[10..0]"

// Retrieval info: CONNECT: @address_a 0 0 6 0 address 0 0 6 0

// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0

// Retrieval info: CONNECT: q 0 0 11 0 @q_a 0 0 11 0

// Retrieval info: GEN_FILE: TYPE_NORMAL rom.v TRUE

// Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.v FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bb.v TRUE

// Retrieval info: LIB_FILE: altera_mf

3.6、U5代码

module singout (clk_MHz,reset,Tone,Q);

input clk_MHz;

input reset;

input [10:0]Tone;

output Q;

//--------------------------------------

reg [10:0]count;

reg full;

reg count2;

always @ (posedge clk_MHz or negedge reset)

begin

if (!reset) count<=Tone; //fu chuzhi

else if (count==11'b11111111111)

begin

count<=Tone; //centence not only one,must use "begin,end" cover it

full<=1'b1;

end

else if (count<11'b11111111111)

begin

count<=count+1'b1;

full<=1'b0;

end

end

always @ (posedge full or negedge reset) //only jun hen zhan kong bi,not change fen ping ratio

begin

if (!reset) count2<=1'b0;

else count2<=!count2;

end

assign Q=count2;

endmodule

4、Modelsim代码和波形图initial

begin

clk=1;

end

always

begin

#1 clk=!clk;

end

initial

begin

reset=0;

end

always

begin

#2 reset=1;

end