8位奇偶校验位产生电路(forloopendloop实现)

8位奇偶校验位产生电路（forloopendloop实现）

8位奇偶校验位产生电路（for-loop-end loop实现）:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY odd_even IS

PORT( d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

Y：OUT STD_LOGIC

);

END odd_even;

ARCHITECTURE art1 OF odd_even IS

BEGIN

PROCESS(d)

V ARIABLE tmp: STD_LOGIC;

BEGIN

tmp:= '1';

FOR n IN 0 TO 7 LOOP

tmp:= tmp XOR d(n);

END LOOP;

Y<=tmp;

END PROCESS; END art1;