大规模集成电路习题与答案

电路性能：

PROBLEM 1. Consider an isolated 2mm long and 1μm wide M1(Metal1)wire over a silicon substrate driven by an inverter that has zero resistance and parasitic output capccitance. How will the wire delay change for the following cases? Explain your reasoning in each case.

a. If the wire width is doubled.

b. If the wire length is halved.

c. If the wire thickness is double

d.

d. If thickness of the oxide between the M1 and the substrate is doubled. PROBLEM 2. A two-stage buffer is used to drive a metal wire of 1 cm. The first inverter is of minimum size with an input capacitance C i=10 fF and an internal

propagation delay t p0=50 ps and load dependent delay of 5ps/fF. The width of the metal wire is 3.6 μm. The sheet resistance of the metal is 0.08 Ω, the capacitance value is 0.03 fF/μm2 and the fringing field capacitance is

0.04fF/μm.

a. What is the propagation delay of the metal wire?

b. Compute the optimal size of the second inverter. What is the minimum delay through the buffer?

PROBLEM 3. An NMOS transistor is used to charge a large capacitor, as shown the following Figure. The minimum size device, (0.25/0.25) for NMOS and (0.75/0.25) for PMOS, has the on resistance 35 kΩ.

a. Determine the t pLH of this circuit, assuming an ideal step from 0 to 2.5V at the input node.

b. Assume that a resistor R S of 5 kΩ is used to discharge the capacitance to

ground. Determine t pHL.

c. The NMOS transistor is replaced by a PMOS device, sized so that k p is equal to the k n of the original NMOS. Will the resulting structure be faster? Explain why or why not.

PROBLEM 4．The figure below assembles a RTL circuit where the active device is a NMOS transistor which has a resistive load. Assume the switch model behavior of the NMOS transistor. When V in <1.25V, the resistance of the transistor is infinite. When V in ≥1.25V, the transistor can be modeled as having a resistance of 150 ohms.

A. Determine the values for V OH and V OL . Explain your answer.

B. Calculate t pLH and t pHL to obtain the average propagation delay, t p .

Solution:

Vin 50fF

PROBLEM 5. The next figure shows two implementations of MOS inverters. The first inverter uses only NMOS transistors.

a. Calculate V OH, V OL, V th for each case.

b. Find V IH, V IL, N ML and N MH for each inverter and comment on the results. How can you increase the noise margins and reduce the undefined region? 0.25um CMOS工艺(L=Lmin) MOS管参数

Problem 6: We want to design a minimum sized CMOS inverter with 0.25um process( =0.12um). The minimum sized NMOS transistor ’s layers are listed and shown below in Figure below.

A. Determine and list the following:

a. Minimum Transistor Length

b. Minimum Transistor Width

c. Minimum Source/Drain Area

d. Minimum Source/Drain Perimeter

Please list the design rules you come across that lead to your results.

B. We desire the minimum sized CMOS inverter with a symmetrical VTC (V Th =V DD /2) in the 0.25um technology. Calculate the following for the pull-up PMOS transistor in the design.

a. Minimum Transistor Length

b. Minimum Transistor Width

c. Minimum Source/Drain Area

d. Minimum Source/Drain Perimeter

Assume the following:

V DD = 2.5V, and refer to the tables in the below.

C. Using the same minimum size inverter from part B, determine the input capacitance (i.e. the load it presents when driven) and the total load capacitance that the inverter presents.

D. Calculate t pLH and t pHL to obtain the average propagation delay, t p .

Rules are:

i) Poly minimum width = 0.24um

ii) Minimum active width = 0.36um

iii) Minimum contact size = 0.24um*0.24um

iv) Minimum spacing from contact to gate = 0.24um

v) Active enclosure of contact = 0.12um

Answer:

A:

a. L = 0.24um

b. W = 0.48um

c. L drain = 0.24um+0.24um+0.12um = 0.6um

A D =A S = 0.48 * 0.6um = 0.288 um 2

d. P D =P S =0.6um*2+0.48um = 1.68um

B:

2

n T0,Th Th p T0,DD p n R R R p T0,DD n T0,Th V V V V V k k 得出k k 11k 1)V (V V V ???? ??--+==+

?

++=

查表得出一下参数：

V T0p = -0.43V V T0n = 0.4V K n ’=115×10-6 A/V 2 K p ’=30×10-6

A/V 2 另：L=0.24um, W n =0.48um

带入上述公式计算得出：K R =0.965 W p =1.907um

We assume u n =2.5u p and can calculate

a. Lp=0.24μm

b. W p = 1.907 μm

c. A D = 1.907μm *0.6μm =1.1442 μm 2

d. P D = 2*0.6μm +1.2μm =3.107 μm

C:

NMOS:

C gn = C ox L n W n = 0.6912 fF

NMOS 管衬底接0V ，输出从1→0(V 1=-2.5V 变为V 2=-1.25V)：

()()()[]()()()[]

0.615264fF

C C C fF

0.2869940.61281.68K C P C 0.44m 0.61V φV φm)(1V V φK fF 32832057022880K C A C 0.5m 0.57V φV φm)

(1V V φK dbsw db dbn1eqsw j D dbsw m 11bsw m 12bsw 12m bsw eq eq j D db m 11b m 12b 12m b eq =+==??====---?----==??====---?----=----.0侧壁：...底部：

输出从0→1(V 1=0V 变为V 2=-1.25V)：

()()()[]()()()[]

fF

0.836064C C C fF

0.3810240.81281.68K C P C 0.44m 0.81V φV φm)(1V V φK fF 0.455040.7920.288K C A C 0.5m 0.79V φV φm)

(1V V φK dbsw db dbn2eqsw j D dbsw m 11bsw m 12bsw 12m bsw eq eq j D db m 11b m 12b 12m b eq =+==??====---?----==??====---?----=----.0侧壁：底部：

PMOS:

C gp = C ox L p W p ) =2.74608 fF

PMOS 管衬底接2.5V ，输出从1→0(V 1= 0V 变为V 2=-1.25V)：

()()()[]()()()[]

fF

2C C C fF

0.58784440.8622K C P C 0.32m 0.86V φV φm)(1V V φK fF 10.7911K C A C 0.48m 0.79V φV φm)

(1V V φK dbsw db dbp1eqsw j D dbsw m 11bsw m 12bsw 12m bsw eqsw eq j D db m 11b m 12b 12m b eq 3052886..0109.3侧壁：7174442.9.1442.=+==??====---?----==??====---?----=----底部：

输出从0→1(V 1=-1.25V 变为V 2= -2.5V)：

()()()[]()()()[]

fF

1.7614342C C C fF

0.4787860.70.223K C P C 0.32m 0.7V φV φm)(1V V φK fF 10.591.91K C A C 0.48m 0.59V φV φm)

(1V V φK dbsw db dbp2eqsw j D dbsw m 11bsw m 12bsw 12m bsw eqsw eq j D db m 11b m 12b 12m b eq =+==??====---?----==??====---?----=----109.侧壁：2826482.1442.底部：

如果m 以0.5计算：

NMOS 管衬底接0V ，输出从1→0(V 1=-2.5V 变为V 2=-1.25V)：

()()()[]

0.596448fF

C C C fF

0.268120.57281.68K C P C fF 32832057022880K C A C 0.57V φV φm)

(1V V φK K dbsw db dbn1eqsw j D dbsw eq j D db m 11b m 12b 12m b eqsw eq =+==??===??===---?----==--.0...底部： 输出从0→1(V 1=0V 变为V 2=-1.25V)：

()()()[]

fF

0.826656C C C fF

0.3716160.79281.68K C P C fF

0.455040.7920.288K C A C 0.79V φV φm)(1V V φK K dbsw db dbn2eqsw j D dbsw eq j D db m 11b m 12b 12m b eqsw eq =+==??===??===---?----==--.0底部：

PMOS 管衬底接2.5V ，输出从1→0(V 1= 0V 变为V 2=-1.25V)：

()()()[]

fF 2C C C fF

0.54034420.7922K C P C fF

1.71744420.79911K C A C 0.79V φV φm)(1V V φK K dbsw db dbp1eqsw j D dbsw eq j D db m 11b m 12b 12m b eqsw eq 2577884..0109.3.144

2.=+==??===??===---?----==--底部：

输出从0→1(V 1=-1.25V 变为V 2= -2.5V)：

()()()[]

fF 1.6290372C C C fF

0.38986860.570.22K C P C fF

10.571.91K C A C 0.57V φV φm)(1V V φK K dbsw db dbp2eqsw j D dbsw eq j D db m 11b m 12b 12m b eqsw eq =+==??===??===---?----==--109.32391686.1442.底部：

D ：

C load 计算：

C load =C wire +C g +C gd,n +C gd,p +C db,n +C db,p≈C g +C db,n +C db,p

C g = C gn + C gp =0.6912+2.74608=3.43728 fF

输出从1→0(V 1= 0V 变为V 2=-1.25V)：

C load≈C g +C db,n +C db,p =6.3578326 fF

16.32ps

1V )V 4(V ln V V 2V )V (V k C A/V 10230k L W k DD T0n DD T0n DD T0n T0n DD n load PHL 2

6'n n

n n =??

???????? ??--+--=?=?=-τ 输出从0→1(V 1=-1.25V 变为V 2= -2.5V)：

C load≈C g +C db,n +C db,p =6.0347782 fF

15.33ps 1V )V 4(V ln V V V 2)V (V k C A/V 10238.375k L W k DD T0p DD T0p

DD T0p T0p

DD p load PLH 26'p p p p =???????? ??--+????--=?=?=

-τ

如果以m=0.5，则：

输出从1→0(V 1= 0V 变为V 2=-1.25V)：

C load≈C g +C db,n +C db,p =6.2915162 fF

16.147ps

1V )V 4(V ln V V 2V )V (V k C DD T0n DD T0n DD T0n T0n DD n load PHL =??

???????? ??--+--=τ 输出从0→1(V 1=-1.25V 变为V 2= -2.5V)：

C load≈C g +C db,n +C db,p =5.8929732 fF

ps 1V )V 4(V ln V V V 2)V (V k C DD T0p DD T0p DD T0p T0p

DD p load PLH 97.14=???

????? ??--+????--=τ PROBLEM 7．We want to design a minimum sized CMOS inverter with 0.25um process(λ=0.12um) and desire the inverter with a symmetrical VTC (V Th =V DD /2) . The minimum sized NMOS transistor’s layers are shown as problem 6. Assume the following:

V DD = 2.5V, and refer to the tables in the below.

A. Determine the input capacitance (i.e. the load it presents when driven) and the total load capacitance that the inverter presents.

B. Calculate t pLH and t pHL to obtain the average propagation delay, t p .

PROBLEM 8. Sizing a chain of inverters.

a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with input capacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown in the following figure. Assume that the propagation delay of a minimum size inverter is 70 ps. Also assumethat the input capacitance of a gate is proportional to its size. Determine the sizing of the two additional buffer stages that will minimize the propagation delay.

b. If you could add any number of stages to achieve the minimum delay, how many stages would you insert?What is the propagation delay in this case?

c. Describe the advantages and disadvantages of the methods shown in (a) and (b).

PROBLEM 9. Consider a CMOS inverter with the following parameters:

V T0,n=1.0V V T0,p=-1.2V μn C ox=45uA/V2

μp C ox=25uA/V2 (W/L)n=10 (W/L)p=20

The power supply voltage is 5V, and the output load capacitance is 1.5pF.

a. Calculate the rise time and the fall time of the output signal using average current method.

b. Determine the maximum frequency of a periodic square-wave input signal so that the output voltage can still exhibit a full logic swing from 0V to 5V in each cycle.

c. Calculate the dynamic power dissipation at this frequency.

d. Assume that the output load capacitance is mainly dominated by fixed

fan-out component( which are independent of W n and W p). We want to

re-design the inverter so that the propagation delay times are reduced by 25%. Determine the required channel dimensions of the nMOS and the pMOS transistors. How does this re-design influence the switching (inversion) threshold?

PROBLEM 10. Consider the following low swing driver consisting of NMOS devi ces M1 and M2. Assume that the inputs IN and IN’ have a 0V to 2.5V swing and that V IN = 0V when V IN’ = 2.5V and vice-versa. Also assume that

there is no skew between IN and IN’ (i.e., the inverter delay to derive IN from IN is zero).

a. What voltage is the bulk terminal of M2 connected to?

b. What is the voltage swing on the output node as the inputs swing from 0V to

2.5V. Show the low value and the high value.

c. Assume that the inputs IN and IN have zero rise and fall times. Assume a zero skew between IN and IN’. Determine the low to high propagation delay for charging the output node measured from the the 50% point of the input to the 50% point of the output. Assume that the total load capacitance is 1pF, including the transistor parasitics.

MOS管参数参照题4。

Logic Styles:

Problem 1: Consider the circuit of following.

a. What is the logic function implemented by the CMOS transistor network? Size the NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 4 and PMOS W/L = 8. Solution:

b. What are the input patterns that give the worst case t pHL and t pLH. State clearly what are the initial input patterns and which input(s) has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes.

Solution:

The worst case t pHL happens when the internal node capacitances (Cx2 and Cx3) are charged before the high to low transition. The initial states that can cause this are: ABCD=[1010, 1110, 0110]. The final state is one of: ABCD=[1011, 0111].

The worst case t pLH happens when Cx1 is discharged before the low to high transition. The input pattern that can cause this is: ABCD=[0111] =>[0011]. Problem 2: A complex logic gate is shown in the following.

a. Write the Boolean equations for outputs F and G. What function does this circuit implement?

Solution: B

F+

=

=

A

+

A

A

B

AB

G

B

b. What logic family does this circuit belong to?

Solution: CVSL

Problem 3: Logic Styles

a. What is the function of the circuit in this figure ?

Solution:

??

b) What is the logic function performed by the dynamic gate shown below?

Solution: B A out +=

c) What is the logic function of the following Dynamic gate?

Solution: )(C B A Y +=

d) What is the logic function of the following CPL gate?

Solution: A B C D Q A B C D Q ==

Problem 4: Logic Styles a) Implement the function D)E (C AB F ++= with a complex static

CMOS gate. You should arrange your gate to minimize the delay from the E input, and so that the worst-case pull up resistance is equal to the worst-case pulldown resistance.

Solution: 不只一种答案

b) Design a 4 input multiplexer (see the truth-table below for its fuction) in the complementary pass-transistor logic style using a minimum number of transistors.

Solution:

Problem 5: Sequential circuits.

a) Would the sequential circuit from the figure above be considered a latch, a master-slave latch pair or a pulse-triggered latch? Briefly explain your answer. Solution:

b) Draw the timing waveforms for this circuit.

c) Redesign this circuit, such that it also implements an OR function of the inputs.

Problem 6: Sequential circuits.

a) Would the sequential circuit from the figure above be considered a latch, a master-slave latch pair or a pulse-triggered latch? Briefly explain your answer.

b) All transistors in this circuit are unit-sized, with equivalent resistances R and gate capacitances C (ignore diffusion capacitances). Calculate the propagation delay t Clk-Q for high-to-low and low-to-high transitions. Load on the output Q is equal 12C. Ignore the signal slopes in delay calculation.

Solution: A pulse-triggered latch

Problem 7: Sequential Elements

In this problem we will be examining the latch shown below, which has been implemented out of a tri-state inverter. Throughout this problem, you can assume that V DD = 2.5V, C G= 2fF/μm, C D= 2fF/μm,

and R sqn = R sqp/2 = 15k?/□.

a) Assuming the latch is ideal (i.e., has no delay,zero setup/hold time, etc),fill in the wave for Q given the clock and inputs shown below.

Solution:

b) For C L=50fF and assuming Q is initially charged to V DD and y is initially 0V, what is the t clk-q of this latch when D=1? You should assume that clk is a ramp. Solution: t clk-q=232.5ps

c) One of your fellow designers comes to you one day and says that when she used this latch in her circuit with C L = 5fF, the latch failed to function correctly. More specifically, if D transitioned, the inverter receiving the output of the latch would transition even when clk was low. However, you have verified that the latch functions correctly when C L = 50fF. What is the cause of the error when the latch has a small C L? (Hint: Think about the second transition of D) Solution: Charge share

d) What is the minimum load capacitance required for the latch to function correctly? You can assume that the inverter receiving the output of the latch has an ideal VTC with a switch point V th = V DD/2, and that none of the transistors’ source/drain regions have been shared.

Solution: C L>12fF

e) Other than artificially increasing C L, how can you modify the latch to fix the problem you identified in part c)? You should explain your fix and draw a

new transistor-level schematic of the latch (no sizing necessary). (Note that there is more than one possible fix – you will receive bonus credit for up to two

additional fixes you identify and draw.) Solution:

Problem 8: Sequential Elements

Solution:

Solution:

Design for speed:

Problem 1. A domino buffer is shown above. All transistors are sized at minimum length. The widths of the transistors have been labeled on the diagram. Capacitances can be calculated as 2fF/um. V DD =2.5V. M2M3M1VDD

clk in clk out

2um

2um

1um

PMOS: 4um

NMOS: 1um

a) Find the logical effort of this domino buffer during the evaluation phase. Solution: 9

521==g g G .

b) Assume the output node is connected to a load C L =50fF. Calculate the

delay (during the evaluation phase) from input to output in terms of tp 0, the intrinsic delay of a minimum symmetrically sized inverter.

Solution: 0067.7)(p i i i p p t p f g t t =+=∑

.

c) A keeper PMOS is M4 added to the circuit as shown below. Find the

maximum size of M4 for proper operation of this domino buffer. You can ignore body effect. Use the parameters as below. M2

M3M1VDD

clk in clk out

2um

2um 1um PMOS: 4um NMOS: 1um M4

x

Solution: M1 and M3 are in series. They can be combined into an equivalent 1um wide NMOS transistor. To guarantee the proper operation of this domino buffer, M1 and M3 should be able to pull the intermediate node x below V Tn . (It is also ok if students assume x is pulled below V M of the skewed inverter, though it is safer to pull x below V Tn .) Assume x = V Tn . A current equation can be set up to find out the maximum size of the M4.

m w M μ91.14=.

Problem2. Assume the inverters are implemented in standard CMOS with symmetrical VTC. Furthermore, assume C intrinsic = C gate . Equivalent resistance and input capacitance of unit-sized inverter are R and C , respectively. Sizing factor S ≥ 1.

a. For inverters in Fig. 2a, pick the best sizing factors S 2 and S 3 to minimize propagation delay.

What is the minimum delay (t p 0 is the delay of unit-sized inverter)?

Solution:

S 2 = 3, S 3 = 9 t p = 3t p,stage = 3t p 0·(1 + f opt ) = 12t p 0 (1pt)

b. What is the delay (in terms of t p 0) of the circuit in Fig. 2b?

Solution: t p = 18.4t p 0

c. Assume you can choose the sizing S 2 and S 4 for inverters in Fig. 2c. What are the optimal values for minimum delay? What is the delay (expressed in terms of t p 0)?