奇偶校验电路

发送机代码：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CERTIFICA TION IS

PORT( IN_A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

OUT_A:OUT STD_LOGIC_VECTOR(8 DOWNTO 0) );

END CERTIFICA TION;

ARCHITECTURE ONE OF CERTIFICA TION IS

BEGIN

PROCESS(IN_A)

V ARIABLE A:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

A:="0000";

FOR N IN 0 TO 7 LOOP

IF IN_A(N)='1' THEN

A:=A+1;

END IF;

END LOOP;

OUT_A(8 DOWNTO 1)<=IN_A(7 DOWNTO 0);

OUT_A(0)<=NOT(A(0));

END PROCESS;

END ONE;

接受机代码：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RECEIVE IS

PORT( IN_B: IN STD_LOGIC_VECTOR(8 DOWNTO 0);

OUT_B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

INSTRUCTION:OUT STD_LOGIC

);

END RECEIVE;

ARCHITECTURE ONE OF RECEIVE IS

BEGIN

PROCESS(IN_B)

V ARIABLE A:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

A:="0000";

FOR N IN 0 TO 8 LOOP

IF IN_B(N)='1' THEN

A:=A+1;

END IF;

END LOOP;

OUT_B(7 DOWNTO 0)<=IN_B(8 DOWNTO 1);

IF A(0)='1' THEN

INSTRUCTION<='1';

ELSE

INSTRUCTION<='0';

END IF;

END PROCESS;

END ONE;

器件原理图：

器件波形图：