数字钟最终程序
module shuzizhong(reset,Hour_Add,Min_Add,F64Hz,F2Hz,F512Hz,dout2, point, w);
input reset,Hour_Add,Min_Add,F64Hz,F2Hz,F512Hz;
output [6:0]dout2;
output [5:0]w;
output point;
wire yu1,yu2,c1,c2,m,s,f,a1,a2;
wire [5:0]d6;
wire [3:0]b1,b2,b3,b4,b5,b6,dout1;
xiaodou u12(.clk(F64Hz),.key(Min_Add),.cout(yu1));
xiaodou u13(.clk(F64Hz),.key(Hour_Add),.cout(yu2));
or and3(m,c1,yu1);
or and4(s,c2,yu2);
fenpin2to1 u1(.clkin(F2Hz),.clkout(f));
counter_6 u2(.clk(F512Hz),.dout(d6));
counter10 u3(.clk(f),.reset(reset),.cout(a1),.dout(b1));
counter6 u4(.clk(a1),.reset(reset),.cout(c1),.dout(b2));
counter10 u5(.clk(m),.reset(reset),.cout(a2),.dout(b3));
counter6 u6(.clk(a2),.reset(reset),.cout(c2),.dout(b4));
counter24 u7(.clk(s),.reset(reset),.dout1(b5),.dout2(b6));
select6to1 u8(.sin(d6),.ain(b1),.bin(b2),.cin(b3),.din(b4),.ein(b5),.fin(b6),.dout(dout1));
decoder7 u9(.data_in(dout1),.data_out(dout2));
xiaoshupoint u10(.f1hz(f),.d2(w[2]),.d4(w[4]),.out(point));
weixuan u11(.din(d6),.dout(w));
endmodule
module decoder7(data_in,data_out );
input [3:0] data_in ;
output [7:0] data_out ;
reg [7:0] data_out ;
always @(data_in)
begin
case (data_in )
4'b0000: data_out = 8'b00111111;
4'b0001: data_out = 8'b00000110;
4'b0010: data_out = 8'b01011011;
4'b0011: data_out = 8'b01001111;
4'b0100: data_out = 8'b01100110;
4'b0101: data_out = 8'b01101101;
4'b0110: data_out = 8'b01111101;
4'b0111: data_out = 8'b00000111;
4'b1000: data_out = 8'b01111111;
4'b1001: data_out = 8'b01101111;
default: data_out = 8'b00000000;
endcase
end
endmodule
module weixuan(din,dout);
input [2:0]din;
output [5:0]dout;
reg [5:0]dout;
always@(din)
begin
case(din)
3'd0:dout<=6'b111110;
3'd1:dout<=6'b111101;
3'd2:dout<=6'b111011;
3'd3:dout<=6'b110111;
3'd4:dout<=6'b101111;
3'd5:dout<=6'b011111;
default:dout<=6'b111111;
endcase
end
endmodule
module select6to1(sin,ain,bin,cin,din,ein,fin,dout);
input [2:0]sin;
input [3:0]ain,bin,cin,din,ein,fin;
output [3:0]dout;
reg [3:0]dout;
always@(sin)
begin
case(sin)
3'd0:dout<=ain;
3'd1:dout<=bin;
3'd2:dout<=cin;
3'd3:dout<=din;
3'd4:dout<=ein;
3'd5:dout<=fin;
endcase
end
endmodule
module counter10(clk,reset,cout,dout);
input clk,reset;
output[3:0] dout;
output cout;
reg[3:0] dout;
reg cout;
always@(posedge clk,posedge reset)
begin
if(reset)
begin
dout<=4'b0;
cout<=1'b0;
end
else
if(dout<9)
begin
dout<=dout+4'b1;
cout<=1'b0;
end
else
begin
dout<=4'b0;
cout<=1'b1;
end
end
endmodule
module counter6(clk,reset,cout,dout);
input clk,reset;
output[2:0] dout;
output cout;
reg[2:0] dout;
reg cout;
always@(posedge clk,posedge reset)
b
egin
if(reset)
begin
dout<=3'b0;
cout<=1'b0;
end
else
if(dout<5)
begin
dout<=dout+4'b1;
cout<=1'b0;
end
else
begin
dout<=3'b0;
cout<=1'b1;
end
end
endmodule
module counter_6(clk,dout);
input clk;
output[2:0] dout;
reg[2:0] dout;
always@(posedge clk)
if(dout<5)
dout<=dout+3'b1;
else
dout<=3'b0;
endmodule
module counter24(clk,reset ,dout1,dout2,cout);
input clk,reset;
output[3:0] dout1,dout2;
output cout;
reg[7:0] dout;
reg cout;
assign dout2=dout/10;
assign dout1=dout%10;
always@(posedge clk,posedge reset)
begin
if(reset)
begin
dout<=8'b0;
cout<=1'b0;
end
else
if(dout<23)
begin
dout<=dout+8'b1;
cout<=1'b0;
end
else
begin
dout<=8'b0;
cout<=1'b1;
end
end
endmodule
module xiaoshupoint(f1hz,d2,d4,out);
input f1hz,d2,d4;
output out ;
wire c;
or u1(c,f1hz,d2);
nand u2(out,d4,c);
endmodule
module fenpin2to1(clkin,clkout);
input clkin;
output clkout;
reg clkout;
always@(posedge clkin)
begin
clkout<=~clkout;
end
endmodule
module xiaodou(clk,key,cout);
input clk,key;
output cout;
reg cout,out_1,out_2;
always @(posedge clk)
begin
out_1<=key;
out_2<=out_1;
cout<=out_1&out_2;
end
endmodule