(总)基于Verilog的4位计数器源程序与testbench测试程序

1、简单4位计数器程序：

module count4(clk,cnt);

input clk;

output reg[3:0]cnt=4'b0;

always @(posedge clk)

begin

cnt<=cnt+1;

end

endmodule

测试程序：

`timescale 1 ns/10 ps

module test_count4();

reg clk=0;

wire [3:0]cnt;

count4 i1(.clk(clk),.cnt(cnt));

always #10 clk=~clk;

initial

begin

$monitor($time,,,"clk=%d cnt=%d",clk,cnt); #400 $stop;

end

endmodule

仿真波形：

2、异步清零4位计数器源程序

module count4_reset(clk,rst,cnt);

input clk,rst;

output reg[3:0]cnt=4'b0;

always @(posedge clk or negedge rst)

begin

if(!rst) cnt<=4'b0;

else cnt<=cnt+1;

end

endmodule

测试程序

`timescale 1 ns/10 ps

module test_count4_reset();

reg clk=0;

reg rst;

wire [3:0]cnt;

count4_reset i1(.clk(clk),.rst(rst),.cnt(cnt));

always #10 clk=~clk;

initial

begin

rst=0;

#20 rst=1;

#45 rst=0;

#10 rst=1;

end

initial

begin

$monitor($time,,,"clk=%d rst=%d cnt=%d",clk,rst,cnt);

#800 $stop;

end

endmodule

仿真波形

3、异步清零、计数使能控制的4位计数器

module count4_rst_en(clk,rst,en,cnt);

input clk,rst,en;

output [3:0]cnt;

reg [3:0]cnt;

always @(posedge clk or negedge rst)

begin

if(!rst) cnt<=0;

else if(en==1) cnt<=cnt+1;

end

endmodule

测试程序

`timescale 1 ns/10 ps

module test_count4_rst_en();

reg clk=0;

reg rst,en;

wire [3:0]cnt;

count4_rst_en i1(.clk(clk),.rst(rst),.en(en),.cnt(cnt));

always #10 clk=~clk;

initial

begin

rst=0;en=0;

#15 en=1;

#20 rst=1;

#20 en=0;

#20 en=1;rst=0;

#20 rst=1;

end

initial

begin

$monitor($time,,,"clk=%d rst=%d en=%d cnt=%d",clk,rst,en,cnt);

#800 $stop;

end

endmodule

仿真波形：

4、异步清零、计数使能、数据加载控制功能的4位计数器：

module count4_rst_en_load(clk,rst,en,load,data,cnt);

input clk,rst,en,load;

input [3:0]data;

output reg[3:0]cnt;

always @(posedge clk or negedge rst)

begin

if(!rst) cnt<=0;

else if(en==1)

begin

if(load) cnt<=data;

else cnt<=cnt+1;

end

end

endmodule

测试程序：

`timescale 1 ns/10 ps

module test_count4_rst_en_load();

reg clk=0;

reg rst,en,load;

reg [3:0]data;

wire [3:0]cnt;

count4_rst_en_load i1(.clk(clk),.rst(rst),.en(en),

.load(load),.data(data),.cnt(cnt));

always #10 clk=~clk;

initial

begin

rst=0;en=0;load=0;data=4'd6;

#20 en=1;

#20 rst=1;

#20 load=1;

#20 rst=0;

#20 rst=1;

#20 load=0;

end

initial

begin

$monitor($time,,,"clk=%d rst=%d en=%d load=%d cnt=%d",

clk,rst,en,load,data,cnt);

#800 $stop;

end

endmodule

仿真波形：