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A sample-and-hold circuit implemented with mixed MOS transistor channel length technique used in 16-bit 100-MS/s A/D converter

Ting Li*, Yuxin Wang, and Ruzhang Li

National Lab of Analog Integrated Circuits, Chongqing 400060, China

* Email: tingtingsr@https://www.360docs.net/doc/d310299942.html,

Abstract üThis paper discusses the design and implementation of a sample-and-hold circuit integrated into a high-speed and high-resolution A/D converter. In order to achieve the required speed and resolution, mixed MOS transistor channel length amplifier is used. The sample-and-hold circuit processes a differential 2.5-V p-p output signal swing and achieves 16-bit linearity with sampling frequency up to 100 MHz. Under these conditions, the total power consumption is 300 mW given by a single 3.3-V supply. The A/D converter is fabricated in a standard 0.35--m CMOS process technology, achieves 95.33-dBc spurious free dynamic range, 75.75-dBc signal-to-noise ratio for a 10.1-MHz input at -0.9dBFS at full sampling rate.

KeywordsüSample-and-hold, Mixed channel length technique

1.Introduction

The increasing popularity of digital signal processing in high-frequency applications requires the development of high-performance A/D converters. In many A/D converters, a sample-and-hold (SH) circuit is required to hold the analog signal for a certain period of time so that the A/D converter can perform the conversion. In a high-speed and high-resolution A/D converter, a wide -band high-dc-gain sample-and-hold amplifier (SHA) is needed. By using a single MOS transistor channel length, it is difficult to implement wide-band and high-dc-gain without compromise.

In this design, to overcome the above critical problem, a mixed MOS transistor channel length technique has been used in the implementation of the SHA in a SH circuit. The proposed SH circuit is applied to a 16-bit 100MS/s A/D converter in 0.35--m CMOS process.

2.Sample-and-hold architecture

Two differential SH architectures were investigated. The first architecture, referred to as a charge-transferring SH, acquires the input signal on the input capacitors during the sample phase, and transfers only the differential charge to the feed-back capacitors during the hold phase. The second architecture is, referred to as a flip-around SH, acquires the input on the input capacitors during the sample phase, and flips the same capacitors to the output during the hold phase.

The charge-transferring SH can handle a wide range of input signal common mode, has a flexible choose of SH gain and easy to get better SHA phase margin, but has larger capacitor induced noise and power consumption. The flip-around SH has lower capacitor induced noise and lower power consumption, but has worse input common-mode compliance and a fixed SH-gain of 1, and is hard to get better SHA phase margin.

To achieving lower capacitor induced noise and proper SH gain for better SNR and SHA phase margin at the proper power consumption, a mixed architecture is used

as shown in Fig. 1.

Figure 2. Schematic diagram of sample-and-hold circuit

C s1 and C s2 acquire the input signal during the sample phase, and transfer only the differential charge to the feed-back capacitors of C f1 and C f2. C f1 and C f2 acquire the input signal in the sample phase, and flip to the output during the hold phase. If C s1 is equal to C s2, and if C f1 is equal to C f2, then the SH gain (C s1+C s2+C f1+C fs)/(C f1+C f2) will be equal to 1.25 when C f1 and C f2 are four times as large as that of C s1 and C s2 . The classic bootstrap circuit is employed to keep the V GS

of the nMOS switching transistors M1, M2, M3 and M4 constant in the sample phase, and to keep the V GS of the nMOS switching transistors M5 and M6 constant in the hold phase.

978-1-4244-5798-4/10/$26.00 ?2010 IEEE

3.SHA design using mixed channel length technique The closed-loop structure of the sample-and-hold circuit requires a high-performance amplifier. On the one hand, the tradeoff between the close-loop-bandwidth and the dc-gain in the amplifier design results in a corresponding tradeoff between the speed response and the accuracy response in the hold phase; on the other hand, high-speed signals nonlinearity is minimized by having a large amplifier bandwidth and a linear gain. In this design, the large close-loop-bandwidth is preferred while the dc-gain has been chosen to satisfy 16-bit linearity in hold phase.

The amplifier used in the sample-and-hold is shown in Fig. 2. It consist of two amplification stages: the first stage is an nMOS input differential pair based low-gain wide-band pre-amplifier to provide large common-mode compliance, the second stage is a telescopic amplifier which offers excellent dc-gain and bandwidth at differential 2.5-V p-p output signal swing. For a standard 0.35--m process technology, it is difficult to achieve large close-loop-bandwidth to satisfy 100MHz sampling rate and to achieve high dc-gain to satisfy 16-bit linearity simultaneously while processing a differential 2.5-V p-p output signal swing and driving more than 8pF load at

3.3-V supply.

Figure 2. Sample-and-hold amplifier

In this implementation, the telescopic stage has an

improved dc-gain as well as a close-loop-bandwidth by

using a mixed MOS transistor channel length technique.

Firstly, in order to enhance the dc-gain of the telescopic

stage to satisfy 16-bit linearity in hold phase while

processing a differential 2.5-V p-p output signal swing and

driving more than 8pF load at 3.3V supply, in addition to

the employment of the gain-boosting circuit of the

pMOS and nMOS cascode transistors, the cascode

nMOS transistors, the pMOS transistors and the

transistors in the gain-boosting circuits use deliberately

0.5--m channel length devices which have larger output

resistances than the 0.35--m channel length devices.

Secondly, in order to get enough wide

closed-loop-bandwidth of the SHA, the input differential

pairs and the tail current sources of the two amplification

stages use 0.35--m channel length devices which have

smaller gate capacitance based on the same

transconductances or higher transconductances based on

the same device width than 0.5--m channel length

devices.

Simulations show that the proposed amplifier achieves

about 65.8e phase margin, 100.5-dB dc gain, and

730MHz close-loop-bandwidth while maintaining a

differential 2.5-V p-p output signal swing and driving

more than 8pF load at 3.3-V supply.

4.Experimental results

The sample-and-hold circuit mentioned above has been

used in a 16-bit 100MS/s A/D converter, and is

processed in standard 0.35--m CMOS process

technology. The micrograph of the fabricated chip is

shown in Fig. 3. The sample-and-hold circuit area is

0.58mm2

and consumes 300mW of power.