力传感器及电子秤设计文献翻译—输入输出访问

Input/Output Accessing

In this article, we will look at the three basic methods of I/O accessing －programmed I/O, interrupt-driven I/O, and direct memory access (DMA). The key issue that distinguishes these three methods is how deeply the processor is involved in I/O operations. The discussion emphasizes interrupt-driven I/O, because it is based on the concept of interrupt handling, which is a general problem that goes beyond Input/Output operations. The study of interrupt handling also aids in understanding the general concept of exception processing, which is an important issue not only for I/O, but also for interfacing a computer with other system control functions.

Addressing I/O Registers

Input/Output devices communicate with a processor through Input/Output ports. Through the input ports, s processor receives data from the I/O devices. Through the output ports, a processor sends data to the I/O devices. Each I/O port consists of a small set of registers, such as data buffer registers (the input buffer and/or the output buffer), the status register, and the control register. The processor must have some means to address these registers while communicating with them. There are two common methods of addressing I/O register －memory-mapped I/O and direct I/O.

1. Memory-Mapped I/O

Memory-mapped I/O maps the I/O registers and main memory into a unified address space in the computer system. I/O registers share the same address space with main memory, but are mapped to a specific section that is reserved just for I/O. Thus, the I/O register can be addressed in ordinary memory reference instructions as if they are part of the main memory locations. There are no specially designed I/O instructions in the instruction set of the system. Any instruction that references a location in this area is an I/O instruction. Any instruction that can specify a memory address is capable of performing I/O operations. The Motorola MC68000 is an example of a computer system that uses this addressing method.

2. Direct I/O

The method of addressing I/O registers directly without sharing the address space with the main memory is called direct I/O or I/O-mapped I/O. In other words, I/O registers are not mapped to the same address space with the main memory. Each I/O register has an independent address space. As a result, instructions that reference the main memory space cannot be used for Input/Output. In the instruction set of the computer system, special I/O instructions must be designed for I/O operations. In these I/O instructions, distinct I.D. numbers must be used to

address different I/O communication channels (i.e., I/O ports). They are called port numbers. The I/O registers of an I/O port are connected to the system I/O bus, through which the processor can reference the I/O registers directly to send/receive data to/from an I/O device. An I/O port number is not from the same address space as main memory. The Pentium is an example of a computer system that uses the direct I/O addressing method. It has a 64 GB memory address space (32 address bits) and, at the same time, a 64 KB I/O address space (16 bits I/O address/port number).

We can compare memory-mapped I/O and the direct I/O and the direct I/O as follows:

●Memory-mapped I/O uses ordinary memory reference instructions to access I/O, so it provides flexibility for I/O programming and simplifies I/O software. Direct I/O does not provide any flexibility in I/O programming, since only a small set of special I/O instructions are allowed to reference I/O registers.

●for memory-mapped I/O, the processor uses the same address lines to access all the addressable I/O registers and the same data lines to send/receive data to/form these registers. This simplifies the connection between I/O port and the processor, and thus leads to a low-cost hardware design and implementation. For direct I/O, the connection between I/O ports and the processor may be more expensive. This is because either (1) special hardware is needed to implement separate I/O address lines or (2) when memory address lines are used for I/O; a special flag is needed, indicating that the requested address is for an I/O operation.

●In spite of the advantage of using ordinary memory reference instructions to access I/O registers, memory-mapped I/O may complicate the control unit design in regards to the implementation of I/O-related instructions. This is because usually the I/O bus cycles need to be longer than the equivalent memory bus cycles, and this means that the design of different timing control logic is required. This can be used to explain why memory-mapped I/O benefits programmers, but not electronics engineers.

●Direct I/O addressing has another advantage over memory-mapped I/O in that low-level debugging on a differentiated addressing system may be easier, because break-points or error traps can be imposed more generally.

●with memory-mapped I/O, I/O registers share the same address space with main memory; hence, the memory space available for programs and data is reduced. For direct I/O addressing, I/O does not share memory space with main memory, and a single contiguous memory space can be maintained and used by programmers.

Programmed I/O

Programmed I/O requires that all data transfer operations be put under the complete control

of the processor when executing programs. It is sometimes called polling, because the program repeatedly polls (checks) the status flag of an I/O device, so that its input/output operation can be synchronized with the processor. A general flowchart of such a program is shown in Figure 1. The program continuously polls the status of an I/O device to find out whether (1) data is available in the input buffer or (2) the output device is ready for receiving data from the processor. If the status shows “available” the program will execute a data transfer instruction to complete the I/O operation; otherwise, the busy status of the I/O device will force the program to circulate in a busy-waiting loop until the status becomes available. Such a busy-waiting loop, which continuously checks the status of data availability (for input) or device availability (for out-put), forms the typical program structure of programmed I/O. It is this time-consuming busy-waiting loop that wastes processor time and makes programmed I/O very inefficient. The processor must be involved continuously in the entire I/O process. During this time interval, the processor cannot perform any useful computation, but only serve a single I/O device. For certain slow I/O devices, this busy-waiting loop interval may be long enough that the processor could execute millions of instructions before the I/O event occurs, e.g., a key stroke on a keyboard.

The operational mode lf programmed I/O stated above is characterized by the busy waiting loop of the program, during which the processor spends time polling an I/O device. Because of the dedication of the processor to a single task, this mode of programmed I/O is called dedicated polling or spin polling. Although dedicated polling is highly inefficient, sometimes it is necessary and even unavoidable. In a particular case, if an urgent event needs an immediate response without delay, then dedicated polling by a dedicated processor may be the best way to handle it. Once the expected event happens, the processor can tract to it immediately. For example, certain real time systems (e.g., radar echo processing systems) require a reaction to incoming data that is so quick that even an interrupt response is too slow. Under such a circumstance, only a fast dedicated polling loop may suffice.

Another mode of operation of programmed I/O is called intermittent polling or timed polling. In this mode, the processor may poll the device at a regular timed interval, which can be expected or prescheduled. Such a device can be found in many embedded systems where a special-purpose computer is used for process control, data acquisition, environmental monitoring, traffic counting, etc. these devices, which measure, collect, or record data, are usually polled periodically in a regular schedule determined by the needs of the application. Such a method of intermittent polling can help save time lost in spin polling and avoid the complexity of interrupt processing. However, it should be noted that intermittent polling may not be applicable in some special cases, in which there is only one device to be polled and the correct polling rate must be achieved with the

assistance of an interrupt-driven clock. Using timed polling in this case would result in simply swapping one interrupt-driven clock. Using time polling in this case would result in simply swapping one interrupt requirement for another.

Interrupt-Driven I/O

Interrupt-driven I/O is a means to avoid the inefficient busy-waiting loops, which characterize programmed I/O. Instead of waiting while the I/O device is busy doing its job of input/output, the processor can run other programs. When the I/O device completes its job and its status becomes “available”, it will issue an interrupt request to the processor, asking for CPU service. In response, the processor suspends whatever it is currently doing, in order to attend to the needs of that I/O device.

In respond to an interrupt request, the processor will first save the contents of both the program counter and the status register for the running program, and then transfer the control to the corresponding interrupt service routine to perform the required data input/output operation. When the interrupt service routine has completed its execution and if no more interrupt requests are pending, the processor will resume the execution of the previously interrupted program and restore the contents of the statuses and program counter. The processor hardware should check the interrupt request signal upon completion of execution of every instruction. If multiple devices issue their interrupt requests at the same time, the processor must use some method to choose which one to service first, and then service all the other interrupt requests one by one by order of priority. Only after all the interrupt requests have been serviced will the CPU return to the interrupted user program. In this way, the processor can serve many I/O devices concurrently and spend more time doing useful jobs, rather than running a busy-waiting loop to serve a single device. Therefore, interrupt I/O is very effective in handling slow and medium-speed I/O devices. Furthermore, the concept of an interrupt can be generalized to handle any event caused by hardware or software, internally or externally. This general problem is referred to as exception processing.

If multiple interrupt requests are issued by different devices at the same time, the processor should have some means to identify the interrupt sources and handle their interrupt requests by some policy, typically by priority. Only one request with the highest priority can be serviced at the current time, while all others are put into a waiting queue. Upon the completion of the service performed by an interrupt service routine, the processor should search the waiting queue for all the pending interrupt requests, old or new, and continue to service them one by one according to their priorities, until the queue becomes empty. Only when all the pending interrupt requests have been

serviced can the interrupted user program be resumed. Although this case contains multiple interrupt requests, it is still a simplified case. The assumption is that all the interrupt service routines must be completed without further interruption 9 (or so-called preemption) once they have been started one after another by the processor. An interrupt process satisfying this assumption is called a non-preemptive interrupt. In real-life circumstances, the process of interrupt-driven I/O can be more complicated than this simplified case. Each interrupted service routine running in the processor can be preempted (interrupted) by a newly arrived interrupt request, which has a higher priority than the current one. This circumstance will cause the main program and all the requested interrupt service routines to have a complicated interrelationship. An interrupt process that allows an interrupt service routine to be preempted by a higher-priority interrupt service routine is called a preemptive interrupt.

Direct Memory Access

Although interrupt I/O is more efficient than the programmed I/O, it still suffers from a relatively high overhead with respect to handling the interrupt. This overhead includes resolving the conflict among multiple interrupt requests, saving and restoring the program contexts, pooling for interrupt identification, branching to/from the interrupt service routine, etc. Using an interrupt is a wasteful activity that can take several microseconds to complete.

Direct memory access(DMA) is a method that can input/output a block of data directly to/form main memory with a speed of one data item per memory cycle, without continuous involvement of the processor. The entire process is implemented by the hardware of a DMA controller, which takes the place of the processor and communicates directly with main memory. As a result, the block diagram of the computer system changes form processor-centered to memory-centered. Hence, from the viewpoint of I/O processing, the processor is no longer the center of a computer, but rather a partner with which the I/O subsystem competes for memory bus cycles to input/output data item to/from main memory. However, a DMA controller is designed to exchange data in blocks, so it works well with the large-volume high-speed block-oriented I/O devices, such as high-speed disks and communication networks.

The DMA controller can work in two different modes. Normally, it works concurrently with the processor, competing for individual memory bus cycles to input/output successive words of a data block. If the I/O speed is not very high, the memory accesses by the processor and the DMA controller can be interwoven. Time is accrued on a cycle-by-cycle basis. Neither the processor nor the DMA controller can continuously use all the memory bus cycles during any time interval. This operational mode of the DMA controller is called cycle stealing, so named because the I/O

subsystem is essentially “stealing” m emory bus cycles from the processor. This mode integrates the DMA memory accesses into CPU activity and avoids serious disruption of the main processing. Alternatively, for even higher I/O transfer speed, DMA operations require bus time, which can be allocated in block of cycles known as bursts. During a burst of memory cycles, the processor is totally excluded from accessing memory. The DMA controller is given exclusive access to main memory and continuously inputs/outputs blocks of data at a speed comparable to the memory speed. This operational mode of the DMA controller is called the block or burst mode. A DMA controller designed for this mode of operation usually incorporates a data storage buffer with a capacity matching the size of at least one data block. When the DMA controller utilizes the memory bus, it can transfer a data block directly between its data storage buffer and main memory.

The following registers are necessary for the DMA to transfer a block of data:

● Data buffer register (DBR)－it can be implemented as two registers, one for input

and the other for output, or even a set of registers comprising a data storage buffer.

● DMA address register (DAR)－used to store the starting address of the memory

buffer area where the block of data is to be read or written.

● Word counter (WC)－the contents specify the number of words in the block of data

remaining to be transferred and it is automatically decremented after each word is transferred.

● Control/status register (CSR)－used by the processor to send control information to

the DMA controller and to collect the statuses and error information of the DMA controller and the I/O devices attached to it.

Using these registers, the DMA controller knows the addresses of the source and destination data blocks, as well as the quantity of data to be transferred. Once the DMA controller acquires the memory bus, the block transfer operation can be performed autonomously using the information contained in these registers, without the continuous involvement of the processor.

Besides the above-listed registers, the DMA controller should contain the control logic of a bus request facility, which performs bus arbitration using the signals of DMA request (DMAR) and DMA acknowledge (DMAA). Bus arbitration is the process of resolving the contention among multiple concurrently operating DMA controllers for acquisition of the memory bus. The selection of the bus master is usually based on the priorities of various DMD devices. Among different DMA devices, the priority order are arranged by the degree urgency of the devices receiving the DMA service, i.e., according to their speed requirements. There are two approaches to bus arbitration for DMA devices －centralized and distributed －which are similar to the