4位十进制计数器(数码管显示)

module count10(rst,mclk,an,ag);
input rst,mclk;
//reg [3:0] out0,out1,out2,out3;
reg cn1,cn2,cn3;
reg [3:0] out0,out1,out2,out3;
wire clk1,clk2;
reg [24:0] count;


output [3:0] an;
output [7:0] ag;



always @ (posedge mclk)
count=count+1;
assign clk1=count[23];
assign clk2=count[12];

always @(posedge clk1 or negedge rst)
begin
if (!rst) begin
out0 <= 0;
cn1 <= 0;end
else begin
if(out0==4'b1001) begin
out0<=0;
cn1<=1; end
else begin
out0<=out0+1;
cn1<=0;
end
end
end

always @(posedge cn1 or negedge rst)
begin
if (!rst) begin
out1 <= 0;
cn2 <= 0;end
else begin
if(out1==4'b1001) begin
out1<=0;
cn2<=1; end
else begin
out1<=out1+1;
cn2<=0;
end
end
end



always @(posedge cn2 or negedge rst)
begin
if (!rst) begin
out2 <= 0;
cn3 <= 0;end
else begin
if(out2==4'b1001) begin
out2<=0;
cn3<=1; end
else begin
out2<=out2+1;
cn3<=0;
end
end
end


always @(posedge cn3 or negedge rst)
begin
if (!rst)
out3 <= 0;
else begin
if(out3==4'b1001)
out3<=0;
else out3<=out3+1;end
end

ledshow led(.rst(rst),.clk(clk2),.an(an),.ag(ag),
.out0(out0),
.out1(out1),
.out2(out2),
.out3(out3));

endmodule


module ledshow(rst,clk,an,ag,out0,out1,out2,out3);
input rst,clk;
input [3:0] out0,out1,out2,out3;
output [3:0] an;
output [7:0] ag;

reg [3:0] digit;
reg [3:0] an_reg;
reg [7:0] ag_reg;
reg [1:0] state,next_state;

assign an=an_reg;
assign ag=ag_reg;





parameter S_0=2'b00,
S_1=2'b01,
S_2=2'b10,
S_3=2'b11;



always @ (posedge clk or negedge rst)
begin
if(!rst) begin
state<=S_0;
//an_reg<=4'b1000;
end
else
begin
state<=next_state;
end
end


always @(state)
begin
next_state=S_0;
case(state)
S_0: begin
digit=out0;
an_reg=4'b1000;
//if(out0==4'b1001)begin
next_state=S_1;end
/*else
next_state=S_0;
end*/

S_1: begin
digit=out1;
an_reg=4'b0010;
//if(out1==4'b1001) begin
next_state=S_2;end
/*else
next_state=S_1;
end*/

S_2:begin
digit=out2;
an_reg=0100;
//if(out2==4'b1001) begin
next_state=S_3;end
/*else
next_state=S_2;
end*/

S_3:begin
digit=out3;
an_reg=0001;
//if(out2==4'b1001) begin
next_state=S_0;end
/*else
next_state=S_3;
end*/

endcase
end

always @(digit) //让数码管显示digit的数，这部分应该没问题
begin
case(digit)
4'b0000: ag_reg<=8'b00111111;
4'b0001: ag_reg<=8'b00000110;
4'b0010: ag_reg<=8'b01011011;
4'b0011: ag_reg<=8'b01001111;
4'b0100: ag_reg<=8'b01100110;
4'b0101: ag_reg<=8'b01101101;
4'b0110: ag_reg<=8'b01111101;
4'b0111: ag_reg<=8'b

00000111;
4'b1000: ag_reg<=8'b01111111;
4'b1001: ag_reg<=8'b01101111;
default: ag_reg<=8'b00111111;
endcase
end
endmodule